ANALOG DEVICES EE-290 Service Manual

Engineer-to-Engineer Note EE-290

Technical notes on using Analog Devices DSPs, processors and development tools

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Managing the Core PLL on SHARC® Processors

Contributed by Jey anthi J egade e san and Mite sh Moonat Rev 5 – March 6, 2012

Introduction

This EE-Note describes how to program the core phase-locked loop (PLL) on ADSP-2126x, ADSP­2136x, ADSP-2137x, ADSP-2146x, ADS P -2147x and ADSP-2148x SHARC® pro ce ssors. This document
also provides example code for programming the PLL and discusses possible problems that can occur due
to incorrect progr amming. Lastly, it provides debug techniques for cor r ect PLL handling.

C callable library functions for pr ogr amming t he PLL on all pr ocessors are also pr ovide d wit h this EE­Note. This lib ra ry f unc t ion can be added to the C run-time library and called from VisualDSP++® project
files.

Programming the P LL on SHARC Proce ssors

ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, ADSP-2147x and ADSP-2148x SHARC
processor s use a PLL to provide clocks that switch at higher frequencies than the clock source (CLKIN).
The PLL derives the clock for the pro cessor's peripherals in addition to the pro cessor's core and internal
memory.

The processor 's CLK_CFG1-0 pins select the core clock (CCLK) to CLKIN ratio during power-up in hardware.
For the ADSP -2147x and ADSP-2148x processors, ratios of 32:1, 16:1, and 8:1 can be selected using the

CLK_CFG pins during reset. For the ADSP-2136x, ADSP-2137x, and ADSP-2146x processors, ratios of

32:1, 16:1, and 6:1 can be selected using the CLK_CFG pins during reset. For t he ADSP-2126x processors,
ratios of 16:1, 8:1, and 3:1 can be selected using the CLK_CFG pins during reset.

The power management co ntrol register (PMCTL) a llo w s yo u t o pro gr a m t he P L L dy na mica lly in s o ftw a r e.
The PMCTL can be used to select CCLK-to-CLKIN rat ios that ar e not suppo rt ed by hardware pins. It can also
pr ovide po we r sa vings in appl icat ion s th at h ave t ime pe rio ds dur in g whic h th e full in str uct ion rat e is n ot
needed. The CCLK rate can be decreased during periods of less-intensive pro cessing.

Th e P L L b lo ck di a gr a m in Figure 1 sho w s an input di vider , mul t ipl ie r , an d a di vider fo r derivin g t he CCLK.

Figure 1 shows the PLL block diagram for the ADSP-21367, ADSP-21368, ADSP-21369 (hereafter

referred to as ADSP-21368 processors) and ADSP-2137x processors. The PLL block diagram for the
ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, ADSP-21366 (hereafter r eferred to as ADSP­21362 processors), a nd ADSP-2126x processo r s is functionally the same with the following differences:

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