Analog Devices EE261v01 Application Notes

Engineer-to-Engineer Note EE-261

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Understanding Jitter Requirements of PLL-Based Processors

Contributed by Boris Lerner and Aaron Lowenberger Rev 1 – January 20, 2005

Introduction

With the advance of faster processors that
require faster lines of communication,
understanding and characterizing clock jitter has
become more important.

Jitter occurs in many different parts of digital
applications. Jitter of data with respect to clock
in synchronous protocols is one example; jitter of
the signal itself in CDR (clock data recovery)
applications is another.

This EE-Note describes jitter issues of the clock
from which PLL-based processors derive timing.
This document analyzes the given clock's jitter
with respect to an ideal clock, only as far as a
processor’s tolerance requires. This document is
intended for hardware design engineers
responsible for choosing the components to
satisfy a processor’s jitter requirements.

The specific processor being analyzed in this EE­Note is the ADSP-TS201S TigerSHARC®
processor. Some portions of this EE-Note apply
to jitter in general; other portions apply
specifically to our case in question.

Unfortunately, unlike more traditional data sheet
parameters like setup and hold, analyzing
acceptable system jitter is not as simple as
merely ensuring that specification numbers are
met. There are many ways to measure jitter; on
top of that, there are infinitely many different
kinds of jitter and the system may behave
differently depending on the jitter type. Thus,
before doing any analysis whatsoever, it is

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important to supply all of the jitter terms and
definitions, first intuitively what they mean and
then the correct mathematical definition.

Terminology

We consider an ideal clock that is being jittered
(i.e., the clock’s edges experience movement
with respect to ideal locations).

The jitter of a particular waveform can be
measured/characterized as period, cycle-to-cycle,
or time interval error (TIE).

Period jitter. This measures the maximum
deviation of each single period of the jittered
clock from that of the ideal clock. In Figure 1, if

k

=

maxJitter TIE (3)

=

thenclock, Ideal of Period

{}

−=

k

,...3,2,1,0

=

{}

T

k

,..3,2,1,0

. maxJitter Period (1)

CP

0

1

+

,...3,2,1,0kkk

PP −=

C

0

Cycle-to-cycle jitter. This measures the
maximum deviation of each single period of the
jittered clock from the previous period of the
same clock. In Figure 1,

Time interval jitter. This mea sures t he maxi mum
deviation of the edge (Figure 1 shows this
relating to the rising edge; it can also relate to the
falling edge) of the jittered clock from the
corresponding edge of the ideal clock. In

Figure 1,

=

k

}

. maxJitter Cycle-to-Cycle (2)

(

(

−

=

()(

()(

=−=

a

Here we presume that at time t=0 of the
measurement, the edge of the jittered clock
aligns with the edge of the ideal clock. Note that
this is not just a simple aberration of the edge of

Figure 1. Jitter Definitions

It is time to put clock and jitter under a more
precise mathematical definition. We define the
ideal clock of period T and constant amplitude A
as the following function of time t:

⎧
⎪

⎪

(4)

Here, T is measured in units of time (usually
seconds) and A is measured in volts. Amplitude
of the ideal clock is irrelevant to the discussion
about jitter, so in all that follows we presume that
the clocks have unit amplitude and we consider
them as parameterized by T, (i.e., their period):

(5)

We also define

with jitter J

function of time J(t) (delay can be positive or
negative), mathematically:

Understanding Jitter Requirements of PLL-Based Processors (EE-261) Page 2 of 9

()

tC

=

,

T

⎨

TA

⎪
⎪

⎩

⎧
⎪

⎪

()

=

tC

⎨
⎪

⎪

⎩

()

tC

TJ ,

(t), as the ideal clock delayed by a

if

1

⎛

if 0

⎜
⎝

if 1

⎛

if 0

⎜
⎝

, the clock of period T

⎞

+

⎟

2

⎠

⎛
⎜

⎝

1

⎞

+

⎟

2

⎠

1

⎛
⎜

⎝

+<≤

⎞

TntnTA

+<≤

⎟

2

⎠

()

1

+<≤

1

⎞

TntnT

⎟

2

⎠

()

TntTn

1

+<≤

TntTn

the jittered clock from the nearest edge of the
ideal clock, because the edge of the jittered clock
may have “wandered” away from the edge of the
ideal clock by more than a full cycle period.

)()

(6)

,

There are several intuitive reasons for defining
jitter this way. The most compelling reason is
that jitter is usually generated in a laboratory by
applying a function generator signal to a delay
input of a pulse generator. This is the way
processor manufacturers test susceptibility to
jitter.

For simplicity we define
(7)

Note that G(t) matters only at points

These points are precisely where the clock
changes from low to high or high to low (thus
“r” for rising and “f” for falling edges). Since
what G does outside of these discrete points is
completely immaterial, we can presume that G
(and, thus J) are infinitely differentiable at all
points.

Since these definitions are mathematical in
nature and we must maintain real-life
plausibility, it is safe to assume that G must be a

TTJ

)()

)

tJtCtC

,

() ( )

and whereor TkfGkTrGfrt

TTJ

kkkk

)

. that so , :

tGCtCtJttG

1

⎛
⎜

⎝

⎞

+===

⎟

2

⎠

.

(

ε

ε

ε

(

π

=

()(

=

a

uniformly increasing function (that is,

() ()

the order of the edges, only their locations.
Going back to Figure 1, we see that

Thus, these definitions naturally lend themselves
to specifying jitter as TIE (simply because the
maximum amplitude of J(t) is the TIE jitter, as
defined in equation (3)). Unfortunately, clock
driver manufacturers do not typically specify
jitter as TIE. Thus, it becomes important to relate
different types of jitter with mathematical
formulas. This is the main reason for this
application note.

tGtGtt <⇒< , since G cannot change

2121

)

kTJTk= .

Jitter Examples

Let’s hesitate from this mild mathematical
onslaught and examine different examples of
jitter as consequences of our definitions.

T

In fact, its period is

Jitter Period

Intuitively, function J(t) is slowly increasing (or
decreasing, depending on the sign of epsilon),
and the edges shift uniformly. Note that infinite
TIE jitter implies that this jitter cannot be
generated by laboratory setup described above; it
would require the function generator to output a
signal of infinite amplitude. For the same reason,
this type of jitter does not occur in real-life
systems, so we will restrict our attention to jitter
of finite amplitude.

Example 3

P

k

T

=

ε

−

. Jitter TIE

∞=

, the same for all k.

ε

−=1

T

ε

T

=−

0, Jitter Cycle-to-Cycle

=

,

ε

11

−

Example 1

()

=

tJ

,

ε

() ( )

,

Period Jitter = 0
Cycle-to-Cycle Jitter = 0
TIE Jitter =

Example 2

()

ttJ

=

TTJ

,

ε

−=

tCtC

ε

() ( )()

,

ε

tCtC

−=

TTJ

)

This type of jitter is appropriately called the

sinusoidal jitter of frequency

Then number. real small a is where

phase a is which ,

clock. ideal original theofshift

Then number. real small a is where

jitter (which, as noted before, is the maximum
amplitude of J) is A. Deriving period and cycle­to-cycle jitter is not as trivial as in Example 1,
and derivation of period jitter will be done in a
following section.

Example 4

tCtJ

TA0,

and amplitude
the original clock by
Thus, provided that

T,

Period Jitter =
Cycle-to-Cycle Jitter =
TIE Jitter =

ofclock idealanother is which , 1

)2sin(

tfAtJ

0

f . In this case, TIE

0

)

, another ideal clock of period T0

A. It is easy to see that J(t) delays

A or does not delay it at all.

T

is reasonably smaller than

0

A

A

A

frequency. )0 (ifhigher or )0 (iflower

<>

εε

Understanding Jitter Requirements of PLL-Based Processors (EE-261) Page 3 of 9