Analog Devices EE255v01 Application Notes

Engineer-to-Engineer Note EE-255

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Technical notes on using Analog Devices DSPs, processors and development tools

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Porting PC-Based MP3 Player Software to ADSP-21262 SHARC®
Processors

Contributed by Srinivas K. and Kunal Singh Rev 1 – November 16, 2004

Introduction

ADSP-21262 devices are a members of the third
generation of SHARC® family of processors.
ADSP-21262 processors offer SIMD architecture
and are equipped with powerful DMA
engines,ensuring high bandwidth data transfers
to and from the processor. Data transfers are
completely transparent to the processor core.
ADSP-21262 processors operate up to 200 MIPS
and provide several peripherals (e.g., SPORTs,
PP, SPI, IDPs) that are well suited for audio
applications.

MP3 is a standard for digitally compressed
music. This compression algorithm is capable of
up to 10:1 compression with no noticeable loss in
quality of the audio data. MP3 (short for
MPEG3) stands for Motion Picture Experts
Group, Audio Layer 3. MP3 is becoming an
increasingly popular way to store audio in
electronic format. An MP3 decoder reads the
compressed data from the storage media and
performs various decoding steps to obtain the
raw audio data. This audio data is in PCM audio
format, which can be stored on storage media or
played to an audio output device (speaker) in real
time.

This application note is based upon experience
gained while porting pure PC-based C code for
an MP3-decoder to ADSP-21262 processors
using the VisualDSP++® 3.5 tools suite. The
target platform was the ADSP-21262 EZ­KIT Lite® evaluation system. This application

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note summarizes key considerations involved in
porting general PC-based C-code to ADSP­21262 processors.

Data I/O - PC versus SHARC

As depicted in Figure 1, general PC-based code
primarily uses file I/O for data input and output
operation. The data may be stored in the form of
the files on the PC's hard drive. The file I/Os on
PC are supported by the OS running on the PC.
For example, MP3 files for an MP3 decoder may
be stored on the PC's hard drive.

MP3-Decoder running on

the PC

Compressed Decoded
MP3 Music PCM audio

Music.mp3 Music.dat

PC Hard Disc

Figure 1. Data I/O Scheme for a PC-based System

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Unlike a PC environment, the data on the
embedded processor would be available from an
external device (e.g., memory or a Host device).
The data from the external device would be
transferred in and out of the processor through its
peripheral. Figure 2 depicts the data I/O scheme
for an MP3 decoder ported onto an ADSP-21262
processor.

ADSP-21262

Core

Processor

DMA Processor

Parallel Port SPORT

FLASH

Memory

Figure 2. Data I/O Scheme for the SHARC-based
MP3 Decoder

Audio

CODEC

can be obtained, and the information can be
stored in an Excel spreadsheet.

Using the above profile, identify the functions
that consume the most MIPS. Devote your
efforts toward optimizing these functions. Don't
bother with the functions that require fewer
MIPS.

The following paragraphs summarize different
techniques that may be used to optimize the
different code modules.

Table 1 shows the instruction count for various

functions optimizing the MP3 code.

Function Cycle Count

Huffman Decode 82327

De-quantize Sample 239079

Anti_alias 4292

Inverse MDCT 52770

Hybrid Synthesis 1201638

Sub-band Synthesis 186984

Table 1. Instruction Count for Various Functions
Measured Before Optimization

The first task in porting the PC-based code to the
embedded platform, is to replace the file I/Os in
the PC code with the peripheral-based I/Os on
the SHARC processor.

Using DMA Engines

The data I/O operations through the peripherals
can be performed in core mode or in DMA mode.
For core-mode data transfers, the processor must

Code Profiling

execute a read/write instruction to an address to
which the particular peripheral has been mapped.

The next step is to obtain an estimate of the
MIPS consumption. The optimization process

These transfers involve one instruction cycle for
ever data transfer.

can be an iterative procedure where MIPS for the
different functions would be measured, changes
would be made to the code structure, and the
effect on the MIPS utilization would be
evaluated.

For DMA-mode data transfers, the SHARC
processor's I/O handles all of the data transfers.
The core processor needs only to initialize the
DMA control/parameter registers with
appropriate values, which may involve only a

The first step in optimization is code profiling.
The entire code is split into a set of smaller
modules for analysis. The benchmarks (in terms
of MIPS consumed) for these different modules

Porting PC-Based MP3 Player Software to ADSP-21262 SHARC® Processors (EE-255) Page 2 of 7

few instructions cycles. Thus, while using the
DMA based transfers, the processor core is
relieved of the instruction penalties that would
have occurred with core-mode transfers. The

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DMA scheme is particularly suitable for real­time applications in which huge amounts of data
must be moved in and out of the processor in real
time.

ADSP-21262 processors offer powerful DMA
engines to perform data transfers across:

 Internal and external memory
 Internal memory and an external peripheral

The above data transfers are completely
transparent to the core.

Parallel Data Fetch and SIMD

ADSP-21262 processors offer dual data fetches
and a MAC operation in a single cycle. The
internal bus architecture of the ADSP-21262
processor consists of separate PM and DM buses.
In normal scenarios, the PM bus fetches
instructions from Program Memory and the DM
bus reads/writes data from Data Memory. While
executing computation instructions with dual
data fetch, one operand is fetched on the PM bus
and the second operand is fetched on the DM
bus. Having the executed instructions available
in the Instruction Cache (so instruction fetches
are not needed and the PM bus is free to access
data) is a prerequisite for the above operation to
complete in a single cycle.

Instructions involving dual operands are
encountered frequently in typical signal­processing code. Some examples include FIR/IIR
filter loops, DCT, FFT, and other transforms.

The above routines involve MAC operations on
two vectors. The operations are performed in a
loop (so all instructions are moved to Instruction
Cache during the first execution of the loop, and
no instruction fetches are required for subsequent
loop iterations). If the two data vectors are
located in different memory blocks (PM and
DM), it may be possible to use a dual fetch in a
single cycle.

Another important feature of the ADSP-21262
processor is its SIMD architecture. The ADSP­21262 has two parallel compute units which can
execute same instructions on different data sets
in parallel.

Consider the following multiplication loop:

float operand1[1024];

float operand2[1024];

float result;

{

int j;

result = 0;

for (j= 0; j<1024; j++)

{

result += operand1[j] *

operand2[j];

}

}

Listing 1. Multiplication Loop Without Optimization

In the absence of a dual data fetch, the inner
multiplication loop in the above example would
require 2048 cycles to finish the execution. This
is because the fetching of operand1 and operand2
for each instruction requires a total of two cycles.

The above code structure can be modified such
that one of the operands lies in the PM block.
With the above modification, the two operands
can be fetched in a single cycle. Since the
multiplication is being performed within a loop,
the instruction would get cached after the first
execution, so that processor can fetch the two
operands in a single cycle.

float PM operand1[1024];

// the “PM” command would place
operand1

// in PM

float operand2[1024];

float result;

{

Porting PC-Based MP3 Player Software to ADSP-21262 SHARC® Processors (EE-255) Page 3 of 7