Analog Devices EE234v01 Application Notes

Engineer-to-Engineer Note EE-234
a
Technical notes on using Analog Devices DSPs, processors and development tools
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Interfacing T1/E1 Transceivers/Framers to Blackfin® Processors via the Serial Port
Contributed by K. Unterkofler and T. Lukasiak Rev 1 – May 11, 2004

Introduction

This EE-Note describes how to interface Blackfin® processors to standard T1 or E1 encoded signals. The proposed template assumes that a Blackfin processor is functionally located between two T1/E1 streams to perform the required processing, such as line echo canceling. However, the Blackfin processor can be adapted easily to other functional architectures. As shown in this EE-Note, most standard backplane PCM data streams interface directly to the processor’s serial port(s), without any external hardware.
This document provides schematics, layout suggestions, and a software framework for receiving, processing, and transmitting PCM streams between two T1/E1 transceivers/ framers.
The chosen framing device is the PMC-Sierra PM4351 COMET. The PCM streams are connected to one of the processor’s synchronous serial ports (SPORTs), which can handle two input streams and two output streams. The COMET is configured via the processor’s asynchronous memory interface in the external bus interface unit (EBIU).
The schematics are intended to be for a daughter­board that plugs into an EZ-KIT Lite™ evaluation system available from Analog Devices, Inc.
The application was implemented on and is described herein for the ADSP-BF533 processor
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[1], [2]. Though it is possible to apply this same board to the ADSP-BF561 EZ-KIT Lite evaluation system with only minor changes, considering that this device incorporates two cores and two SPORTs, it makes more sense to extend the board to four COMET devices and to allow it to handle twice the number of processed channels [3].
The board was also designed to interface
!
also to a ADSP-BF535 processor, although it requires more substantial hardware changes, such as using two SPORTs instead of the one needed for the ADSP-BF533. The schematics refer to the the required changes. This entails significant software which are beyond the scope of this EE-Note.
The software framework is written in C entirely. All references to execution times are taken from this code example.

System Architecture

Figure 1 shows a block diagram of a typical application. The board is designed to plug into an existing T1/E1 connection via two RJ48C connectors. This leads to two streams (stream 1 and stream 2), both carrying incoming and outgoing data (R most basic mode of operation (pass-through),
R
and SIN are copied unaltered to R
IN
S
respectively, such that the whole resembles
OUT,
the original single T1/E1 connection.
IN
, R
OUT
, S
and S
IN,
). In the
OUT
OUT
and
a
T1/E1 Stream 1
T1/E1 Interface Board
Rin
Framing and
processing
Sout

Figure 1. System overview

The software also provides a parser-based UART interface to a generic host processor for setting operating modes and parameters and controlling the Blackfin processor and the COMET framing device.
Figure 2 provides a detailed view of the interface. The signals from the two RJ48C connectors are conditioned and isolated from the digital domain by transformers. Also provided are over-voltage protection diodes. The COMET framers (PM4351) are configured to generate serial inputs in a format compliant with the SPORT’s multi­channel mode from the R to generate the R SPORT’s serial output data. The two COMET framer chips are connected to the Blackfin processor via the External Bus Interface Unit (EBIU) and are configured via this interface.
OUT
and S

T1/E1 Data Formats

T1/E1 connections are a well-known and widely adopted standard. For the purpose of this EE­Note, it is sufficient to say that T1 lines encode 24
and SIN streams, and
IN
streams from the
OUT
T1/E1 Stream 2
Rout
Sin
RS232 to Host
channels of 8-bit data plus one framing bit (totaling 193 bits) into a 1.544 MHz carrier wave. Similarly, E1 lines encode 32 channels of 8-bit data (totaling 256 bits) into a 2.048 MHz carrier. In both cases, this corresponds to a new sample of each channel every 125 µs. The 8-bit data is obtained from linear, 14- or 13-bit data samples by compression according to a-law or µ-law, respectively.
In addition to the data (sometimes referred to as the payload), T1/E1 streams contain signaling bits according to a variety of communication standards. This EE-Note does not go into the details of these standards, since the COMET devices’ functionality is to extract the payload from the incoming T1/E1 streams and to encode a valid T1/E1 outgoing stream from the payload from the DSP, according to the selected standard. Thus, if the COMET devices are set up correctly, the processor will “see” the payload only and never have to handle the signaling bits. If errors occur, the COMET can be set up to generate an interrupt for the DSP as well. For more details, refer to [4], [5] and [7].
Interfacing T1/E1 Transceivers/Framers to Blackfin® Processors via the Serial Port (EE-234) Page 2 of 13
a
Rin
Line Interface
Protection
RJ48C
&
Isolation
RS232
Sout
EZ-KIT Lite
Expansion
Connectors
CLK
2.048MHz
COMET1
PM4351

Figure 2. T1/E1 Interface Card Block Diagram

The incoming streams (RIN and SIN) are thus converted (mapped) into a PCM data stream, sometimes referred to as “backplane”. Again, there are a variety of standards, but they consist of a signal containing the data bits for each channel and, for T1 lines, the framing bit, synchronous to a
1.544 (T1) or 2.048 MHz (E1) clock. This block of data is called a frame. The beginning of a frame is signaled by a separate signal called a “frame sync”. For T1, the COMET also provides the option of mapping the 24 channels into a
2.048 MHz backplane, such that channels 24-31 contain dummy data, which the processor can then ignore. This offers the advantage that both T1 and E1 settings use the same clock, thus switching between the two formats requires only a simple software change, rather than switching between two clock sources.
For the outgoing streams (R
OUT
and S
OUT
considerations apply. The backplane signals consist of 32 channels of 8-bit data for an E1 line. Similarly, for a T1 line, the COMET simply ignores channels 24-31.
EBIU SPORT
PCM data streams
), similar
UART
DSP
Line Interface
Protection
&
Isolation
Rout
RJ48C
Sin
via
COMET2
PM4351
Figure 3 graphically shows the backplane formats. Since each SPORT has two transmit lines and two receive lines, the ADSP-BF561 can be used to handle all four PCM streams. The clock and frame sync are shared so that the data flows are synchronized at all times. With its ability to independently select driving and sampling edges for the receiver and the transmitter, clock and frame sync, and delay between frame sync and first bit of the data streams, the ADSP-BF561 can be adapted to virtually all common backplane formats. Figure 3 shows the format used in this application.
For the PCM data to be available for processing, it must be transferred into the processor’s memory. Similarly, outgoing data has to be transferred from memory to the SPORT. This is done via direct memory access (DMA) channels. The so called 2D-DMA capabilities allow for rearranging samples in flexible ways, as is shown in
Figure 4. Incoming samples are stored in the
manner depicted in the figure as they arrive, that is
R
[0], SIN[0], RIN[1], SIN[1], …
IN
Interfacing T1/E1 Transceivers/Framers to Blackfin® Processors via the Serial Port (EE-234) Page 3 of 13
a
RIN[Number_of_channels-1], SIN[Number_of_channels-1] for frame 0, and similarly for the other frames. Note that the two receive lines (R re-organized as they come in to the SPORT without any intervention of the core. The attached code example acquires a block of
Number_of_Samples frames, set by default to 40,
such that an interrupt occurs every (
Number_of_Samples * 125) µs (5 ms for the
provided example). The interrupt signals that the acquired frames are available for processing, but the DMA continues to acquire new frames in a different memory area. When this second block is acquired, another interrupt is generated and the DMA places new frames into the first memory area, overwriting the ones already there. This mechanism is sometimes referred to as double buffering and allows the Blackfin processor to process half the incoming data (the first
and SIN) are
IN
Number_of_Samples frames) while the other half is
acquired. This is done in hardware, without any code intervention, by using the descriptor chain mechanism provided by the DMA engines. Similar considerations apply for the transmitted streams, R functionality, refer to [2].
The last step before processing the incoming data is to convert the PCM data into linear values. As previously mentioned, the incoming data is compressed and has to be expanded using a-law or µ-law. Once processed, the resulting output data must be compressed to fit into the outgoing PCM data streams.
The SPORT does the expanding and compressing (companding) in hardware, which eliminates processing time needed by the processor.
OUT
and S
. For details on DMA
OUT

Figure 3. Backplane signal formats

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