Analog Devices EE222v01 Application Notes

Engineer-to-Engineer Note EE-222

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Technical notes on using Analog Devices DSPs, processors and development tools

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Interfacing the ADSP-21262 SHARC® EZ-KIT Lite™ Boards to High­Speed Converter Evaluation Boards

Contributed by R. Murphy and R. Gentile Rev 1 – January 23, 2004

Introduction

This Engineer-to-Engineer Note describes the use of
the Parallel Data Acquisition Port (PDAP) on the
ADSP-21262 SHARC® DSP and the use of the EZ­KIT Extender card to interface an ADSP-21262 EZ­KIT Lite™ board to evaluation boards of high-speed
converters.

Representatively, physical connection to an AD9244­EB Evaluation Board is described, as well as the
configuration of the SHARC DSP. This project was
implemented using an ADSP-21262 EZ-KIT Lite
board, a SHARC EZ-KIT Extender card, an AD9244
High-Speed Converter Evaluation Board, and the
VisualDSP++® 3.0 SP1 development environment.

Background

In the 1970’s and 80’s, high-speed mixed-signal
designs were often constrained by digital (not analog)
circuitry limitations. Highspeed (>10MSPS) parallel
converters, for example, have been available from
industry leaders like Analog Devices, Inc., since the
1970’s.

More and more applications are demanding intensive
real-time algorithms. In addition, higher sample rates
(14 bits at greater than 50MSPS) are available from
analog-to-digital converters (ADCs) and digital-to­analog converters (DACs). In addition to the higher
sample rates are vast decreases in power
consumption, exemplified in the AD9244, which
consumes only 590 mW at its full sample rate of 65
MSPS. These factors mandate faster programmable
general-purpose (GP) digital signal processors
(DSPs) to handle the challenges presented by these
high-speed designs.

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Until recently, most designers were forced to
interface high-speed parallel converters to application
specific ICs (ASICs) or fast field programmable gate
arrays (FPGAs).

Advantages of using a GP DSP

One of the biggest advantages of general-purpose
programmable processors is that these solutions
typically cost less than their closest digital processing
counterparts (FPGAs and ASICs). Additionally,
general-purpose DSP design cycles are much shorter,
allowing faster time to market. Some companies must
hire (or consult with) professionals who specialize in
FPGA/ASIC design. Companies may even be forced
to send their intellectual property (IP) out of house,
involving risks in confidentiality (hardware,
firmware, and software). On the other hand, general­purpose DSP code can be placed onto off-chip ROM
or masked onto a DSP, like the ADSP-21262, further
protecting intellectual property.General-purpose
processors are also fully programmable, unlike
ASICs, which require costly redesign (time and
money). These factors drive many engineers to
consider general-purpose DSPs as the solution of
choice, even more so as DSPs approach “Pentium
class” core rates.

The processing bandwidth needed depends on the
processor's interface capabilities, which in turn, are
influenced by several factors including: block
processing versus sample processing, the existence of
a Direct Memory Access (DMA) controller, multi­ported memory, and the use of external FIFOs.

Fortunately, Analog Devices' 32-bit SHARC family
of DSPs boasts a zero-overhead DMA controller as
well as dual-ported on-chip SRAM. Similar to the

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ADSP-2116x DSP family, the ADSP-21262 is a
SIMD processor, and it runs at a core instruction rate
of 200 MHz (5ns). The SIMD capability effectively
doubles the data processing bandwidth of the
processor, providing 1200 MFLOPs of processing
power. The combination of core speed, an
independent DMA controller, and a large dual-ported
on-chip memory (up to 2 Mbits of SRAM and 4
Mbits of ROM) enable the ADSP-21262 to perform
efficient block processing at high data rates.

Hardware Interface

AD9244 HSC

The high-speed converter in this example is the
AD9244 (Figure 1). It is a 14-bit, 65 MSPS, analog­to-digital converter with an on-chip, high­performance sample-and-hold amplifier. At half the
power dissipation (only 590 mW) of any competitor’s
ADC, the AD9244 is highly desirable for power­sensitive applications, such as wireless
communications subsystems (Microcell, Picocell),
medical imaging systems, ultrasound equipment,
portable and battery-operated instrumentation, high­resolution CCD imaging, and IF digitizing
applications.

several methods of providing this clock source. This
clock will also be used to control the PDAP interface
on the ADSP-21262. The digital output is hardware­selectable and can be presented in straight binary or
in twos complement format. An out-of-range (OTR)
signal indicates an overflow condition that can be
used with the most significant bit to determine low or
high overflow.

The AD9244 evaluation board (AD9244-65PCB)
allows designers to validate the AD9244 in their
system. The ADSP-21262 SHARC DSP is also
available as an evaluation board (ADDS-21262­EZLITE). Analog Devices has developed an EZ-KIT
Extender Card (Figure 3) to provide designers with an
easy solution to evaluate the ADSP-21262 and
AD9244 together,.

Figure 2. AD9244 ADC Evaluation Board

AD9244-65PCB Configuration

The AD9244 evaluation board provides several
options, permitting multiple combinations of data

Figure 1. AD9244 Block Diagram

The AD9244 includes an on-board, programmable
voltage reference. Alternatively, an external reference
can be used to suit the DC accuracy and temperature
drift requirements of the application. The AD9244
evalution board has circuitry to satisfy this
requirement. A differential or single-ended clock
input is used to control all internal conversion cycles,
and the AD9244 evaluation board has provisions for

Interfacing the ADSP-21262 SHARC® EZ-KIT Lite™ Boards to High-Speed Converter Evaluation Boards
(EE-222) Page 2 of 8

inputs and outputs and clock inputs. The
configuration used for this project is included below.
See Reference [5] for more information.

DFS: Digital Format Select (JP2) Open = straight
binary; Closed = twos complement

DRVDD: Output Drive. The AD9244 output drivers
can be configured to interface with 5-V or 3.3-V logic
families by setting DRVDD to 5V or 3.3V,
respectively.

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OEB: Digital Output Enable. (High = digital output
enabled; Low = high impedance state)

OTR: Out of Range. High = analog input voltage
exceeds analog input range. The out-of-range signal
is not used in this project. Optionally, it can be
ANDed with the MSB and its complement to detect
underrange and overrange conditions.
Clock Input Modes: Several modes of operation for
the AD9244 clock interface are available, such
asdifferential clock input (AC- or DC-coupled)
orsingle-ended clock inputs (AC- or DC-coupled).

Analog Input Configuration

The AD9244 evaluation board allows analog inputs
to be driven:

• Differentially through a transformer

• Via an AD8138 high-speed differential amplifier

• Directly (single-ended)

configurable high-speed converter products (The
AD9244 does not use this). To maintain signal
integrity over multiple PCBs, a buffer has been used
for all data signals; a GPIO pin can enable/disable
this buffer. The board also provides an extensive
breadboard area as well as clock-squaring circuitry
and space to install a crystal oscillator. The PDAP
peripheral of the ADSP-21262 SHARC DSP has the
capability to use either the DAI pins or the Parallel
Port pins (AD15-0) as its data bus. For greater
flexibility, the Parallel Port pins are routed to the
AD9244 evaluation boards via the Extender Card.
This project uses the PDAP with the Parallel Port
pins and provides the option to connect the Parallel
Port to a parallel device using the extender card.

ADSP-21262 SHARC DSP

The ADSP-21262 SHARC DSP provides two parallel
peripherals that are useful when connecting to
parallel ADCs: the Parallel Port and the Parallel Data
Acquisition Port (PDAP).

The Parallel Port is an asynchronous 16-bit bi­directional interface, providing an interface to
inexpensive external SRAM. Its maximum
throughput is 66 MB/s. The Parellel Port is used with
the SHARC DSP’s zero-overhead DMA controller,
and the address and data pins are multiplexed., The
external DMA address index, count, and modify
registers can be configured such that the index
register is not incremented, allowing the Parallel Port
to receive data from the ADC and place it in memory.

Figure 3. SHARC EZ-KIT Lite Extender Card

EZ-KIT Lite Extender Card

This card, which connects to the EZ-KIT Lite board's
Expansion Interface, provides a path to the PDAP for
the ADC, with a few extras. The extender card
provides an interface between the ADSP-21262 EZ­KIT Lite and a host of high-speed converter ADC and
DAC evaluation boards, providing debug access to all
signals. The SPI-compatible port of the ADSP-21262
is routed to this card as well, supporting SPI-

Interfacing the ADSP-21262 SHARC® EZ-KIT Lite™ Boards to High-Speed Converter Evaluation Boards
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Figure 4. ADSP-21262 PDAP

The PDAP interface (Figure 4) uses one channel of
the Input Data Port and the 16 DAI pins or the
Parallel Port’s address pins to bring data into
memory. The PDAP is also used with the DMA
controller, but is an input only.In addition to its data
pins, the PDAP has two control inputs: PDAP_HOLD
and PDAP_CLK. Use PDAP_HOLD to pause the
input buffer in situations where the data is invalid, or