Analog Devices EE216 Application Notes

Engineer-to-Engineer Note EE-216

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Estimating Power Dissipation for ADSP-21262S SHARC® DSPs

Contributed by C. Coughlin December 2, 2003

Introduction

This EE-Note discusses power consumption of
the ADSP-21262S SHARC® DSPs based on
characterization data measured over power
supply voltage, core frequency (CCLK) and
ambient operating temperature (T

). The intent

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of this document is to assist board designers in
estimating their power budget for power supply
design and thermal relief designs using the
ADSP-21262S DSP.

The ADSP-21262S DSP is a member of the
SIMD SHARC family of DSPs featuring Analog
Devices’ Super Harvard Architecture. Like other
SHARC DSPs, the ADSP-21262S is a 32-bit
processor optimized for high-precision signal
processing applications. The DSP operates at
core clock frequencies up to 200MHz with the
core operating at 1.2V (V
operating at 3.3V (V

DDEXT

).

) and the I/O

DDINT

Total power consumption has two components:
internal circuitry (i.e. the core and PLL) and
switching of external output drivers (i.e. the I/O).
The following sections detail how to derive both
of these components for estimating total power
consumption.

Estimating Internal Power Consumption

The internal power consumption (on the V
supply) is dependent on the instruction execution
sequence and the data operands involved. The
data sheet

[2]

provides current consumption

DDINT

figures for discrete activity levels. Mapping
system application code to specified values
provides a means of estimating internal power
consumption for an ADSP-21262S DSP in a
given application.

Internal Power Vector Definitions and Activity Levels

The following power vector definitions define
the levels of activity that apply to the internal
power vectors shown in Table 1:

• I

DD-IDLE

V

supply current for Idle

DDINT

activity. Idle activity is the core executing the
IDLE instruction only, without core memory
accesses, DMA, or interrupts.

• I

DD-INLOW

V

supply current for Low

DDINT

activity. Low activity is the core executing a
single-function instruction fetched from
internal memory with no core memory
accesses and no DMA.

• I

DD-INHIGH VDDINT

supply current for High
activity. High activity is the core executing a
multifunction instruction fetched from
internal memory, with 4 core memory
accesses per CLKIN cycle (DMx64) and
DMA through 3 SPORTs running @ 50MHz.
The DMA is chained to itself (running
continuously) and does not use interrupts.
The bit pattern for each core memory access
and DMA is random.

• I

DD-INTYP

Same code as High activity,

however, operating under nominal power

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supply conditions (V

= 1.2V) and TA =

DDINT

+25°C.

• I

DD-INPEAK VDDINT

supply current for Peak
activity. Peak activity is the core executing a
multifunction instruction fetched from
internal memory and/or cache, with 8 core
memory accesses per CLKIN cycle (DMx64,
PMx64) and DMA through 6 SPORTs
running @ 50MHz. The DMA is chained to
itself (running continuously) and does not use
interrupts. The bit pattern for each core
memory access is random, and the DMA bit
pattern is worst case.

Vector

I

T

DD-IDLE

I

DD-INLOW

I

DD-INHIGH

I

DD-INTYP

I

DD-INPEAK

T

T

T

T

Test Conditions (worst case except where noted)

= +70°C, V

A

= +70°C, V

A

= +70°C, V

A

= +25°C, V

A

= +70°C, V

A

= Max, CCLK = Max 0.70 0.70

DDINT

= Max, CCLK = Max 0.85 0.85

DDINT

= Max, CCLK = Max 1.00 1.00

DDINT

= 1.2V, CCLK = 200MHz 0.50 0.50

DDINT

= Max, CCLK = Max 1.26 1.06

DDINT

Table 1 lists the maximum internal current
consumption for the DSP at different levels of
activity. These figures represent the worst case
I

as measured across process, voltage,

DDINT

temperature, and frequency (PVTF). From these
internal activity levels (and from an
understanding of the program flow using
profiling or some other method), you can
calculate a worst-case weighted-average of
power consumption for each ADSP-21262S DSP
in a system.

1

I

(A) 2 I

DDINT

DDINT

(A) 3

Table 1: Maximum Internal Current Consumption per Vector Type

1

Worst-case conditions: TJ < +125°C, V

2 Worst case across process, voltage, temperature and frequency (PVTF) for 136-ball mBGA package option. See “Estimating Total Power

Consumption and Power Budget” for more information pertaining to the power budget and the mBGA package option.

3 Worst case across process, voltage, temperature and frequency (PVTF) for 144-lead LQFP package option. See “Estimating Total Power

Consumption and Power Budget” for more information pertaining to the power budget and the LQFP package option.

DDEXT

= 3.47V, V

= 1.26V, CCLK = 200MHz; does not apply to I

DDINT

DD-INTYP

Operation Low Activity High Activity Peak Activity

Instruction Type Single Function Multifunction Multifunction
Instruction Fetch Internal Memory Internal Memory Internal Memory, Cache

4

Core Memory Access
DMA Transmit Int to Ext N/A 3 SPORTs running @ 50 MHz 6 SPORTs running @ 50MHz
Data Bit Pattern for core

Memory Access and DMA

None 4 per tCK cycle (DMx64) 8 per tCK cycle (DMx64, PMx64)

N/A Random Worst case

Table 2: Activity Level Definitions

4 tCK = CLKIN; Core clock ratio 8:1

Estimating Power Dissipation for ADSP-21262S SHARC® DSPs Page 2 of 9

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Table 2 summarizes low, high and peak activity
levels corresponding to the vectors listed in
Table 1.

The average current consumption for an ADSP­21262S device in a specific application is
calculated according to the following formula,
where “%” is the percentage of the time that the
application spends in that state.

% Peak Activity Level * I
% High Activity Level * I

% Low Activity Level * I

% Idle Activity Level * I

---------------------------------------------­Total Current for V

Equation 1: Internal Current (IDDINT) Calculation

DDINT

DD-INPEAK

DD-INHIGH

DD-INLOW

DD-IDLE

(I

DDINT

)

Estimated average internal power consumption
(P

Equation 2: Internal Power (PDDINT) Calculation

) can then be calculated as follows:

DDINT

P

DDINT

= V

DDINT

x I

DDINT

30% * 1.26
30% * 1.00
20% * 0.85
20% * 0.70

-------------------

I

= 0.988 A

DDINT

Example 2: Internal Current Estimation Example

Therefore, an estimate of the average internal
power for the processor can be calculated from
Example 2 as follows:

P

= 1.20 V x 0.988 A = 1.1856 W

DDINT

Example 3: Internal Power Estimation

Estimating External Power Consumption

The external power consumption (on the V
supply) is dependent on the switching of the
output pins. The magnitude of the external power
depends on:

DDEXT

For example, after profiling the application code
for a particular system, activity is determined to
be proportioned a:

Peak Activity Level 30%
High Activity Level 30%

Low Activity Level 20%
Idle Activity Level 20%

• The number of output pins (O) that switch

during each cycle

• The maximum frequency (f) at which the

output pins can switch

• The voltage swing of the output pins (V

• The load capacitance of the output pins (C

DDEXT

L

)

In addition to the input capacitance of each
device connected to an output, the total load
capacitance includes the capacitance (C

OUT

) of

the DSP pin itself which is driving the load. The

Example 1: Internal System Activity Levels

Using the percentages in this example and the
currents provided for each activity level in Table
1 (mBGA package used for this example), a
value for the worst case average internal current
consumption of a single processor is estimated as
follows:

parallel port address/data pins (AD15-0) can
transfer data at 1/3 the DSP core clock rate. This
corresponds to a maximum switching frequency
of 33MHz for AD15-0 and 66MHz for

/WR at a

core clock rate of 200MHz. In addition, the serial
ports can operate up to 1/8 the DSP core clock
rate. This corresponds to a maximum switching
frequency of 12.5MHz for SDATA and a

Estimating Power Dissipation for ADSP-21262S SHARC® DSPs Page 3 of 9

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