Analog Devices EE212 Application Notes

Engineer To Engineer Note EE-212

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Technical Notes on using Analog Devices' DSP components and development tools

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Connecting the AD74111 Mono Audio Codec Evaluation Board to the
ADSP-21161N SHARC® EZ-KIT Lite™ Board

Contributed by Mazlum Adas October 21, 2003

Introduction

This application note describes, setting up the AD74111 codec to communicate with the ADSP-21161
SHARC® DSP. The DSP receives the serial data from the ADC and sends it back to the DAC. An
example code will delivered with this application note to show how to configure the codec and transfer the
data.

Overview of the codec

The AD74111 is a front-end-codec for general-purpose audio and video applications. It provides a mono
input channel and a mono output channel.

The codec supports sample rates from 8 kHz up to 48 kHz and word length from 16 to 24 bit. Also the
codec provides a programmable ADC gain and on-chip volume control for the DAC channel.

The configuration of the AD74111 is done with SPORT 3, also for the data transmission the SPORTs
(SPORT 1 and SPORT 3) are used.

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Building the hardware

Figure 1 shows the connection between the AD74111 evaluation board and the ADSP-21161 EZ-KIT
Lite™ board.

Figure 1: Connection of the AD74111 Evaluation Board and the ADSP-21161N EZ-KIT Lite

On the ADSP-21161N EZ-KIT Lite both frame syncs (SFS1 and SFS3) and the SPORT clocks (SCLK1
and SCLK3) are tied together with Zero-Ohm Resistors, so both SPORTs have the same frame sync and
clock. It is necessary to have a good ground connection between the two boards. Also short cables should
be used to reduce noise on the signals.

Jumper Settings on the ADSP-21161N EZ-KIT Lite Board

For the connection of the ADSP-21161N EZ-KIT Lite to the AD74111 Evaluation Board the relevant
jumpers should be set as follows in Table 1. The other jumpers can be left as default.

Jumper Description State

JP4 FLAG 0 enable OFF
JP5 FLAG 1 enable OFF
JP26 Push-button enable FLAG 0 OFF
JP27 Push-button enable FLAG1 OFF
JP19 DSP ID ON: 1-2, 3-4, 5-6
JP20 Boot Mode ON: 3-4 OFF: 1-2, 5-6
JP21 Clock Mode ON: 5-6 OFF: 1-2, 3-4

Table 1: ADSP-21161N EZ-KIT Lite jumper’s settings

Connecting the AD74111 Mono Audio Codec Evaluation Board to the ADSP-21161N SHARC® EZ-KIT Lite™
Board (EE-212) Page 2 of 12

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Jumper Settings on the AD74111 Evaluation Board

The following table (Table 2) shows the jumper settings for the AD74111 Evaluation board.

Link Description State

LK5 Selecting of the on board crystal oscillator B
LK6 Disabling of the MCLK divider A
LK7 MCLK/2 is not reference clock source for DCLK OFF
LK8 Selecting as master device A
LK11 External reset signal B

Table 2: AD74111 Evaluation board jumper's settings

The other jumpers can be left in the default position.

Software flow

The software flow for the data transmission between the ADSP-21161N SHARC DSP and the AD74111
is described in the following figure (Figure 2):

Initialization of the ADSP-

21161 EZ-KIT Lite

Reset of the AD74111

Initialization of SPORT 3

to configure the codec

Configuration of the

AD74111 via SPORT 3

Setting up the DMA Channels of the SPORTs:

SPORT 1 Receive

SPORT 3 Transmit

Figure 2: Data transmission flow diagram

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Board (EE-212) Page 3 of 12

First the AD74111 must be reset to put it into the correct state. Then the internal control registers of the
codec are programmed via the SPORT 3 of the ADSP-21161. After this is done, the DMA channels of the
DSP will be set up to receive data and transmit data.

The DSP receives the serial data from the codec with SPORT 1 channel A. The data is stored in the
internal memory and send with SPORT 3 to the codec back. The user can modify the received data in the
internal memory before sending it back.

The input data is provided to the codec over the ADC In connector on the evaluation board. The output
data goes from the DAC Out connector to a loudspeaker.

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Reset of the codec

To reset the codec in the right way is very important. The state of the DIN (data in) signal during the reset
decides if the codec is in slave or in master mode. If DIN is high while the codec is reset, the codec will
operate in slave mode. In slave mode DCLK and DFS are provided externally to the codec.

If DIN is low during reset the master mode will be selected. In master mode DCLK and DFS are
generated from the codec. The reset timing is shown in Figure 3.

Figure 3: Reset timing of the codec

In this application Flag 0 is used to generate the reset signal for the codec. It is important to meet the
timing (t

The reset procedure takes 3072 MCLK (64ms) periods. It is not possible to write to the codec until this
time is finished.

Connecting the AD74111 Mono Audio Codec Evaluation Board to the ADSP-21161N SHARC® EZ-KIT Lite™
Board (EE-212) Page 4 of 12

, tRS and tRH) to have defined reset provided for the codec.

RES