Analog Devices EE210v02 Application Notes
Engineer-to-Engineer Note EE-210
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Technical notes on using Analog Devices DSPs, processors and development tools
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SDRAM Selection Guidelines and Configuration for ADI Processors
Contributed by Maikel Kokaly-Bannourah Rev 2 – August 13, 2004
Introduction
This EE-Note is intended to help the user select and configure a suitable Synchronous Dynamic Random
Access Memory (SDRAM) device to interface with Analog Devices Inc. (ADI) processors and DSPs.
The different factors involved in choosing the appropriate memory component depending on the Processor
or DSP used will be discussed in this document. Additionally, some programming examples on how to
configure the SDRAM controller will be shown.
Please note that, although the concepts explained throughout this note apply to all ADI processors and
DSPs that have an On-Chip SDRAM Controller, the programming examples described in this document
are based on the ADSP-TS201S TigerSHARC® and the ADSP-BF533 Blackfin® processors.
Table of Contents
Introduction........................................................................................................................................... 1
Table of Contents............................................................................................................................... 1
Listings ....................................................................................................................................................2
ADI Processors and DSPs ................................................................................................................ 3
SDRAM Specifications........................................................................................................................3
Choosing the appropriate SDRAM................................................................................................ 3
The ADSP-TS201S TigerSHARC Processor On-Chip SDRAM Controller..................... 3
SDRAM Controller Features .......................................................................................................3
Setting up the SDRAM Controller.........................................................................................4
SDRCON................................................................................................................................................. 4
The ADSP-BF533 Blackfin Processor On-Chip SDRAM Controller ............................8
SDRAM Controller Features .......................................................................................................8
Setting up the SDRAM Controller.........................................................................................9
EBIU_SDGCTL................................................................................................................................... 10
EBIU_SDBCTL................................................................................................................................... 14
EBIU_SDRRC...................................................................................................................................... 15
EBIU_SDSTAT................................................................................................................................... 16
Summary..................................................................................................................................................... 18
References..............................................................................................................................................20
Document History...............................................................................................................................20
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Listings
Figure 1. ADSP-TS201S SDRAM Control Register (SDRCON) ........................................5
Figure 2. ADSP-BF533 SDRAM EBIU_SDGCTL Register – Upper 16-bits ..............10
Figure 3. ADSP-BF533 SDRAM EBIU_SDGCTL Register – Lower 16-bits ..............11
Figure 4. ADSP-BF533 SDRAM Bank Control Register (EBIU_SDBCTL).................14
Figure 5. ADSP-BF533 EBIU_SDRRC Register...................................................................... 15
Figure 6. ADSP-BF533 SDRAM Status Register (EBIU_SDSTAT)............................... 16
Table 1. ADSP-TS201S TigerSHARC Processor and SDRAMs compatibility......... 4
Table 2. SDRAM “A” CAS Latency................................................................................................ 5
Table 3. SDRAM “A” Specifications ........................................................................................ 6
Table 4. Relevant SDRAM “A” Timing Specifications.................................................. 7
Table 5. ADSP-BF533 Blackfin Processor and SDRAMs compatibility ................9
Table 6. SDRAM “D” CAS Latency.............................................................................................. 11
Table 7. Relevant SDRAM “D” Timing Specifications................................................ 12
Table 8. SDRAM “D” Specifications ...................................................................................... 15
Table 9. TigerSHARC Processors with On-Chip SDRAM Controller...................... 19
Table 10. Blackfin Processors with On-Chip SDRAM Controller........................ 19
Table 11. SHARC DSPs with On-Chip SDRAM Controller.............................................. 20
Code 1. SDRCON Settings using header file defts201.h........................................... 7
Code 2. SDRCON Settings without the use of header files.................................... 8
Code 3. SDRAM Control Registers Settings using header file defBF532.h 17
Code 4. SDRAM Control Registers Settings without header files................... 18
SDRAM Selection Guidelines and Configuration for ADI Processors (EE-210) Page 2 of 20
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ADI Processors and DSPs
Several Analog Devices processors and DSPs
have been designed with an on-chip SDRAM
controller:
• The ADSP-21065L and ADSP-21161N
SHARC DSPs.
• The ADSP-TS101S, ADSP-TS201S, ADSP-
TS202S and ADSP-TS203S TigerSHARC
processors.
• The ADSP-BF531, ADSP-BF532, ADSP-
BF533 and ADSP-BF535 Blackfin
processors.
Having an On-Chip SDRAM Controller allows
to gluelessly interface to SDRAM memory
devices without the necessity of incorporating
additional components to the system, resulting in
a cost-effective solution.
SDRAM Specifications
There are several factors that need to be
considered when selecting an SDRAM device to
interface with ADI’s processors or DSPs, which
are common across all families:
• Supported operating voltage
• Maximum supported operating frequency
• Maximum supported memory
• I/O size and number of banks
• Column Address Strobe (CAS) latency
• Refresh rate
• Burst length
• Page size
• Initialization sequence
All these characteristics are defined in the
SDRAM device datasheet and must meet the
specifications of the on-chip SDRAM controller
of the processor being used in order to be able to
gluelessly interface to it.
Choosing the appropriate SDRAM
As an example, let’s examine the ADSP-TS201S
TigerSHARC and the ADSP-BF533 Blackfin
processors and their compatibility with different
SDRAM devices.
The ADSP-TS201S TigerSHARC
Processor On-Chip SDRAM
Controller
Before an SDRAM device can be selected, the
user needs to understand the features and
specifications of the chosen processor.
SDRAM Controller Features
With the factors previously explained in mind,
these are the relevant ADSP-TS201S processor
on-chip SDRAM controller characteristics for
choosing the appropriate memory device:
• Supported operating Voltage
o 3.3 and 2.5 V
• Maximum supported operating Frequency
o 125 MHz
• Maximum supported memory
o 256 Mbytes (64 M x 32 bits or
32 M x 64 bits) per external SDRAM
bank
• Number of internal SDRAM banks
o 2 or 4 banks.
• Column Address Strobe (CAS) latency
o Programmable value: 1 to 3 system clock
cycles (SCLK)
• Refresh rate
o Programmable value: 32 to 64 ms.
• Burst Length
o Full page burst
• Page size
o Programmable value to: 256, 512 or 1024
words.
• Initialization sequence
o Programmable sequence: MRSÖREF, or
REFÖMRS.
SDRAM Selection Guidelines and Configuration for ADI Processors (EE-210) Page 3 of 20
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For the aid of this example, devices A and B
have been selected. Are these two SDRAM
devices compatible with the ADSP-TS201S
SDRAM
Features
Voltage
Max. Frequency
Max. Mem. Size
Supported I/O
Number of
SDRAM Banks
CAS Latency
Refresh Rate
Burst Length
ADSP-TS201S SDRAM
Controller
2.5 or 3.3 V 3.3 V
125 MHz 143/166 MHz
64 Mx32 or 32 Mx64
(256 Mbytes) per external
SDRAM bank
x32, x64
2 or 4 banks 4 banks
1 to 3 cycles 1 to 3 cycles
32 and 64 ms 64 ms
Full-page burst
TigerSHARC Processor? Let’s look at the
different specifications to be met:
SDRAM “A”
1 Meg x 32 x 4
banks
16 Mbytes
x32
1,2,4,8 or
Full-page
OK
9
9
9
9
9
9
9
9
SDRAM “B”
4 Meg x 32 x 2
banks
3.3 V
100/133 MHz
32 Mbytes
x32
2 banks
1 to 3 cycles
64 ms
1
OK
9
9
9
9
9
9
9
8
Page Size
Init. Sequence
Table 1. ADSP-TS201S TigerSHARC Processor and SDRAMs compatibility
As it can be seen from the table above, device B
does not meet all specifications: it only supports
burst length of one (and not full page burst) and
its page size is 2048 words (which is bigger than
the maximum supported page size of 1024
words).
On the other side, it can be seen that device A
meets all requirements, and therefore, it can be
properly interfaced to the ADSP-TS201S
TigerSHARC Processor.
Setting up the SDRAM Controller
Now that a compatible SDRAM device has been
selected (SDRAM A), the next step is to properly
configure the SDRAM control register
256, 512, and 1024 256
MRSÖREF or REFÖMRS REFÖMRS
(SDRCON) according to the memory
specifications given in Table 1.
SDRCON
The initial value of the SDRCON register after
reset is zero, meaning that the SDRAM is
disabled. The bit descriptions for this register are
shown in Figure 1. Note that although this is a
32-bit register, only the lower 16-bits are shown.
The upper 16-bits are reserved and should
always be set to zero.
For more details, please refer to SDRAM
Interface chapter of the ADSP-TS201
TigerSHARC Processor Hardware Reference.
9
9
2048
MRSÖREF
8
9
SDRAM Selection Guidelines and Configuration for ADI Processors (EE-210) Page 4 of 20
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Figure 1. ADSP-TS201S SDRAM Control Register (SDRCON)
So how do we correctly set up the SDRAM
Control register (SDRCON)? Let’s have a look
at a typical SDRAM device datasheet to
determine the settings for the different bits:
• SDRAM ENABLE. This bit must be set
when SDRAM is present in the system
(SDRCON_ENBL).
To use the above bit definition
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SDRAM Selection Guidelines and Configuration for ADI Processors (EE-210) Page 5 of 20
(SDRCON_ENBL), the file defTS201.h
should be included in the source code
(see Code 1 ). This file comes with the
VisualDSP++™ 32-bit Tools and can be
found in the directory:
• CAS LATENCY. This parameter specifies
Table 2. SDRAM “A” CAS Latency
C:\...\AnalogDevices\VisualDSP\TS\include.
the delay between a read command and the
time data becomes available. It does not
apply to write accesses. CAS Latency is
generally specified in the datasheet as shown
in Table 2.
Assuming the external port runs with a
100MHz system clock (SCLK), the selected
CAS LATENCY is 2 (SDRCON_CLAT2).
Note that, as specified in Table 1, the
maximum supported SCLK frequency by the
ADSP-TS201S is 125 MHz. The selected
frequency for this example, 100 MHz,
corresponds to the default value of the
ADSP-TS201S EZ-KIT Lite™.
Some SDRAM timing specifications
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• PIPE DEPTH. In systems where several
• PAGE BOUNDARY. These bits define the
(CL, tRAS, tRP, etc) may vary depending
on the speed grade of the SDRAM being
used.
Settings in this particular example are
optimized for a dedicated operating
frequency (100 MHz) and speed grade
part (-6). Variations in the clock
frequency and/or speed grade of the
SDRAM device also require modifying
the parameter settings.
SDRAMs are used in parallel, and external
buffers are needed, this bit should be
enabled.
This is valid if the nominal capacitive pin
loading is exceeded (30 pF/pin). In this
particular example (ADSP-TS201S EZ-KIT
Lite), there are only two SDRAMs where no
buffering of the signals is needed (SDRAM
pin capacitance 2x5 pF+10 pF (PCB) ≈
20 pF). Therefore, this bit should be cleared
(SDRCON_PIPE1).
page size, in number of words, of the
SDRAM’s banks. This number corresponds
to the number of addressable columns.
Table 3. SDRAM “A” Specifications
As it can bee seen in Table 3, the maximum
number of addressable columns is 256 (A0-
7). Thus, the page size should be configured
to 256 (SDRCON_PG256).
• REFRESH RATE. These bits select the
refresh counter to coordinate the Processor’s
SOC clock rate (SOCCLK) with the SDRAM
device’s required refresh rate.
The refresh count is provided in Table 3 as
4 K, and is also generally listed under the
SDRAM features list as:
64 ms, 4,096-cycle refresh (15,6 µs/row)
With this in mind, the refresh rate is
calculated as follows:
⎛
SOCCLKCycles
⎜
⎝
Where: SOCCLK = 250 MHz (default
ADSP-TS201S EZ-KIT Lite value)
tREF = SDRAM refresh period
Rows = number of row addresses
Therefore,
Refresh rate = 250 MHz × 15,6 µs
= 3900 cycles
In order to be able to guarantee that this
number is met, a refresh rate equal to or
smaller than 3900 cycles should be selected.
In this case, and since the processor’s
controller supports up to 3700 cycles only,
this should be the selected refresh rate
(SDRCON_REF3700).
tREF
⋅=
Rows
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⎞
⎟
⎠
SDRAM Selection Guidelines and Configuration for ADI Processors (EE-210) Page 6 of 20
• PRC TO RAS DELAY. This parameter
determines the Precharge to RAS delay,
which is typically given in the datasheet as
tRP.
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