Analog Devices EE201v01 Application Notes
Engineer-to-Engineer Note EE-201
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Technical notes on using Analog Devices DSPs, processors and development tools
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The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller
Contributed by Maikel Kokaly-Bannourah Rev 1 – February 4, 2004
1 Introduction
This Engineer-to-Engineer Note introduces characteristics of the ADSP-TS20x TigerSHARC® processor
on-chip SDRAM controller. Although, this document is based on the ADSP-TS201 TigerSHARC
processor, a list highlighting the differences between TigerSHARC processor family derivatives (such as
ADSP-TS201, ADSP-TS202, and ADSP-TS203) is provided at the end of this document.
The internal signal chain is shown with the necessary address-mapping scheme. The command truth table
gives detailed information about execution in the SDRAM. The power-up sequence summarizes detail
information to start successful designs. A timing overview demonstrates the performance for different
access modes. For basic understanding of SDRAM memories, refer to the application note The ABC of
SDRAMemory (EE-126) [5].
Copyright 2004, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of
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of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however
no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices’ Engineer-to-Engineer Notes.
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2 Table of Contents
1 Introduction ............................................................................................................................................................................1
2 Table of Contents....................................................................................................................................................................2
3 Listings.....................................................................................................................................................................................4
4 Signal Chain of SDRAM........................................................................................................................................................5
5 On-Chip Controller Architecture .........................................................................................................................................6
5.1 Controller Command Interface.....................................................................................................................................6
5.2 TigerSHARC Processor Output FIFO..........................................................................................................................6
5.3 Controller Address Multiplexer....................................................................................................................................6
5.4 Controller Data Delay Buffer .......................................................................................................................................6
5.5 SDRAM Types .............................................................................................................................................................6
6 Command Coding...................................................................................................................................................................7
6.1 Controller’s Pin Definition ...........................................................................................................................................7
6.2 Controller Command Truth Table ................................................................................................................................7
6.3 Setup and Hold Times ..................................................................................................................................................8
6.4 Simplified State Diagram..............................................................................................................................................8
7 SDRAM Controller Properties............................................................................................................................................10
7.1 Address Mapping Scheme..........................................................................................................................................10
7.2 TigerSHARC Processor SDRAM Memory Select Signals (~MSSDx)......................................................................11
7.3 Burst Stop (BST) ........................................................................................................................................................11
7.4 Data Mask Function ([H:L]DQM)..............................................................................................................................12
7.5 SDRAM Bank Select..................................................................................................................................................12
TANDARD SDRAMS ........................................................................................................ 12
S
L
OW-POWER SDRAMS ..................................................................................................... 13
7.6 Controller Address 10 (SDA10).................................................................................................................................14
7.7 Burst Mode .................................................................................................................................................................14
7.8 Precharge All (PREA) ................................................................................................................................................14
7.9 Circular Access...........................................................................................................................................................14
7.10 Auto Refresh (REF)..................................................................................................................................................14
7.11 Self-Refresh (SREF).................................................................................................................................................14
7.12 Mode Register Set (MRS).........................................................................................................................................15
7.13 Extended Mode Register Set (EMRS)......................................................................................................................15
8 SDRAM Programming.........................................................................................................................................................16
8.1 SYSCON Register......................................................................................................................................................16
8.2 SDRCON Register ......................................................................................................................................................16
8.3 SDRAM Mode of Operation ......................................................................................................................................18
8.4 ADSP-TS201S Processor EZ-KIT Lite Evaluation Systems...................................................................................... 18
8.5 SDRAM Setting Overview.........................................................................................................................................19
9 Power-Up Sequence..............................................................................................................................................................20
9.1 Hardware Initialization............................................................................................................................................... 20
9.2 Software Initialization ................................................................................................................................................20
9.3 SDRAM Initialization Example..................................................................................................................................21
9.4 SDRAM Interface After Reset....................................................................................................................................22
The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (EE-201) Page 2 of 49
10 DMA Transfers...................................................................................................................................................................23
10.1 Internal Memory and SDRAM.................................................................................................................................23
10.2 External Device and SDRAM (FLY-BY) ................................................................................................................23
11 SDRAM Interface in Host Mode.......................................................................................................................................25
12 Multiprocessing...................................................................................................................................................................27
12.1 Command Decoding.................................................................................................................................................27
12.2 MRS Decoding .........................................................................................................................................................27
12.3 REF Decoding ..........................................................................................................................................................27
12.4 SREF Decoding........................................................................................................................................................27
12.5 Bus Transition Cycle ................................................................................................................................................27
13 SDRAM and Booting..........................................................................................................................................................29
13.1 Loader Kernel...........................................................................................................................................................29
13.2 Booting Modes .........................................................................................................................................................29
14 SDRAM Interface Throughput.........................................................................................................................................30
14.1 Sequential Reads Without Interruption.....................................................................................................................31
14.2 Non Sequential Reads Without Interruption.............................................................................................................32
14.3 Sequential Reads with Minimum Interruption..........................................................................................................33
14.4 Sequential Writes Without Interruption....................................................................................................................34
14.5 Non Sequential Writes Without Interruption............................................................................................................35
14.6 Sequential Writes with Minimum Interruption.........................................................................................................36
14.7 Reads Between Page/Bank .......................................................................................................................................37
14.8 Writes Between Page/Bank ......................................................................................................................................38
14.9 Minimum Read-to-Write Interval.............................................................................................................................39
14.10 Minimum Write-to-Read Interval...........................................................................................................................40
14.11 Chained DMA Transfers.........................................................................................................................................41
14.12 Auto-Refresh ..........................................................................................................................................................42
14.13 Self-Refresh and Host Accesses.............................................................................................................................43
14.14 SDRAM Performance Table...................................................................................................................................45
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15 Optimizing SDRAM Performance....................................................................................................................................46
15.1 External Buffering....................................................................................................................................................46
15.2 Using PC Modules....................................................................................................................................................46
15.3 General Rules for Optimized Performance...............................................................................................................47
16 ADSP-TS20x TigerSHARC Processor Family Derivatives.............................................................................................48
17 References............................................................................................................................................................................ 49
18 Document History ...............................................................................................................................................................49
The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (EE-201) Page 3 of 49
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3 Listings
Figure 1. ADSP-TS201 to SDRAM Signal Chain (64-bit bus configuration) ............................................................................... 5
Figure 2. ADSP-TS201S SDRAM Controller Simplified State Diagram...................................................................................... 9
Figure 3. ADSP-TS201S SDRAM Controller Mapping Scheme Example.................................................................................. 10
Figure 4. ADSP-TS201S Processor SDRAM Controller Access Structure ................................................................................. 11
Figure 5. ADSP-TS201S Processor External Port Data Alignment............................................................................................. 16
Figure 6. Power-Up and Initialization: PREA-REF-MRS............................................................................................................ 20
Figure 7. Signal Chain: Fly-by DMA and SDRAM..................................................................................................................... 23
Figure 8. Signal Chain: Host to ADSP-TS201S Processor .......................................................................................................... 25
Figure 9. Bus Transition Cycle During SDRAM Accesses.......................................................................................................... 28
Figure 10. Signal Chain: ADSP-TS201S Processor to SDRAM Using External Buffer ............................................................. 46
Table 1. Supported SDRAM devices.............................................................................................................................................. 6
Table 2. ADSP-TS201 SDRAM Controller Pins Description........................................................................................................ 7
Table 3. SDRAM Commands Truth Table..................................................................................................................................... 7
Table 4. [H:L]DQM Pins Functionality........................................................................................................................................ 12
Table 5. Bank Select Pins for 2-Banked LVTTL SDRAMs......................................................................................................... 12
Table 6. Bank Select Pins for 4-Banked LVTTL SDRAMs......................................................................................................... 13
Table 7. Bank Select Pins for 2-Banked Low-Power SDRAMs ........................................................................ .......................... 13
Table 8. Bank Select Pins for 4-Banked Low-Power SDRAMs ........................................................................ .......................... 13
Table 9. Refresh Counter Values.................................................................................................................................................. 17
Table 10. ADSP-TS201 EZ-Kit Lite SDRAM Settings ............................................................................................................... 18
Table 11. ADSP-TS201 Processor SDRAM Pin Description After Reset................................................................................... 22
Table 12. Multiprocessing Command Decoding.......................................................................................................................... 27
Table 13. ADSP-TS20x TigerSHARC Processor Family Product Differences ........................................................................... 48
The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (EE-201) Page 4 of 49
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4 Signal Chain of SDRAM
Figure 1 illustrates the signal chain between the ADSP-TS201S, the on-chip SDRAM controller, and the
external memory device for a 64-bit bus configuration:
ADSP-TS201S
SCLK
Core
DMA
SCLK
int. RD
int. WR
int. Reset
int. ACK
External
Port
Buffers
busy
~MSSDx
A25:0
A31:0
(non SDRAM)
m
m
o
L
C
d
A
M
Pipe depth
D63:0
SDCKE
d
n
a
c
i
g
~SDWE
o
[H:L]DQM
~MSSDx
s
s
e
x
r
e
d
l
p
i
t
l
A1:10,
u
buffer
~RAS
~CAS
SDA10
A14
r
e
A13
A12
Data
Figure 1. ADSP-TS201 to SDRAM Signal Chain (64-bit bus configuration)
CLK
CKE
~RAS
~CAS
~WE
DQM
A10
SDRAM
~CS
BA0
BA1
A0:9,
A11
DQ31:0
Consider the three parts of the signal flow:
ADSP-TS201S (core, DMA engine, I/O processor, and the address buffer)
The SDRAM Controller (control interface, delay buffer, and address multiplexer)
SDRAM device
The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (EE-201) Page 5 of 49
K
K
K
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5 On-Chip Controller Architecture
The synchronous interface between the ADSP-TS201S processor and the on-chip controller are described
in four basic parts:
5.1 Controller Command Interface
Because of the two different timing protocols, the TigerSHARC processor's internal commands are
converted to comply with the JEDEC standard for SDRAMs. The 125 MHz (maximum) external clock is
used for synchronous operation. The TigerSHARC’s internal request lines or strobes are used to access
the SDRAM with pulsed commands. The controller’s internal ACK line inserts variable wait states to the
processor during overhead cycles, caused by DRAM technology.
5.2 TigerSHARC Processor Output FIFO
The TigerSHARC processor’s output FIFO is active for external port addresses like SDRAM. The
processor's six-stage FIFO depth supports address pipelining for high-speed non-sequential read
operations without performance loss.
5.3 Controller Address Multiplexer
Every first read or write action is issued in multiplexed mode. A maximum of 8192 rows (64-bit bus
configuration) and 16384 rows (32-bit bus configuration) within 1024 columns can be addressed.
5.4 Controller Data Delay Buffer
If systems incorporate a heavy busload, an additional data buffer is used to decouple the input from the
capacitive load. This delay buffer, in conjunction with an external buffer for SDRAM control and address
lines, reduces additional logic.
5.5 SDRAM Types
The ADSP-TS201S processor's on-chip SDRAM controller interface supports various LVTTL (3.3V) as
well as mobile low-power SDRAM devices (2.5V), depending on size and internal organization (I/O
capability, number of rows, and page size). The following table summarizes all the supported types:
Size I/O capability Row x Page Size I/O capability Row x Page
1M x 16 2Kx 256 8M x 32 8Kx 256
16 Mbits
64 Mbits
128 Mbits
2M x 8 2Kx 512 16M x 16 8Kx 512
4M x 4 2
2M x 32 2Kx 256 8M x 32 8Kx 256
4M x 16 4Kx 256 16M x 16 8Kx 512
8M x 8 4Kx 512
16M x 4 4
4M x 32 4Kx 256
8M x 16 4Kx 512
16M x 8 4
x 1024
x 1024
x 1024
256 Mbits
32M x 8 8Kx 1024
512 Mbits
32M x 8 8Kx 1024
Table 1. Supported SDRAM devices
The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (EE-201) Page 6 of 49
6 Command Coding
6.1 Controller’s Pin Definition
Pin Type Description
~MSSD[3:0] I/O/T (pu) SDRAM banks Memory select signals
~RAS I/O/T (pu) Row select signal
~CAS I/O/T (pu) Column select signal
~SDWE I/O/T (pu) Write enable signal
HDQM O/T (pu) Mask data high lane signal
LDQM O/T (pu) Mask data low lane signal
SDA10 O/T (pu) Address10 /command select signal
SDCKE I/O/T (pu/pd) Clock enable signal
A[1:10,:12-15] I/O/T addresses for 64-bit
A[0:9,11-15] I/O/T addresses for 32-bit
A[11:15] I/O/T Bank select signal
D[63:0] I/O/T Data signals
I = input, O = output, T = Hi-Z, pd = pull-down, pu = pull-up
Table 2. ADSP-TS201 SDRAM Controller Pins Description
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6.2 Controller Command Truth Table
Table 3 provides an overview of all commands provided by the SDRAM controller. These commands are
automatically handled by the interface.
SDCKE = high
CMD SDCKE(n-1) SDCKE(n) ~MSSDx ~RAS ~CAS ~SDWE SDA10 ADDR
MRS 1 1 0 0 0 0 V V
ACT 1 1 0 0 1 1 V V
RD 1 1 0 1 0 1 0 V
WR 1 1 0 1 0 0 0 V
SDCKE = high, no validity of address
CMD SDCKE(n-1) SDCKE(n) ~MSSDx ~RAS ~CAS ~SDWE SDA10 ADDR
NOP 1 1 1 x x x x x
BST 1 1 0 1 1 0 x x
REF 1 1 0 0 0 1 1 x
PREA 1 1 0 0 1 0 1 x
Commands with SDCKE transition
CMD SDCKE(n-1) SDCKE(n) ~MSSDx ~RAS ~CAS ~SDWE SDA10 ADDR
SREF En 1 0 0 0 0 1 x x
SREF Ma 0 0 x x x X x x
SREF Ex 0 1 1 x x x x x
x=don’t care, v=valid data input, 0=logic 0, 1=logic 1, En=entry, Ma=maintain, Ex=exit
Table 3. SDRAM Commands Truth Table
The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (EE-201) Page 7 of 49
Although the SDCKE line toggles in an asynchronous manner, the commands are sampled synchronous to
the CLK signal.
Note that Power-down and Suspend modes are not supported, and that the controller does not allow auto
precharge. Lastly, keep in mind that all SDRAM commands are fully transparent to the user.
6.3 Setup and Hold Times
The synchronous operation uses the external clock as a reference. Commands, addresses, and data are
latched at the rising edge of clock. The valid time margin around the rising edge is defined as setup time
(time before rising edge) and hold time (time after rising edge) to guarantee that both the controller and
the SDRAM are working together reliably. Signal slew rates, propagation delays (PCB), and capacitive
loads (devices) influence these parameters and should be taken into consideration. Refer to the ADSP-
TS201S Data sheet for SDRAM interface AC signal specifications.
6.4 Simplified State Diagram
The following state diagram (Figure 2) shows all possible SDRAM commands sequences to help analyze
the controller’s functionality.
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The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (EE-201) Page 8 of 49
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if
"EMRS”
bit set
Core
DMA
MMS
Host
only one bank at the time
can be active
tRCD=CL
CL
1-3
Mode
Register
MRS SREF
tMRD=2 tXSR= tR C
BST
RD
tRCD
1-3
Read
burst
ACT
T
S
B
Idle
State
Row
activate
B
S
BST
WR
T
tRCD
1-3
Exit
Refresh
Counter
expired
Write
burst
Self
Refresh
(Host)
REF
Auto
Refresh
PREA
SDR A M burst:
full page
(256-512 -102 4 w ord s)
set bit
"SDRAM
enable"
Autom atic s eq ue n ce
Con t ro ll e r in p u t
Trigger MRS
Sequence
Pre-
charge
all
Controller burst:
Quad-word (128-bits)
32-bit => 4 words
64-bit => 2 words
tRAS
2-8
tRP
2-5
Figure 2. ADSP-TS201S SDRAM Controller Simplified State Diagram
The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (EE-201) Page 9 of 49
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7 SDRAM Controller Properties
Following, the ADSP-TS201S processor's on-chip SDRAM controller properties are examined:
7.1 Address Mapping Scheme
There are various possibilities when accessing the SDRAM. For instance, all rows in a bank (or all banks
in a row) can be accessed sequentially. PC DIMM modules are accessed in a different manner compared
to a typical DSP application. The ADSP-TS201S controller uses a hardware map scheme optimized for
digital signal processing.
The address mapping scheme is decoded from the page size and the bus width (both configurable by
software in the SDRCON and SYSCON registers respectively; refer to section 8 SDRAM Programming).
For more information regarding the address mapping scheme, refer to the SDRAM chapter of the ADSP-
TS201 TigerSHARC Processor Hardware Reference [1].
Figure 3 reproduces an example of the controller’s address mapping for 64-bit data. In bank A, the
SDRAM’s columns are sequentially accessed until the end of the row. Similarly, the SDRAM’s rows are
sequentially selected until the bank’s end.
Example: Address Multiplexing of a 128MBits SDRAM (4k x 512 x 4 Banks x 16bit)
(64-bit bus configuration)
Bank
Row
Column
Input:
2631
~MSSDx
~CS
25 22
23 22 21 10
14 13
23 22
14 13
21
4096 512
12 1
10
Row
8
Column
9
Controller
0
address
1. Output:
Row address
08
1
2. Output:
Column address
Figure 3. ADSP-TS201S SDRAM Controller Mapping Scheme Example
Note that only one bank may be active at a time, which results in overhead cycles when switching
between banks (off-bank accesses). Similarly, moving from one row to another (off-page access) results in
the same overhead cycles. Figure 4 shows how the ADSP-TS201S TigerSHARC processor's on-chip
SDRAM controller accesses SDRAM.
The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (EE-201) Page 10 of 49
4M x 4bit x 4 Banks, 4096 Rows, Page size 1024 words
Column
1023
Off Page
Access
Bank C
Bank D
Row 0
Row 1
Row
4095
Off Bank
Column
0
Access
On Page
Access
Bank A
Bank B
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Figure 4. ADSP-TS201S Processor SDRAM Controller Access Structure
7.2 TigerSHARC Processor SDRAM Memory Select Signals (~MSSDx)
The ADSP-TS201 TigerSHARC processor has four SDRAM Memory Select lines (~MSSD[3:0]) to
address the four SDRAM memory banks:
• ~MSSD0 – SDRAM address memory space: 0x4000 0000-0x4400 0000.
• ~MSSD1 – SDRAM address memory space: 0x5000 0000-0x5400 0000.
• ~MSSD2 – SDRAM address memory space: 0x6000 0000-0x6400 0000.
• ~MSSD3 – SDRAM address memory space: 0x7000 0000-0x7400 0000.
These signals can be used for SDRAM accesses only. In this memory region, the controller’s address
multiplexer will be active.
7.3 Burst Stop (BST)
Although the controller works in burst mode, there is one way to interrupt the burst with the burst stop
command. BST is issued if the next instruction is:
• Non external SDRAM access (access to another TigerSHARC bank)
• Core access (depending on the number of accesses, delay and external port FIFOs state)
• DMA operation (external port DMA to SDRAM interrupted by a higher priority DMA)
The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (EE-201) Page 11 of 49
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• Refresh counter expired (refresh period counter)
• SDRAM read to write and write to read transitions
• SDRAM off page/bank access
• ~HBR asserted (host interface)
• During a Bus Transition Cycle (multiprocessing)
7.4 Data Mask Function ([H:L]DQM)
The [H:L]DQM pins are used by the controller to mask write operations. HDQM masks the SDRAM DQ
buffers when performing 32-bit writes to even addresses in a 64-bit bus configuration. LDQM masks the
SDRAM DQ buffers when performing writes to odd addresses in a 64-bit bus configuration. This data
mask function does not apply for read operations, where the LDQM and HDQM pins are always low
(inactive).
This is summarized in the following table:
Bus Width* 64-bit 32-bit
Access type 32-bit Even 32-bit Odd 64-bit 32-bit Even/Odd
HDQM
LDQM
*Bus Width bit setting in SYSCON
x = don’t care, 0 = logic 0, 1 = logic 1
Table 4. [H:L]DQM Pins Functionality
1 0 0 x
0 1 0 0
7.5 SDRAM Bank Select
The connections of the address pins as bank select lines for the SDRAM device varies, depending the
operational voltage of the SDRAM device (standard or low-power) and the number of banks that the part
has.
Standard SDRAMs
The next tables show the address lines selection for the different banks:
2-banked access
Banks A[11:15] SDA10
Bank_A
Bank_B
Banks A/B
0 0
1 0
x 1
x = don’t care, 0 = logic 0, 1 = logic 1
Table 5. Bank Select Pins for 2-Banked LVTTL SDRAMs
Note: Any address line from address range A[11:15] can be used for bank select as long as it is are not
driven as a row or column address.
The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (EE-201) Page 12 of 49
4-banked access
Banks A[11,13,15] A[12,14] SDA10
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Bank_A
Bank_B
Bank_C
Bank_D
All Banks
x = don’t care, 0 = logic 0, 1 = logic 1
Table 6. Bank Select Pins for 4-Banked LVTTL SDRAMs
0 0 0
1 0 0
0 1 0
1 1 0
X X 1
Note: Any address line pair from address range A[11:15] can be used for bank select as long as they are
not driven as a row or column address.
Low-Power SDRAMs
The following tables show address line selection for the different banks:
2-banked access
Banks A[14:15] SDA10
Bank_A
Bank_B
Banks A/B
0 0
1 0
x 1
x = don’t care, 0 = logic 0, 1 = logic 1
Table 7. Bank Select Pins for 2-Banked Low-Power SDRAMs
Note: Any address line from the two address lines A[14:15] can be used for bank select as long as it is not
driven as row- or column address.
4-banked access
Banks A[14] A[15] SDA10
Bank_A
Bank_B
Bank_C
Bank_D
All Banks
x = don’t care, 0 = logic 0, 1 = logic 1
Table 8. Bank Select Pins for 4-Banked Low-Power SDRAMs
0 0 0
1 0 0
0 1 0
1 1 0
X X 1
Note: Address lines A[14:15] must be used for bank select.
The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (EE-201) Page 13 of 49
7.6 Controller Address 10 (SDA10)
This pin provides a special solution to gain control of the SDRAM, even when the processor operates as a
slave (multiprocessing). The SDA10 pin allows simultaneous access to all banks during a refresh and
precharge-all command. This pin must be connected to the A10 pin of the SDRAM.
Note: The SDA10 pin replaces the processor’s A[10] and A[11] pins in a 32-bi and 64-bit bus width
configuration, respectively. Also, during access to the ~MSSDx space, these pins are not used.
7.7 Burst Mode
Although the SDRAM device is programmed for full-page burst, the controller uses quad-word (128-bits)
burst mode. For 32-bit bus width, the burst length is 4 words; for 64-bit width, the burst length is 2 words.
Only the first read or write command is accompanied with an external address, which is driven by the
controller until the burst is interrupted by another address.
Note that the SDRAM Controller burst mode cannot be changed.
7.8 Precharge All (PREA)
This command precharges all SDRAM banks simultaneously (SDA10 must be high to select all banks),
which places the banks into the idle state.
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Although only one bank may be active at a time, the controller does not support a single bank precharge.
7.9 Circular Access
The controller supports circular accesses during sequential read or writes within a page, performing a
fixed throughput of 1 cycle/word. At the end of the page (defined in the SDRCON register), the
instructions
xR3:0=Q[j1+=last_word];;
followed by
xR7:4=Q[j1+=first_word];;
are also executed with a 1-cycle/word throughput.
This functionality is similar to the IALU’s circular buffering mode supported by the TigerSHARC
processor's core.
7.10 Auto Refresh (REF)
After the SDRAM registers the CAS before RAS refresh command, it internally asserts CAS and delayed
RAS to execute a row’s refresh. The row interval (tREFI) is typically 15,6 or 7,8 µs, depending on the
SDRAM device being used. The limit of refresh period is given by the tREFmax specification.
Note that the controller does not support burst refresh.
7.11 Self-Refresh (SREF)
The self-refresh is a very effective way of reducing the application’s power consumption to a minimum.
When a host processor gains control of the cluster bus, the TigerSHARC processor's SDRAM controller
places the SDRAM into self-refresh mode before the bus is relinquished to the host. When triggered by an
The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (EE-201) Page 14 of 49
internal timer, the SDRAM starts refreshing itself. The controller does not allow the software to place the
SDRAM into self-refresh mode, only during host accesses.
7.12 Mode Register Set (MRS)
During the MRS command, the SDRAM controller initializes the SDRAM with the following fixed
settings:
• Burst length is hardwired to full-page burst
• Burst type is hardwired to sequential burst
• Read latency (CL) is user programmable (1-3 cycles)
7.13 Extended Mode Register Set (EMRS)
Although, this is also an MRS command, the difference between the two sequences, MRS and EMRS,
relies on the data sent via the address lines driven by the TigerSHARC processor SDRAM controller (also
see section SDRAM Bank Select).
The Extended Mode register controls power-saving related functions and initializes the SDRAM with the
following fixed settings:
• Partial Array Self-Refresh (PASR) –self-refresh coverage is set to 4 banks
• Temperature Compensated Self-Refresh (TCSR) - self-refresh frequency is set to its maximum
(maximum case temperature 85°C)
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The ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (EE-201) Page 15 of 49
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