Analog Devices EE200v01 Application Notes

Engineer-to-Engineer Note EE-200

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ADSP-TS20x TigerSHARC® Processor Boot Loader Kernels Operation

Contributed by B. Lerner Rev 1 – March 4, 2004

Introduction

This EE-Note explains the functional operation
of the power-on booting procedure and the boot
loader kernels for the ADSP-TS20x
TigerSHARC® family of processors.

This EE-Note focuses on kernels for ADSP­TS201S and ADSP-TS202S processors. Kernels
for ADSP-TS203S processors form a subset of
the discussed functionality because this
processor has only two link ports and a 32-bit
external bus. Except for these restrictions, the
following information applies to all ADSP­TS20x processors.

Loader Kernels and Boot Modes

A loader kernel is a program executed by the
processor that is appended to user application
code by the elfloader utility (
VisualDSP++® development tools. The
processor executes the loader kernel processor at
boot time, allowing the processor to initialize its
internal and external memory sections defined in
the application code.

The loader kernel is a self-modifying program
that is transferred into the processor’s internal
memory. The ADSP-TS20x family of processors
supports three booting methods: EPROM booting
(via the external port), host booting (via an
external host processor or another ADSP-TS20x
processor), and link booting (via the processor’s
link ports). VisualDSP++ includes three distinct
loader kernels that support each of the

elfloader.exe) of the

processor’s booting modes. Additionally, there
are several no-boot modes, which do not require
kernels.

Booting Procedure

The booting mode is selected by the processor's

/BMS pin. While the processor is held in reset, the
/BMS pin is an active input. If /BMS is sampled

low a certain number of SCLK cycles after reset,
EPROM boot mode is selected; a number of
SCLK cycles after this, the
output and serves as the EPROM chip select. If

/BMS is sampled high instead, the ADSP-TS20x

processor will be in an idle state, waiting for a
host boot or a link port boot to occur. The exact
timing for sampling
following driving of
processor's data sheet [3].

Additionally, a weak internal pull-down resistor
is on the

/BMS pin. Depending upon the external

line loading on this pin, this pull-down resistor
may not be sufficient,. Thus, you may need to
add an external pull-down resistor to select
EPROM booting mode. If host or link boot is
desired,

/BMS must be held high during and after

reset and may be tied directly to
provided it is never used as a chip select.

Each booting method is described in detail in the
following sections.

/BMS pin becomes an

/BMS boot strap and

/BMS is provided in the

VDD_IO,

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EPROM Boot

When EPROM boot mode is selected, the ADSP­TS20x processor initializes its external port
DMA channel 0 to transfer 256 32-bit words of
code from the boot EPROM into memory block 0
locations 0x00-0xFF of the ADSP-TS20x
processor. The corresponding interrupt vector
(for DMA channel 0) is initialized to 0. Upon
completion of the DMA, the ADSP-TS20x
processor continues program execution from
location 0x00. These 256 words of code act as a
boot loader to initialize the rest of the ADSP­TS20x processor’s memory. The VisualDSP++
development tools provide a default boot loader
kernel source file (
as a reference.

TS201_prom.asm), which serves

utility takes your project's executable file (

*.dxe)

and the boot loader executable file (default:

TS201_prom.dxe) and produces an EPROM loader

output file (

*.ldr). The loader output file specifies

how various blocks of ADSP-TS20x processor’s
internal and external memory are to be initialized
during the booting process. Figure 1 describes its
format. Figure 2 describes the block tag word.

Type: 0=Final init, 1=Non-zero init, 2=Zero init

ID: ID of the processor to which the block belongs

COUNT: Number of 32-bit words in the block

Figure 2: Block Tag Word Format

The supplied boot loader (TS201_prom.dxe)
operates as follows:

1. After the boot loader is loaded, the

DMA0

interrupt wakes up the ADSP-TS20x
processor and starts execution of the loader at
location 0x00000000. At this stage, the
ADSP-TS20x processor is at interrupt level
of

DMA0; further DMA0 and global

(

SQSTAT[20]) interrupts are disabled.

2. Note the code delimited by the labels

__init_debug_start and __init_debug_end. This

code describes the final state of some of the
processor's system registers after the loader
has finished booting all of the user code. The
simulator and the emulator use this code to
set these registers to the same state when a
.

DXE file is loaded (without having to run the

loader). The RDS function is important to the
loader's operation , because it reduces the
interrupt level of

DMA0 interrupts. Before RDS;; set the NMOD

bit in the

SQCTL register to ensure that the

DMA0 and allows further

processor remains in supervisor mode. Also,

Figure 1. EPROM Loader File Format

The default EPROM boot loader works in
conjunction with the loader utility (

elfloader.exe)

all link port DMAs are disabled. The real
loader code starts at label

__init_debug_end.

3. All cache is disabled. This is not necessary
for correct loader operation but it places the

supplied with the VisualDSP++ tools. The loader

ADSP-TS20x TigerSHARC® Processor Boot Loader Kernels Operation (EE-200) Page 2 of 10

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cache in a known clean state when the user
code takes over.

4. The loader sets the
bits in the

NMOD, TRCBEN, and GIE

SQCTL register, ensuring

supervisor mode and enabling trace buffer
and global interrupts.

5. The

DMA0 interrupt vector is set to dma_int.

DMA0 is set up to move data from boot

PROM starting at 0x0400 (0x0000-0x03ff
was the boot loader) to internal memory
starting at 0x00000000. The DMA routine
starts the DMA by programming the TCBs,
advancing the PROM pointer, and sitting in
idle until the DMA interrupt wakes it up and
sends it to dma_int. There,

RTI returns to the

DMA routine, which, in turn, returns to
loader execution.

6. Registers

xR1 contains the source count, and xR5

xR7:0 will be used to start DMA0.

contains the destination count, which will
vary (and modifies which are always one and
four); thus,
individually before starting
to the value of the source

EPROM/Priority=Norm/Normal Word/Interrupt=On.
xR7 is set to value of destination DP, which is

EPROM/Priority=Norm/Normal Word/Interrupt=On.
xR0 (i.e., source address) starts at

0x00000400 (incrementing as necessary).

xR1 and xR5 will be set

DMA0. xR3 is set

DP, which is

xR4

(i.e., destination address) is set to
0x00000000.

7. The processor ID is computed and stored in

xR10.

8. The loader parses the blocks of data from the
PROM. Two words (the tag words of the
block to follow) are moved to locations
0x00000000 and 0x00000001. . In the first
word, bits 31:30 are block

TYPE (0=final init,

1=non-zero init, 2=zero init), bits 29:27 are
the processor ID, bits 26:16 are reserved and
bits 15:0 are the block
tag word is pointer to

COUNT. The second

DESTINATION.

9. The ID of the block is compared to the ID
stored in

xR10. If the IDs are not the same,

the PROM block is skipped.

10. If the IDs are the same, the type is examined.

11. If type is 1, the

COUNT number of words is

moved one word at a time via location
0x00000000 to the

DESTINATION. Once

finished, the steps starting with 8 are
repeated.

12. If type is 2, the
moved to the

COUNT number of zeros is

DESTINATION. Once finished,

the steps starting with 8 are repeated.

13. If type is 0, the loader performs the final init
(i.e., it overwrites itself with the user code).
A DMA of 256 words into 0x00000000­0x000000ff with wake up from idle would do
this, but would start user code execution at
interrupt level of DMA0. To avoid this, the
following algorithm is used:

a. First four instructions of user code

(destined to locations 0x00000000­0x00000003) are DMAed from the
PROM and stored in registers

xR11:8.

b. The following code is written into

locations 0x00000000-0x00000003:

RETI = 0;;
SQCTL = yr0;;
RTI (ABS)(NP); Q[j31+=0] = xR11:8;;

c. The DMA0 interrupt vector is set to

0x00000000.

d.

yR0 is preset to SQCTL_NMOD |
SQCTL_TRCBEN

(this disables global
interrupts when the user code starts, but
ensures that the
mode) and

TRCBEN bit (trace buffer) are

NMOD bit (supervisor

enabled. This value will be written into
the

SQCTL register in the _last_patch_code

that was relocated to 0x00000000­0x00000003.

ADSP-TS20x TigerSHARC® Processor Boot Loader Kernels Operation (EE-200) Page 3 of 10