Analog Devices EE198 Application Notes

Engineer To Engineer Note EE-198

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Technical Notes on using Analog Devices' DSP components and development tools

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User Guide to ADSP-TS201S TigerSHARC® Processor IBIS Files

Contributed by Boris Lerner July 2, 2003

Introduction

ADSP-TS201S TigerSHARC® Processor comes
with 24 IBIS files. This guide explains which file
to use under which circumstances.

Naming of IBIS Files

ADSP-TS201S IBIS files are named as
following:

TS201-dx.ibs

Where

d = 0, 1, 2, 3, 4, 5, 6 or 7: the setting of the
controlled impedance and

x = n, f or r: “n” if the processor’s ID is not zero,
“f” if the processor’s ID is zero and the falling
edge is simulated and “r” if the processor’s ID is
zero and the rising edge is simulated.

necessary internal pull-up or pull-down resistor.
On those signals, IBIS simulations will be
different for the processor with ID0 than for the
processor with a non-zero ID. Thus, separate
IBIS is provided for the non-zero IDs.

Rising and Falling Edge

This applies only to signal ACK and only on
processor with ID = 0. This signal has a different
DC behavior, depending on whether the signal is
rising or falling. On processor with ID = 0 it
always has a 500 Ohm resistor, but on rising
edge it also turns on an additional 50 Ohm
resistor to achieve a fast rise time. If this signal is
simulated, it is important to choose the correct
IBIS file, depending on whether a rising or a
falling edge is simulated. Also, this signal is the
only difference between the “f” and “r” types of
files.

Controlled Impedance

Additional Information

ADSP-TS201S allows selectable impedance
control of its drivers, depending on the setting of
CONTROLIMP[1:0] and DS[2:0] pins at reset.
Each setting will produce a different simulation
and, thus, requires a different IBIS file.

Processor ID

On the cluster bus, ADSP-TS201S processors are
distinguished by their individual processor IDs
that can range from 0 to 7. On many bussed
signals only processor with ID = 0 provides the

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It is important to note that all of the resistors
mentioned in the discussion above are, in fact,
built as transistors and, thus, do not behave
linearly as Voltage vs. Current and, moreover,
are affected by the process variations. For this
reason the simulation behavior of pulled up or
down signals with ID = 0 is not the same as the
simulation behavior of the same signal of non­zero ID with an external resistor. For proper
results, the correct model must be used.

Document History

Version Description

July 2, 2003 by Boris Lerner Initial Release

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