Analog Devices EE193 Application Notes
Engineer To Engineer Note EE-193
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Technical Notes on using Analog Devices' DSP components and development tools
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Interfacing the ADSP-BF535 Blackfin® Processor to the AD73322L Codec
Contributed by Jeff Sondermeyer, Senior DSP FAE, and Paul Ellis, Engineering Technologist, Daniels Electronics
May 13, 2003
Introduction
The AD73322L is a dual front-end processor for
general-purpose applications including speech
and telephony. It features two 16-bit A/D
conversion channels and two 16-bit D/A
conversion channels. Each channel provides
78dB signal-to-noise ratio. Over a voiceband
signal bandwidth. It also features an input-tooutput gain network in both the analog and
digital domains. This is featured on both codecs
and can be used for impedance matching or
scaling when interfacing to Subscriber Line
Interface Circuits (SLICs).
The AD73322L is particularly suited for a
variety of applications in the speech and
telephony area, including low bit rate, high
quality compression, speech enhancement,
recognition and synthesis. The low group delay
characteristic of the part (25uS typical) makes it
suitable for single or multichannel active control
applications. The AD73322L also has a flexible
serial port which allows up to four dual Codecs
to be connected in cascade providing eight
input/output channels. Furthermore, the typical
power consumption for the AD73322L device is
50mW at 3.0V. When used in conjunction with
our new low power Blackfin® processors, this
provides an overall, power efficient, end-to-end,
glueless solution suitable for handheld speech
and telephony battery operated devices.
Hardware Interface
In this application, an AD73322L is connected to
SPORT1 on the ADSP-BF535 (see Figure 1).
The AD73322L is a 16-bit Codec operating from
a single supply down to 2.7V. It has a
programmable sample rate up to 64KHz. To
avoid any voltage translation when connecting it
to the ADSP-BF535, the codec should be
operated at 3.3V (same as the Blackfin® I/O
voltage). We tested the AD73322L-ADSPBF535 interface in two configurations: single
codec, dual channel and cascaded eight channel
modes. Figure 2 shows the single, dual channel
glueless connection to the ADSP-BF535. Figure
3 shows the cascaded eight channel connection
to the ADSP-BF535 (assembly code for the
eight-channel operation is not shown in this note
but is part of the VisualDSP++™ 3.1 project ZIP
file).
In order to synchronize the codec to the ADSPBF535 processor, we connected the AD73322L
SE (serial enable) control line to the FP11 on
ADSP-BF535. This ensures that we are always
reading the proper channel from the codec after
initialization. When SE is de-asserted, the first
channel of the last device in the cascade chain is
transmitted back to the processor. In this way,
we can always identify which channel is coming
from the codec(s).
s
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Figure 1: ADDS-21535-EZLITE to Eval-AD73322LEB Interface
The /RESET pin of the AD73322L may be
connected to the system or hardware reset for the
ADSP-BF535 or it may be controlled using a
general purpose flag from the ADSP-BF535 (as
shown in Figure 2 and Figure 3). In the event of
tying it to the system reset, it is advisable to
operate the device in mixed mode, which allows
a software reset, otherwise there is not
convenient way of resetting the device.
Digital Interface
The AD73322L is designed to easily interface to
most common processors. The SCLK, SDO,
SDOFS, SDI, and SDIFS must be connected to
the ADSP-BF535’s Serial Clock, Receiver Data,
Interfacing the ADSP-BF535 Blackfin® Processor to the AD73322L Codec (EE-193) Page 2 of 36
Receive Data Frame Sync, Transmit Data and
Transmit Data Frame Sync pins respectively (See
Figure 2). Where it is required to configure a
cascade of up to eight codecs (four AD73322L
dual codecs), it is necessary to ensure that the
timing of the SE and /RESET signals be
synchronized at each device in the cascade. A
simple D type flip flop is sufficient to sync each
signal to the MCLK (master clock), as in Figure
2. Connection of a cascade of devices to a
ADSP-BF535 is no more complicated than
connecting a single device. Instead of
connecting the SDO and SDOFS to the DSP’s Rx
port, these are now daisy-chained to the SDI and
SDIFS of the next device in the cascade. The
SDO and SDOFS of the final device in the
cascade are connected to the DSP’s Rx port to
complete the chain. SE and /RESET on all
devices are fed from the signals that were
synchronized with the MCLK using the circuit as
described above. The SCLK from only one
device need be connected to the DSP’s SCLK
input(s) as all devices will be running at the same
SCLK frequency and phase. Note that SCLK in
this context does not refer to the system clock on
the ADSP-BF535 but to the serial clock on the
AD73322L.
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ADSP-BF535
RCLK1
TCLK1
RFS1
TFS1
DR1
DT1
PF10
PF11
AD73322L
SCLK
SDIFS
SDOFS
SDO
SDI
RESET
SE
Figure 2: Dual Channel CODEC-DSP connection
Interfacing the ADSP-BF535 Blackfin® Processor to the AD73322L Codec (EE-193) Page 3 of 36
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ADSP-BF53x AD73322L # 1
RCLK1
TCLK1
RFS1
TFS1
DR1
DT1
PF10
PF11
SCLK
SDIFS
SDOFS
SDO
SDI
RESET
SE
N/C
RFS1
TFS1
PF10
PF11
AD73322L # 3
SCLK
SDIFS
SDOFS
SDO
SDI
RESET
SE
PF11 from DSP
MCLK from Conv.
PF10 from DSP
MCLK from Conv.
D
CLK
D
CLK
74HC74
74HC74
PF11 to 73322
Q
PF10 to 73322
Q
RFS1
TFS1
PF10
AD73322L #2
SCLK
SDIFS
SDOFS
SDO
SDI
RESET
SE
N/CN/C
RFS1
TFS1
PF10
PF11PF11
AD73322L #4
SCLK
SDIFS
SDOFS
SDO
SDI
RESET
SE
Figure 3: Eight Channel CODEC-DSP Connection
Interfacing the ADSP-BF535 Blackfin® Processor to the AD73322L Codec (EE-193) Page 4 of 36
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ADSP-BF535 Programming Considerations
This section discusses some aspects of how the
serial port of the ADSP-BF535 should be
configured and the implications of whether Rx
and Tx interrupts should be enabled.
Following are the key settings of the ADSPBF535 SPORT required for the successful
operation with the AD73322L:
• Configure for External SPORT serial clock.
• Serial Word Length = 16 bits.
• Transmit and Receive Frame Syncs required
with every word.
• Receive Frame Sync is an input to the DSP.
• Transmit Frame Sync is an:
Input—in Frame Sync Loop-Back Mode
Output—in Nonframe Sync Loop-Back
Mode.
• Frame Syncs occur one SPORT serial clock
cycle before the MSB of the serial word.
• Frame Syncs are active high.
If SPORT interrupts are enabled, it is important
to note that the active signals on the frame sync
pins do not necessarily correspond with the
positions in time of where SPORT interrupts are
generated. On ADSP-BF535 processor, it is
necessary to enable SPORT interrupts and use
Interrupt Service Routines (ISRs) to handle
Tx/Rx activity.
ADSP-BF535 Software Considerations
Sync Loop Back (FSLB) or NonFSLB when
deciding on DSP to AFE connectivity. There is
also a choice to be made between using
autobuffering of input and output samples or
simply choosing to accept them as individual
interrupts. As most modern DSP engines support
these modes, this appendix will attempt to
discuss these topics in a generic DSP sense.
Operating Mode
The AD73322L supports two basic operating
modes: FSLB and NonFSLB. As described
previously, FSLB has some limitations when
used in Mixed Mode but is very suitable for use
with the autobuffering DMA feature that is
offered on many modern DSPs (including the
ADSP-BF535). Autobuffering allows the user to
specify the number of input or output words
(samples) that are transferred before a specific
Tx or Rx SPORT interrupt is generated. Given
that the AD73322L outputs two sample words
per sample period, it is possible using
autobuffering to have the ADSP-BF535 SPORT
generate a single interrupt on receipt of the
second of the two sample words (Appendix 1 is a
very simple autobuffer DMA example).
Additionally, both samples could be stored in a
data buffer within the data memory store. This
technique has the advantage of reducing the
number of both Tx and Rx SPORT interrupts to a
single one at each sample interval. The user also
knows where each sample is stored. The
alternative is to handle a larger number of
SPORT interrupts (twice as many in the case of a
single AD73322L) while also having some status
flags to indicate where each new sample comes
from (or is destined for).
It is important when choosing the operating
mode and hardware configuration of the
AD73322L to be aware of their implications for
ADSP-BF535 software operation. The user has
the flexibility of choosing from either Frame
Interfacing the ADSP-BF535 Blackfin® Processor to the AD73322L Codec (EE-193) Page 5 of 36
Mixed-Mode Operation
To take full advantage of mixed-mode operation,
it is necessary to configure the ADSPBF535/Codec interface in NonFSLB and to
disable autobuffering (see Appendix 2). This
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allows a variable numbers of words to be sent to
the AD73322L in each sample period—the extra
words being control words that are typically used
to update gain settings in adaptive control
applications. The recommended sequence for
updating control registers in mixed mode is to
send the control word(s) first before the DAC
update word. This EE note used this method and
provides two listings. Appendix 1 is the
assembly code for a single AD73322 codec. See
Figure 4 for a Logic Analyzer plot of the relevant
timing signals. Also, See Figure 5 for a scope
plot of necessary timing (blue=clock,
yellow=frame and purple=data). You can see
from these two figures that each 16-bit word has
a 1-bit frame signal that proceeds the data by one
SCLK. Due to this functionality, Multi-channel
Mode (MCM or TDM) SPORT modes do not
work with this codec. As a result, we are forced
to use either autobuffer DMA or interrupts to
process each and every 16-bit word.
Figure 4: Logic Analyzer of AD73322L Timing
It is possible to use mixed-mode operation when
configured in FSLB, but it is necessary to replace
the DAC update with a control word write in
each sample period which may cause some
discontinuity in the output signal due to a sample
Interfacing the ADSP-BF535 Blackfin® Processor to the AD73322L Codec (EE-193) Page 6 of 36
point being missed and the previous sample
being repeated. This however may be acceptable
in some cases as the effect may be masked by
gain changes, etc.
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Figure 5: Scope plot of two channels
Interrupts
The AD73322L transfers and receives
information over the serial connection from the
ADSP-BF535 SPORT. This occurs following
reset during the initialization phase—and in both
data-mode and mixed-mode. Each transfer of
data to or from the ADSP-BF535 can cause a
SPORT interrupt to occur. However even in
FSLB configuration where serial transfers in and
out of the DSP are synchronous, it is important to
note that Tx and Rx interrupts do not occur at the
same time due to the way that Tx and Rx
interrupts are generated internally within the
ADSP-BF535’s SPORT. This is especially
important in time critical control loop
Interfacing the ADSP-BF535 Blackfin® Processor to the AD73322L Codec (EE-193) Page 7 of 36
applications where it may be necessary to use Rx
interrupts only, as the relative positioning of the
Tx interrupts relative to the Rx interrupts in a
single sample interval are not suitable for quick
update of new DAC positions.
AD73322L Initialization
Following reset, the AD73322L is in its default
condition which ensures that the device is in
Control Mode and must be programmed or
initialized from the ADSP-BF535 to start
conversions. As communications between
AD73322L and the ADSP-BF535 are interrupt
driven, it is usually not practical to embed the
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initialization codes into the body of the
Conclusions
initialization routine. It is more practical to put
the sequence of initialization codes in a memory
buffer and to access this buffer with a pointer
that is updated on each interrupt. If a circular
buffer is used, it allows the interrupt routine to
check when the circular buffer pointer has
wrapped around—at which point the
initialization sequence is complete. In FSLB
configurations, a single control word per codec
per sample period is sent to the AD73322L
whereas in NonFSLB, it is possible to initialize
the device in a single sample period provided the
SCLK rate is programmed to a high rate. It is
also possible to use autobuffering in which case
an interrupt is generated when the entire
initialization sequence has been sent to the
This note provides the hardware interface and
assembly code for ADSP-BF535 interface to
AD73322L operating in mixed mode. While this
code example is not the most efficient in terms of
the number interrupts, it does provide the most
flexibility allowing multiple AD73322L’s to be
cascaded with full control and realtime parameter
updates. Each codec will add two additional
interrupts that must be processed. The assembly
code in this example is not fully optimized and is
not C callable. Additional work should be done
to expand the simple FSLB mode (in Appendix
1) to provide a full talkthrough utilizing Tx and
Rx autobuffer DMAs.
AD73322L.
References
[1] ADSP-BF535 Blackfin® DSP Hardware Reference. Revision 1.0, Nov. 2002, Analog Devices, Inc.
[2] AD73322L, Low Cost, Low Power CMOS General Purpose Dual Analog Front End Datasheet,
Rev 0.
[3] Eval-AD73322LEB Rev 0 evaluation board.
[4] ADDS-21535-EZLITE Rev 1.5, 2001.
[5] Blackfin® VisualDSP++™ 3.1.
Appendix 1: Simple Autobuffer DMA example
73322 Test Code.asm
/* ---------------------------------------------------------------------------- */
/* 73322 Test Code */
/* */
/* PF10 - Reset */
/* PF11 - SE */
/* */
/* 2 CODECs wired in cascade */
/* ---------------------------------------------------------------------------- */
#include <def21535.h>
#include <SportBits.h>
/* ---------------------------------------------------------------------------- */
/* Global and External Declarations */
Interfacing the ADSP-BF535 Blackfin® Processor to the AD73322L Codec (EE-193) Page 8 of 36
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.GLOBAL Start;
.EXTERN _EHANDLER;
.EXTERN _RHANDLER;
.EXTERN _NHANDLER;
.EXTERN _XHANDLER;
.EXTERN _HWHANDLER;
.EXTERN _THANDLER;
.EXTERN _RTCHANDLER;
.EXTERN _SportISR;
.EXTERN _I9HANDLER;
.EXTERN _I10HANDLER;
.EXTERN _I11HANDLER;
.EXTERN _I12HANDLER;
.EXTERN _I13HANDLER;
.EXTERN _I14HANDLER;
.EXTERN _I15HANDLER;
/* ---------------------------------------------------------------------------- */
/* Data Memory */
.SECTION Buffers;
.byte2 TxBuf[18] = // for 1 device
/*5432109876543210*/
b#1000100100000110, // CRB - DmClk=MCLK=10MHz, SCLK=MCLK,
// Fs= DMCLK/256=39.0625KHz
b#1000000100000110, // CRB - DmClk=MCLK=10MHz, SCLK=MCLK,
// Fs= DMCLK/256=39.0625KHz
b#1000101000111101, // CRC - RefOut=Disabled, Ref Power=On,
// InAmp=Off, Gain Tap=Off
b#1000001000111101, // CRC - RefOut=Disabled, Ref Power=On,
// InAmp=Off, Gain Tap=Off
b#1000101100000000, // CRD - I/O gain=0, ADC Mod=Off, Mute=Off
b#1000001100000000, // CRD - I/O gain=0, ADC Mod=Off, Mute=Off
b#1000110000000000, // CRE - Dac=0, DGain tap=Disabled,
// InterpolatorBypass=Disabled
b#1000010000000000, // CRE - Dac=0, DGain tap=Disabled,
// InterpolatorBypass=Disabled
b#1000110100000000, // CRF - A Gain Tap=0, Single Ended,
// A Gain Tap=Disables,
b#1000010000000000, // CRF - Dac=0, DGain tap=Disabled
// InterpolatorBypass=Disabled
b#1000111000000000, // CRG - Digital Gain Tap Coef0-7=0
b#1000011000000000, // CRG - Digital Gain Tap Coef0-7=0
b#1000111100000000, // CRH - Digital Gain Tap Coef8-15=0
b#1000011100000000, // CRH - Digital Gain Tap Coef8-15=0
/* 5432109876543210 */
b#1000100000010000, // CRA - Program Mode, Mixed Mode=Off,
// Dig/SPORT LoopBack=0, Device Count=1
Interfacing the ADSP-BF535 Blackfin® Processor to the AD73322L Codec (EE-193) Page 9 of 36
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b#1000000000010000, // CRA - Program Mode, Mixed Mode=Off,
// Dog/SPORT LoopBack=0, Device Count=1
b#1000100000010001, // CRA - Data Mode, Mixed Mode=Off, LoopBack=0,
// Device Count=1
b#1000000000010001; // CRA - Data Mode, Mixed Mode=Off, LoopBack=0,
// Device Count=1
.byte2 TxBuf4[32] = // for 2 devices
/*5432109876543210*/
b#1001100100001111, // CRB - DmClk=MCLK=10MHz, SCLK=MCLK,
// Fs= DMCLK/256=39.0625KHz
b#1001000100001111, // CRB - DmClk=MCLK=10MHz, SCLK=MCLK,
// Fs= DMCLK/256=39.0625KHz
b#1000100100001111, // CRB - DmClk=MCLK=10MHz, SCLK=MCLK,
// Fs= DMCLK/256=39.0625KHz
b#1000000100001111, // CRB - DmClk=MCLK=10MHz, SCLK=MCLK,
// Fs= DMCLK/256=39.0625KHz
b#1001101000100001, // CRC - RefOut=Disabled, Ref Power=On,
// InAmp=Off, Gain Tap=Off
b#1001001000100001, // CRC - ditto
b#1000101000100001, // CRC - RefOut=Disabled, Ref Power=On,
// InAmp=Off, Gain Tap=Off
b#1000001000100001, // CRC - ditto
b#1001101100000000, // CRD - I/O gain=0, ADC Mod=Off, Mute=Off
b#1001001100000000, // CRD - ditto
b#1000101100000000, // CRD - I/O gain=0, ADC Mod=Off, Mute=Off
b#1000001100000000, // CRD - ditto
b#1001110000000000, // CRE - Dac=0, InterpolatorBypass=Disabled,
// DGain tap=Disabled
b#1001010000000000, // CRE - ditto
b#1000110000000000, // CRE - Dac=0, InterpolatorBypass=Disabled,
// DGain tap=Disabled
b#1000010000000000, // CRE - ditto
b#1001110100000000, // CRF - A Gain Tap=0, Single Ended,
// A Gain Tap=Disables,
b#1001010100000000, // CRF - Input not inverted, LoopBack=Disabled,
// A Gain Tap Muted
b#1000110100000000, // CRF - A Gain Tap=0, Single Ended,
// A Gain Tap=Disables,
b#1000010100000000, // CRF - Input not inverted, LoopBack=Disabled,
// A Gain Tap Muted
b#1001111000000000, // CRG - Digital Gain Tap Coef0-7=0
b#1001011000000000, // CRG - ditto
b#1000111000000000, // CRG - Digital Gain Tap Coef0-7=0
b#1000011000000000, // CRG - ditto
b#1001111100000000, // CRH - Digital Gain Tap Coef8-15=0
b#1001011100000000, // CRH - ditto
b#1000111100000000, // CRH - Digital Gain Tap Coef8-15=0
b#1000011100000000, // CRH - ditto
b#1001100000110001, // CRA - Data Mode, Mixed Mode=Off, LoopBack=0,
Interfacing the ADSP-BF535 Blackfin® Processor to the AD73322L Codec (EE-193) Page 10 of 36
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// Device Count=1
b#1001000000110001, // CRA - Reset=Off
b#1000100000110001, // CRA - Data Mode, Mixed Mode=Off, LoopBack=0,
// Device Count=1
b#1000000000110001; // CRA - Reset=Off
#define RxBufLen 12000
.var RxBuf[RxBufLen];
/* ---------------------------------------------------------------------------- */
// Code Start.....
.Section ProgramCode;
// Note: should add in check for SIC_IMASK in Rev 0.2 and 1.0 silicon of the ADSP// BF535 (should be inverted polarity).
// Setup Event Vectors and Handlers
SETUP: R0 = 0;
LoadP0(EVT0)
r1 = _EHANDLER (Z);
r1.h = _EHANDLER; // Emulation Handler (Int0)
[ P0 ++ ] = R1;
R0 = _RHANDLER (Z);
R0.H = _RHANDLER; // Reset Handler (Int1)
[ P0 ++ ] = R0;
R0 = _NHANDLER (Z);
R0.H = _NHANDLER; // NMI Handler (Int2)
[ P0 ++ ] = R0;
R0.L = _XHANDLER;
R0.H = _XHANDLER; // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 isn't used
R0 = _HWHANDLER (Z);
R0.H = _HWHANDLER; // HW Error Handler (Int5)
[ P0 ++ ] = R0;
R0 = _THANDLER (Z);
R0.H = _THANDLER; // Timer Handler (Int6)
[ P0 ++ ] = R0;
R0 = _RTCHANDLER (Z);
R0.H = _RTCHANDLER; // IVG7 Handler
[ P0 ++ ] = R0;
R0 = _SportISR (Z);
R0.H = _SportISR; // IVG8 Handler
[ P0 ++ ] = R0;
R0 = _I9HANDLER (Z);
R0.H = _I9HANDLER; // IVG9 Handler
[ P0 ++ ] = R0;
Interfacing the ADSP-BF535 Blackfin® Processor to the AD73322L Codec (EE-193) Page 11 of 36
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