Analog Devices EE187 Application Notes

Engineer To Engineer Note EE-187

Technical Notes on using Analog Devices' DSP components and development tools

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Using the PCI Interface On The ADSP-BF535 Blackfin® Processor in Host
Mode

Contributed by Jorge Manguane April 17, 2003

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Introduction

Configuration entails allocating resources
(memory ranges, interrupt lines) to the various

The purpose of this document is to familiarize
the user with the workings of the PCI interface
on the ADSP-BF535 Blackfin® Processor.

The ADSP-BF535 Processor includes a Revision

2.2, 3.3V-compliant, 33 MHz/32-bit Peripheral
Component Interconnect (PCI) bus interface.
The interface can act as either a Host or a
Device. In Host mode, an external arbiter is

devices. Once configured, devices will respond
to transactions that fall within their allocated
memory ranges.

Note: PCI bus arbitration is not built into the
ADSP-BF535 PCI peripheral. An external PCI
bus arbiter is required (See Momentum Data
Systems Eagle-35 User Manual, Appendix B for
example PLD equations).

required. The ADSP-BF535 Processor can
master the PCI bus in both Host and Device
modes. In addition, a dedicated bus is available
on chip to allow an external bus master to
transfer data directly to internal (L2 memory) or
external memory spaces of the ADSP-BF535.

This document describes how to program the PCI
interface to function in Host mode.

Configuration Accesses

Before it can configure other devices, the PCI
core must initialize its PCI space registers
appropriately for host operation. At a minimum,
it must do the following:

1. Set bit 0 of the PCI Control Register
(PCI_CTL) register to enable host mode

Host mode

In host mode, the ADSP-BF535 PCI peripheral
acts as a system controller of the PCI bus and, as
such, it is responsible for configuring PCI
devices attached to the bus as well as arbitrating
mastership of the bus. Most PCI agents (host

2. Write to the PCI Configuration Command
Register (PCI_CFG_CMD) to enable
response to memory accesses, bus mastership

3. Write to the PCI Host Memory Control
Register(PCI_HMCTL) to tell PCI agents
what ADSP-BF535 resources can be accessed

and/or devices) can master the PCI bus; a device
can initiate a PCI transaction in the same way
that a host can, which allows for peer to peer
communications between different PCI agents.
Essentially, what differentiates a device from a

4. Set bit 1 of the PCI_CTL register to enable
PCI

To perform configuration accesses, the ADSP­BF535 PCI interface uses two resources:

host in a system is who performs the
configuration of the various PCI agents.

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0

0

1. Configuration Base Address Pointer
Register (PCI_CBAP ) is used to address the

configuration space of the devices. The
structure of the contents of this register
depends on whether a Type 0 or Type 1
configuration access is being performed. If
the device to be configured sits behind a
PCI-to-PCI Bridge, Type 1 configuration
accesses will be performed, otherwise, Type
0 accesses will be performed.

2. Configuration Data Port is a memory
location (0xEEFF FFFC) that holds the data
to be written to devices or returns data read
from devices during configuration accesses.

When performing configuration cycles, the Host
accesses a register set predefined by the PCI
specification. The specification currently defines
three Header formats:

 Header Type Two: defined for PCI-to-

CardBus bridges

 Header Type One: defined for PCI-to-PCI

bridges

 Header Type Zero: defined for all other

devices.

bridges themselves may be on the same
“primary” bus.

Alternatively, the primary bus of the second
bridge may be the secondary bus of the first
bridge, as shown in the figure below.

ADSP-

BF535DSP

CORE

Host-to-PCI

Bridge

PCI Bus 0

PCI Device

PCI-to-PCI
Bridge

PCI Device

PCI Bus 1

PCI-to-PCI

PCI Device

Bridge

PCI Bus 2

PCI Device

Figure 1

The host must traverse some or all of the
registers defined in the headers above. In this
application note, we’ll only touch on the last two
header types (header type 0, and header type 1)
since we are only concerned with configuring
PCI devices that sit directly on the PCI bus
(primary bus: Type 0 configuration) or devices
that sit behind a PCI-to-PCI bridge (secondary
bus: Type 1 configuration). Note when more
than one PCI-to-PCI bridge is present on the
system, the “secondary” bus can be anywhere
from bus #1 to bus #255 in the bus hierarchy.
Each PCI-to-PCI bridge adds a bus number to the
system. For example, if there’s only one bridge,
devices on the other side of the bridge will reside
on secondary bus #1, if there are two bridges,
devices on the other side of the second bridge
will reside on secondary bus #2, and so on. The

Using the PCI Interface On The ADSP-BF535 Blackfin

Type 0 Configuration Accesses

These accesses are directed to all PCI agents that
reside on the primary bus, including devices and
PCI-to-PCI bridges. The format of the data must
be programmed into the PCI_CBAP register
(Configuration Base Address Pointer register) as
shown below.

31 11 10 8 7 2 1 0

Function

RESERVED

Figure 2

rom the above figure,

F

Number

Target configuration
doubleword number

AD[1:0] = 00 to indicate a type zero access

indicate the target word to be accessed AD[7:2]

® Processor in Host Mode (EE-187) Page 2 of 6

DoubleWord
Number

Type 0
access