Analog Devices ee184 Application Notes

Engineer To Engineer Note EE-184
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Technical Notes on using Analog Devices' DSP components and development tools
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Interfacing EPSON S1D13806 memory display controller to Blackfin® Processors
Contributed by Michael Hennerich May 20, 2003

Introduction

The Blackfin® Processor family of products are based on an architecture that combines a dual­MAC, state-of-the-art signal processing engine, with an orthogonal RISC-like processor instruction set, and single-instruction, multiple­data (SIMD) multimedia capabilities into a single instruction set architecture. By integrating a rich set of industry leading system peripherals and memory, Blackfin Processors are the platform of choice for next generation applications that require RISC like programmability, multimedia support and leading edge signal processing in one integrated Processor.
Typical Blackfin Processor applications such as video Tele-conferencing systems, digital imaging products or Personal Digital Assistants (PDAs) all have a general for a display capability.
This EE-Note describes the hardware and software environment necessary to provide an interface between the EPSON S1D13806 Embedded Memory Display Controller and the ADSP-BF535 High Performance 300 MHz, Blackfin Processor.
The designs described in this document are presented only as examples of how such interfaces might be implemented.

S1D13806 Embedded Memory Display Controller

embedded memory supporting a wide range of CPUs and display devices. The S1D13806 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications. The S1D13806 supports all LCD panel types, CRT, TV, and additionally provides a number of differentiating features.
1280K bytes of embedded DRAM
Resolutions up to:
800x600 at a color depth of 16 bpp.
1024x768 at a color depth of 8 bpp.

Overview

The ADSP-BF535 System Bus

The External Bus Interface Unit (EBIU) on the ADSP-BF535 provides a high performance interface to a wide variety of industry-standard memory and I/O devices. The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank occupies a 64M-byte window in the processor’s address space bus system. The banks can also be configured for either 16-bit wide or 32-bit wide buses. Word or byte accesses can be controlled by the Asynchronous Byte Enable signals (
/ABE[x]).
s
The S1D13806 is a highly integrated color LCD/CRT/TV graphics controller with
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This section provides an overview of the operation of the CPU bus in order to establish interface requirements.

Asynchronous Memory Access Cycles

Once an address in the LCD block of memory is placed on the external address bus
(
ADD[2:25], /ABE3), the LCD chip select (/CS) is
driven low by signals ( appropriate cycle and insert wait states into the cycle. conjunction with
/WE0 (write low byte) and /WE1 (write high byte)
/AMS[x]. The read or write enable
/ARE or /AWE) are driven low for the
ARDY is driven low to
/ABE0 in
/ABE1 allows an external logic
byte steering. Figure 1 illustrates a typical Blackfin
asynchronous memory write cycles to the LCD controller interface.
Note: At reset, the Register/Memory Select bit in the Miscellaneous Register (
REG[001h] bit 7) is
set to 1. This means that only REG[000h] (read­only) and REG[001h] are accessible until a write to REG[001h] sets bit 7 to 0 making all registers accessible. When debugging a new hardware design, this can sometimes give the appearance that the interface is not working, so it is important to remember to clear this bit before proceeding with debugging.

Host Bus Interface Pin Mapping

Table 1 shows the functions of each Host Bus Interface signal.
ADSP-BF535 Pin Name S1D13806 Pin Name
ADDR[2:20], /ABE3 AB[1:20] DATA[0:15] DB[0:15] f
(/AWE, /ABE0, A20,A21)
f
(/AWE, /ABE1, A20,A21)
/ARE
/WE0 /WE1
/RD RD/WR
Figure 1: ADSP-BF535 Write Cycle

S1D13806 Host Bus Interface

The S1D13806 directly supports multiple processors. The S1D13806 implements a 16-bit generic little endian Host Bus Interface which is most suitable for direct connection to the ADSP­BF535 microprocessor.
The Generic Host Bus Interface is selected by the S1D13806 on the rising edge of
/RESET. After
releasing reset the bus interface signals assume their selected configuration. For details on S1D13806 configuration, refer to the “S1D13806 Technical Manual”.
/AMS[x] /CS ADDR21 M/R +VDD AB0 ARDY /WAIT +VDD /BS CLKOUT BUSCLK /RESET /RESET
Table 1: Host Bus Interface Pin Mapping

Host Bus Interface Signal Descriptions

The S1D13806 Generic Host Bus Interface requires the following signals.
BUSCLK is a clock input which is required by
the S1D13806 Host Bus Interface. It is separate from the input clock (
CLKI) and is typically
driven by the host CPU system clock (CLKOUT).
• The address inputs
DB[0:15], connect directly to the ADSP-BF535
AB[1:20], and the data bus
Interfacing EPSON S1D13806 memory display controller to Blackfin® Processors (EE-184) Page 2 of 13
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address (ADDR[2:20], /ABE3) and data bus (
DATA[0:15]), respectively. CONF[3:0] must be set
to select the Generic Host Bus Interface with little endian mode.
M/R (memory/register) selects between memory
or register access. It may be connected to an address line, allowing system address be connected to the
• Chip Select (
M/R line.
/CS) must be driven low by /AMS[x]
ADDR21 to
whenever the S1D13806 is accessed by the ADSP-BF535.
/WE0 (the low byte write enable signal) is
connected to an external decode logic conjunction with address bit 0
. /AWE, in
(/ABE0), allow
byte steering of write operations to register memory space. All other accesses are 16-bits wide (
• connected to an external decode logic conjunction with address bit 0
/WE1 and /WE0 asserted simultaneously).
/WE1 (the high byte write enable signal) is
. /AWE, in
(/ABE1), allow
byte steering of write operations to register memory space. All other accesses are 16-bits wide
(/WE1 and /WE0 asserted simultaneously).
the S1D13806 internal registers and/or display buffer. The
/WAIT line resolves these contentions
by forcing the host to wait until the resource arbitration is complete.
• The
/BS and AB0 signals are not used for the
Generic Host Bus Interface and should be connect to V

Hardware Description

DD
Figure 2 shows a typical implementation utilizing the S1D13806 memory mapped into the ADSP-BF535 address space.

S1D13806 Hardware Configuration

The S1D13806 latches CONF7 through CONF0 to allow selection of the bus mode and other configuration data on the rising edge of /RESET. For details on configuration, refer to the S1D13806 Hardware Functional Specification. Table 2 shows the configuration settings important to the Generic Host Bus Interface used by the ADSP-BF535 .
/RD and RD/WR connected to /ARE (the read
enable signal from the ADSP-BF535) and must be driven low when the ADSP-BF535 is reading data from the S1D13806. This causes all read accesses to be 16-bits wide.
/WAIT connected to ARDY and is a signal output
from the S1D13806 that indicates the ADSP­BF535 must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. Since ADSP-BF535 accesses to the S1D13806 may occur asynchronously to the display update, it is possible that contention may occur in accessing
S1D13806 Pin
Name
CONF[3:0]
CONF4
CONF5 0 = BUSCLK input not divided CONF6 1 = /WAIT is always driven
Table 2: Summary of Power-On/Reset Options
state of this pin at rising
edge of /RESET
0000 = Generic Host Bus Interface, little endian, active low /WAIT selected
Reserved. Must be tied to ground
Interfacing EPSON S1D13806 memory display controller to Blackfin® Processors (EE-184) Page 3 of 13
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Figure 2: Typical Implementation of ADSP-BF535 to S1D13806 Interface

Register/Memory Mapping

The ADSP-BF535 supports four asynchronous memory regions. Each has a unique memory select (
AMS[x]) associated with it, shown in the
Table 3.
Memory Bank Address Start Address End
AMS[0] AMS[1] AMS[2] AMS[3]
Table 3: Register/Memory Mapping
2000 0000 23FF FFFF 2400 0000 27FF FFFF 2800 0000 2BFF FFFF
2C00 0000 2FFF FFFF
The S1D13806 is a memory-mapped device. The internal registers are mapped in the lower
requires 1.25M bytes and is mapped in the third and fourth megabytes (0x20 0000 to 0x33 FFFF).
A21 A20 A12
0 0 0
0 0 1
0 1 x
1 X x
x = don’t care
Table 4: Typical Register/Memory Mapping
address space starting at zero. The display buffer
Physical
Address Range
0h2x00 0000 to 0h2x00 01FF
0h2x00 1000 to 0h2x00 1FFF
0h2x10 0000 to 0h2x1F FFFF
0h2x20 0000 to 0h2x33 FFFF
Function
Control Registers Decoded
MediaPlug Registers Decoded
BitBLT Registers Decoded
Display Buffer Decoded
Interfacing EPSON S1D13806 memory display controller to Blackfin® Processors (EE-184) Page 4 of 13
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