Analog Devices EE181 Application Notes

Engineer To Engineer Note EE-181

Technical Notes on using Analog Devices' DSP components and development tools

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Interfacing the ADSP-BF535 Blackfin® Processor to Single-CHIP CIF
Digital Camera "OV6630" over the External Memory Bus

Contributed by Thorsten Lorenzen April 17, 2003

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1 Introduction

The purpose of this note is to describe how to
hook up video devices like a CIF (Common
Interface Format) Single–Chip Digital Camera to
the external bus of the ADSP-BF535 Blackfin®
Processor. Because of its architecture and video
processing capabilities, Blackfin Processors will
interface with video devices. The ADSP-BF535
as the first part of the Blackfin family is not
equipped with a standard interface that glueless
interact with video devices. This note is
dedicated to show how the Asynchronous
Interface can be used to receive video in CIF
sizes.

2 Output Format of the OV6630

The OV6630 is a CMOS Image sensor provided
as a single chip video/imaging camera device
designed to provide a high level functionality in
a single, small-footprint package. For more
details about the functionality it is referred to the
internet address below. In order to explain the
way been accessed by the ADSP-BF535
Processor see the schematic of the required
output pins in figure 2.1. The datasheet for the
OV6630 can be found at www.ovt.com

As it can be seen in figure 2.1 the pins Y[7:0]
and UV[7:0] are required to transfer data. The
PCLK represents the clock aligned to the data.
Each raising edge of the PCLK will indicate
valid data on the bus. These pins are necessary

and must be linked to the ADSP-BF535 for data
transfers. Additionally, some pins are required
for device control and configuration purposes.
The pin HREF asserted (polarity can be chosen)
indicates active video pixels (image data).

Figure 2.1

Because of the programmable sensor size as it is
discussed below HREF provides a way to
distinguish between active video pixels and
blank data. The blank data of the modified senor
field will also be transferred and is represented
by hex “10” on Y[7:0] and hex “80” UV[7:0].
Figure 2.2 shows a transfer of one pixel,
blanking and HREF indicating an active pixel.
Due to the configuration the sensor is set to
output over a 16 -bit bus in this note. One pixel
exists of one byte of luminance and one byte of

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chrominance information that can be transferred
the same time.

Figure 2.2

The windowing feature of the OV6630 image
sensors allows user-definable window sizing as
required by the application. Window size setting
(in pixels) ranges from 2 x 2 to 356 x 292, and
can be positioned anywhere inside the 356 x 292
boundary.

Note that modifying window size and/or position
does not change frame or data rate. The OV6630
imager alters the assertion of the HREF signal to
be consistent with the programmed horizontal
and vertical region. The default output window is
352 x 288. Figure 2.3 shows it graphically.

the VSYNC pin on channel 1 and the HREF pin
on channel 4. It can be seen if the sensor is set to
transfer e.g. 200 lines the HREF will be asserted
200 times also. Each start of frame will be
indicated by VSYNC around 2 ms before HREF
asserts.

Figure 2.4

The video output port of the OV6630 image
sensor provides a number of output format /
standard options to suit many different
application requirements. These formats are user
programmable through Omnivision’s SCCB two
wire control interface.

The OV6630 imager supports both ITU-601 and
ITU-656 output formats in different
configurations.

In this note the sensor is set to provide
differential video signals (YUV) 4:2:2, 16-bit
wide and clocked at 8.867MHz (PCLK).

3 Asynchronize Interface of the ADSP-BF535 Blackfin Processor

The Processors asynchronous interface is used to
receive the video data. 32-bit data can be fetched
in a manner it is shown in figure 3.1.

Figure 2.3

In order to detect the first line of each frame the
signal VSYNC asserts before. Figure 2.4 shows

Interfacing the ADSP-BF535 Blackfin® Processor to Single-CHIP CIF Digital Camera "OV6630" over the External
Memory Bus (EE-181) Page 2 of 10

Figure 3.1

As mentioned in the ADSP-BF535 Blackfin
Hardware Reference Manual after a read cycle is
initiated the Async Memory Select line (/AMS) ,
Async Ouput Enable line (/AOE) and the Async
Read Enable line (/ARE) become asserted. After
a multicycle “Read Access” delay (Configured
by the Async Interface Bank Control Register),
the /ARE pin normally de-assert to complete the
read operation. But if the interface is configured
to extend the access, the /ARE pin remains low
until the ARDY pin has been sampled high. The
data will be fetched one cycle after this
happened.

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Figure 3.2

Note also that each DMA transfer is split into
bursts of eight accesses (in this configuration,
four bursts per DMA execution). Understanding
this behavior is crucial for developing a proper
DMA interface. Figure 3.3 zooms into one of
these burst patterns to analyze how many cycles
are taken for each access.

Due to the architecture of the ADSP-BF535, a
DMA-controlled data download is somewhat
non-intuitive. Each data transfer is split into
bursts of eight read access. After the burst, a gap
appears because of internal bus activity. Figure

3.2 illustrates this.
As shown in the figure, the first DMA is set up to

read 32 data words (shown as Channel 2, the
/ARE signal). The large gap before the next
DMA is required for loading the next DMA
descriptor.

Interfacing the ADSP-BF535 Blackfin® Processor to Single-CHIP CIF Digital Camera "OV6630" over the External
Memory Bus (EE-181) Page 3 of 10

Figure 3.3

The peripheral clock “SCLK” is displayed in
channel 1 and channel 2 shows the /ARE pin.
After eight read strobes are done nine extra
cycles are taken to place the data into internal
memory.