Analog Devices EE179v04 Application Notes
Engineer-to-Engineer Note EE-179
Technical notes on using Analog Devices DSPs, processors and development tools
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ADSP-TS20xS TigerSHARC® System Design Guidelines
Contributed by Greg F., John A., & Phil G. Rev 4 – January 15, 2005
Introduction
This EE-Note discusses specific hardware issues when
implementing a system design, which incorporates any of
the ADSP-TS20xS TigerSHARC® processors. This
document is provided as an aid to hardware engineers for
designing systems using processors with silicon revisions
of 1.0 and higher.
All of the guidelines provided in this EE-Note apply to
ADSP-TS201S, ADSP-TS202S, and ADSP-TS203S
TigerSHARC embedded processors.
Power Supplies
The ADSP-TS20xS processor has four power supply
domains V
(External I/O) and a V
(Internal), V
DD
DD_DRAM
supply is a filtered version of the V
Refer to the ADSP-TS20xS TigerSHARC Embedded
Processor Data Sheet [1] for more specific details.
• V
Power Supply
DD
The V
power supply pins are used to power all
DD
internal logic except for the internal DRAM, I/O’s and
PLL.
(Analog PLL), V
DD_A
(DRAM) domain. The V
supply.
DD
DD_IO
DD_A
• V
DD_DRAM
The V
internal embedded DRAM logic.
Ground (VSS) Supply
The ADSP-TS20xS processor contains a single ground
supply V
V
, V
DD_A
Power Supply Current
The VDD, V
can be calculated with the formulas specified in the
application note Estimating Power For The ADSP-TS201S
(EE-170) [5].
Power Supply Sequencing
There are no power sequencing requirements other than
the V
DD_DRAM
ADSP-TS201S TigerSHARC Embedded Processor Data
Sheet [1] for more information.
Supply Bypass Capacitors
Power Supply
DD_DRAM
. The V
SS
DD_DRAM
DD_A, VDD_DRAM
power supply pins provide power to the
pins are ground returns for the VDD,
SS
and V
supply pins.
DD_IO
and V
power supply currents
DD_IO
voltage must occur last. Refer to the
• V
Power Supply
DD_A
The two V
power supply pins are used to directly
DD_A
power the PLL. These pins are isolated from the
internal V
supply pins so additional decoupling and
DD
filtering circuits can be added to reduce noise.
For multiprocessor designs ADI recommends keeping
the V
to the V
supplies separate for each processor. Refer
DD_A
supply decoupling section for further
DD_A
details.
• V
Power Supply
DD_IO
The V
DD_IO
power supply pins provide power to all the
I/O’s including all the link port LVDS pins.
The ADSP-TS20xS processor requires bypass capacitors
on each supply. In many cases it is difficult to place lots of
supply bypass capacitors close to the package pins,
especially on the bottom side of the PCB. ADI
recommends that PCB designers prioritize decoupling
capacitor placement in the following order:
1. V
2. V
3. V
4. V
to VSS bypass capacitors
DD_A
to V
DD
DD_DRAM
DD_IO
bypass capacitors
SS
to V
bypass capacitors
SS
to V
bypass capacitors
SS
Low-ESR/low-ESL 0.1 µF capacitors are recommended
for proper bypassing. For higher-frequency filtering,
0.01 µF and 0.001 µF capacitors can also be used (in
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addition to the 0.1 µF capacitors), provided their
inductance is small enough. In some cases, performing
SPICE analyses of the power supply filtering
characteristics may be necessary.
Enough “bulk” capacitors must be used to prevent power
supply ripple that exceeds max/min power supply
tolerances (refer to the data sheet for the appropriate
supply tolerances) caused by current transients in the
system. Several parallel electrolytic and/or tantalum
capacitors are preferred in order to minimize ESR and to
provide sufficient capacitance.
V
The two analog (V
generator PLLs. To produce a good stable clock, systems
must provide a “clean” power supply to the V
Therefore, the system designer must pay critical attention
to bypassing and filtering of the V
decoupling capacitor placement for V
first priority over the other supplies. Figure-1 shows the
recommended design of the V
components used in this circuit should be placed as close
as possible to the V
stray capacitance.
V
V
It is recommended that the V
duplicated for each processor in multiprocessor systems.
V
Below are the minimal recommended bypass capacitor
requirements for a single processor’s V
capacitors should be duplicated for each processor in the
system.
Supply Decoupling
DD_A
) supply pins power the clock
DD_A
domain.
DD_A
supply. The
DD_A
should be given
DD_A
filtering circuit. The
DD_A
pins to minimize inductance and
DD_A
DD
SS
10uH
1uF
Place as close to
pins as possible
TS20xS #1
V
1nF
HF
SMD
DD_A
V
DD_A
V
SS
Figure-1: V
10uH
V
DD
V
SS
Supply Decoupling
DD_A
DD_A
Place as close to
pins as possible
TS20xS #N
V
1nF
HF
1uF
V
SMD
V
decoupling circuit be
• Place 10 µH inductor and 1 µF capacitor together
with good connections to V
DD, VSS,
and V
DD_A
• Place one (minimum) or two 1 nF HF SMD
capacitors as close to the V
SS
and V
DD_A
package
pins as possible.
• Make sure that the V
PCB trace isn’t close to
DD_A
any noise-generating signals.
DD_DRAM
Supply Decoupling
DD_DRAM
supply. All
DD_A
DD_A
SS
.
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1. Minimum of six 1 nF high frequency bypass
capacitors located as close to the package pins as
possible.
2. At least two 10 nF bypass capacitor located as
close to the package pins as possible.
3. At least four 0.1 µF bypass capacitors located as
close to the package pins as possible.
4. A minimum of 47 µF of “bulk” low ESR (less
then 100mΩ) capacitors for each processor
connected to the V
DD_DRAM
recommended. These capacitors are used to
reduce power supply ripple during high peak
transient currents.
• Single Electrolytic: Panasonic FK Series or
Sanyo OS-CON series
• Single tantalum: AVX TPS III series
• Multiple ganged MLC capacitors: AVX Y5V
series
V
Supply Decoupling
DD
High frequency noise on internal supplies can adversely
affect the speed of any device. It is always important to
provide robust supply bypassing for internal supplies
especially for products whose internal voltages are less
than 1.5 V. It is recommended that as many highfrequency capacitors as possible be connected to the V
supplies as close to the package pins as possible.
A minimum of 470 µF of “bulk” low ESR (less than 25
mΩ) capacitors for each processor connected to the V
supply is recommended. These capacitors are used to
reduce power supply ripple during high peak transient
currents.
1. Minimum of six 1 nF high frequency bypass
capacitors located as close to the package pins as
possible.
2. At least two 10 nF bypass capacitor located as
close to the package pins as possible.
3. At least four 0.1 µF bypass capacitors located as
close to the package pins as possible.
4. A minimum of 470 µF of “bulk” low ESR (less
than 25 mΩ) capacitors for each processor
connected to the V
supply is recommended.
DD
These capacitors are used to reduce power supply
ripple during high peak transient currents.
supply is
DD
DD
ADSP-TS20xS TigerSHARC® System Design Guidelines (EE-179) Page 2 of 14
• Single Electrolytic: Panasonic FK Series or
Sanyo OS-CON series
• Single tantalum: AVX TPS III series
• Multiple ganged MLC capacitors: AVX Y5V
series
Proper VDD supply design is critical to ensure
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operation within the data sheet specifications
under all operating conditions. Adhering to the
data sheet V
and IDD specifications will ensure
DD
that no run time system errors will occur due to
specification violations.
V
DD_IO
It is important to provide proper decoupling on the V
supply. Although not as important as the V
V
DD_DRAM
Supply Decoupling
DD_IO
, VDD, and
DD_A
supplies, careful capacitor placement and supply
ripple analysis is required to ensure adequate decoupling.
1. Minimum of six 1 nF high frequency bypass
capacitors located as close to the package pins as
possible.
2. At least two 10 nF bypass capacitor located as
close to the package pins as possible.
3. At least four 0.1 µF bypass capacitors located as
close to the package pins as possible.
4. A minimum of 100 µF of “bulk” low ESR (less
than 100 mΩ) capacitors for each processor
connected to the V
supply is recommended.
DD_IO
These capacitors are used to reduce power supply
ripple during high peak transient currents.
a
Figure-2: Recommended V
In multiprocessor (cluster bus) designs V
shared between all DSPs. It is important to make sure that
each processor has at least one (preferably more) 1 nF high
speed decoupling capacitor located close to the V
is also important to keep noise sources from coupling into
REF
signal.
REF
Pin
the V
SCLK_V
The ADSP-TS20xS contains a single SCLK_V
reference pin. This pin sets the input reference voltage for
the SCLK input pin.
The SCLK_V
voltage should be set to the value
REF
specified in the data sheet with the recommended circuit in
Figure-3. All resistor tolerances must be 1%. (For values
of R1 and R2, refer to Figure 7 of the ADSP-TS201S
TigerSHARC Embedded Processor Data Sheet [1].)
REF
circuit
REF
should be
pin. It
REF
voltage
REF
• Single Electrolytic: Panasonic FK Series or
Sanyo OS-CON series
• Single tantalum: AVX TPS III series
• Multiple MLC capacitors: AVX Y5V series
V
Pin
REF
The ADSP-TS20xS contains a single V
REF
voltage
reference pin. This pin sets the input reference voltage for
certain input pins. For the exact list of pins whose
threshold is set by V
refer to the ADSP-TS201S
REF
TigerSHARC Embedded Processor Data Sheet [1].
The V
voltage should be set to the value specified in the
REF
data sheet with recommended circuit in Figure-2 below.
Figure-3: Recommended SCLK_V
REF
In multiprocessor (cluster bus) designs, SCLK_V
should be shared between all DSPs. It is important to make
sure that each processor has at least one (preferably more)
1 nF high speed decoupling capacitor located close to the
SCLK_V
source from coupling into the SCLK_V
pin. It is also important to keep any noise
REF
REF
circuit
REF
signal.
All resistor tolerances must be 1%. (For values of R1 and
R2, refer to Figure 6 of the ADSP-TS201S TigerSHARC
Embedded Processor Data Sheet [1].)
No-Connect (NC) Pins
The ADSP-TS20xS contains several No-Connect (NC)
pins. These pins must not connect to any supply or ground
(V
DD
, V
, VDD_A, VDD_
DD_IO
, or VSS) and they must not
DRAM
connect to any other NC pin. All NC pins must be left
totally unconnected.
ADSP-TS20xS TigerSHARC® System Design Guidelines (EE-179) Page 3 of 14
Configuration Pins
The ADSP-TS20xS configuration pins SCLKRAT2-0,
ID2-0, CONTROLIMP1-0 and DS2-0 are used to select
various chip functions such as PLL clock ratio, chip-ID
and output impedance. These pins typically have either an
internal pull-up or pull-down resistor. All configuration
pins must have a constant value while the ADSP-TS20xS
is powered.
When using the default configuration, no external
connection is needed; the pin should be treated as a NC
(No Connect). For all other configurations (non default),
the pin must be connected to V
through a sufficiently strong resistor.
In multi-processor designs where configuration pins are
likely to be wired together (SCLKRAT2-0 connected to
several processor’s) make sure that a proper value of
resistor is used to override the default pull-down/up. Note
that the total resistor value is divided by the number of
processors.
For initial or prototype designs it is
L
• CONTROLIMP1-0 Configuration Pins
advantageous to have pads on the PCB for
populating strap resistors to change the default
setting for all the SCLKRAT2-0,
CONTROLIMP1-0 and DS2-0 pins.
Configuration pins, which have default pull-ups,
should have resistor pads between the pin and
and default pull-downs should have resistor
V
SS
pads between the pin and V
The CONTROLIMP0 pin has an internal pull-down
resistor and CONTROLIMP1 has an internal pull-up
resistor. These pins control output driver impedance.
Refer to Table 12 of the ADSP-TS201S TigerSHARC
Embedded Processor Data Sheet [1] for more
information on the CONTROLIMP1-0 pin values.
For all designs it is recommended to set the
L
CONTROLIMP1-0 pins to a value of “00”
(Normal), since this is the only mode
supported by IBIS model simulation.
DD_IO
DD_IO
or V
SS
.
directly or
a
• SCLKRAT2-0 Configuration Pins
The SCLKRAT2-0 pins contain an internal pull-down
resistor. These pins set the PLL multiplier, which
generates the core clock from the SCLK input.
For more information on the maximum SCLK duty
cycle specifications, and max/min SCLK frequency
specifications, refer to the ADSP-TS201S
TigerSHARC Embedded Processor Data Sheet [1].
• ID2-0 Configuration Pins
The ID2-0 pins have an internal pull-down resistor. In
single processor systems and in multiprocessor
designs where the cluster bus is not connected to any
other TS20xS device, the ID pins should be set to the
default value (000). This is because internal pullup/pull-downs on certain pins, like memory interface
and bus arbitration are enabled only when the ID2-0 =
(000). Setting the processor ID2-0 pins to (000)
eliminates the need for external resistors. Refer to
ADSP-TS201S TigerSHARC Embedded Processor
Data Sheet [1] for more details.
Note that ID2-0=[000] is the only processor which can
enable SDRAM and start the MRS sequence.
In multiprocessor designs where the cluster bus is
shared between TS20xS devices, each processor must
be programmed to a unique device ID starting with
ID2-0 = (000) and incrementing upwards. The table
and figures below describe the various configurations
and ID2-0 assignments.
ID2-0 Multiprocessor ID
000 (default) 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
• DS2-0 Configuration Pins
The DS2 and DS0 pins contain an internal pull-up
resistor. DS1 contains an internal pull-down resistor.
These pins control the drive strength of the ADSPTS20xS output drivers. For further information refer
to the ADSP-TS201S TigerSHARC Embedded
Processor Data Sheet [1] and the application note
User Guide to ADSP-TS201S TigerSHARC processor
IBIS files (EE-198) [7].
ADSP-TS20xS TigerSHARC® System Design Guidelines (EE-179) Page 4 of 14
Table-1: ID2-0 Configuration options
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• /BMS Strap Pin (EBOOT)
The /BMS strap pin sets EEPROM (default) or
External boot mode.
During reset, /RST_IN (low), a 5 kΩ pull-down
resistor is enabled on /BMS if the chip’s ID2-0 pins
are programmed to (000). All remaining DSPs ID2-0
programmed to (1 to 7), in the system, will not have
any pull-downs or pull-ups active on /BMS.
Figure-4: No cluster bus connection between TS20x
processors. (All processor ID’s must be 0)
Figure-5: Cluster bus connection between TS20x
processors. (All processor ID’s must be
unique)
Strap Pins: /BMS,/BM,TMR0E,/BUSLOCK
The ADSP-TS20xS processor contains four dual-purpose
strap pins /BMS, /BM, TMR0E and /BUSLOCK. These
strap pins select the boot-mode, SYSCON/SDRCON write
enable, link port width and interrupt (edge/level). These
strap pins also have additional functionality after reset.
When the default configuration is used, no external resistor
is needed. For all other configurations, a sufficiently strong
resistor (typically 500 Ω) connected to V
Do not strap these pins directly to any supply or any other
pin.
For designs which are driving strap pins directly from an
FPGA, ASIC or other device, refer to the data sheet for
timing details on when the strap pins are sampled and
when the FPGA, ASIC or device should stop driving strap
pin data value.
The four strap pins have an internal pull-down resistor,
pull-up resistor or no-resistor (three-state) on each pin. The
resistor type, which is connected to the I/O pad, depends
on whether /RST_IN is active (low) or if /RST_IN is deasserted (high). Refer to Table 17 (“Strap Pin Internal
Resistors”) of the ADSP-TS201S TigerSHARC Embedded
Processor Data Sheet [1] for more information.
is required.
DD_IO
To over-ride the default setting, place a sufficiently
strong resistor (typically 500 Ω) between /BMS and
.
V
DD_IO
/BMS Boot Mode
0 (default) EPROM Boot
1 External or Link port Boot
Table-2: /BMS strap options
• /BM Strap Pin (IRQEN)
The /BM strap pin sets Interrupt disable (default) or
Interrupt enable for /IRQ3-0. During reset, /RST_IN
(low), an internal pull-down resistor is enabled.
To override the default setting, place a sufficiently
strong resistor (typically 500 Ω) between /BM and
.
V
DD_IO
/BM Interrupt Enable, (IRQ3-0) Type
0 (default) Disable interrupts, level-sensitive
1 Enable interrupts, edge-sensitive
Table-3: /BM strap options
If the /BM and /BMS strap pins are high, at the deassertion of /RST_IN, the processor starts running
from the memory address selected by one of the
/IRQ3-0 signals (one /IRQ signals should be asserted).
The table below shows the starting memory address.
Interrupt Address
/IRQ0 0x3000 0000 (External Memory, /MS0)
/IRQ1 0x3800 0000 (External Memory, /MS1)
/IRQ2 0x8000 0000 (External Memory, /MSH)
/IRQ3 0x0000 0000 (Internal Memory)
Table-4: No Boot, Run From Memory Address
ADSP-TS20xS TigerSHARC® System Design Guidelines (EE-179) Page 5 of 14
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