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The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller
Contributed by Maikel Kokaly-Bannourah & Robert Hoffmann Rev 2 – December 19, 2003
1 Introduction
In systems where a Digital Signal Processor (DSP) is used to address Synchronous Dynamic Random
Access Memory (SDRAM), additional hardware and software is needed to handle the multiplexed row
and column addressing, as well as the refresh and precharge requirements of the SDRAM. The ADSPTS101S TigerSHARC® processor uses a hardware intensive solution, an on-chip SDRAM controller.
This Engineer-to-Engineer Note introduces the ADSP-TS101S on-chip SDRAM controller‘s
characteristics. The internal signal chain is shown with the necessary address-mapping scheme. The
command truth table gives detailed information about execution in the SDRAM. The important power-up
sequence summarizes detail information to start successful designs. A timing overview demonstrates the
performance for different access modes. For basic understanding of SDRAM memories, refer to “The ABC of SDRAMemory (EE-126)” [3].
Copyright 2003, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of
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no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices’ Engineer-to-Engineer Notes.
2 Table of Contents....................................................................................................................................................................2
3 Signal Chain of SDRAM........................................................................................................................................................4
5.2 Controller Command Truth Table ................................................................................................................................6
5.3 Setup and Hold Times ..................................................................................................................................................7
5.4 Simplified State Diagram..............................................................................................................................................7
6.4 Data Mask Function ([H:L]DQM)..............................................................................................................................11
6.5 SDRAM Bank Select..................................................................................................................................................11
6.8 Precharge All (PREA) ................................................................................................................................................12
6.12 Mode Register Set (MRS).........................................................................................................................................13
8.4 SDRAM Interface After Reset....................................................................................................................................19
9.1 Internal Memory and SDRAM...................................................................................................................................20
9.2 External Device and SDRAM (FLY-BY) ..................................................................................................................20
10 SDRAM Interface in Host Mode.......................................................................................................................................22
The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller (EE-178) Page 2 of 44
11.5 Bus Transition Cycle ................................................................................................................................................24
12 SDRAM and Booting..........................................................................................................................................................26
13.1 Sequential Reads without Interruption .....................................................................................................................28
13.2 Non Sequential Reads without Interruption..............................................................................................................29
13.3 Sequential Reads with minimum Interruption..........................................................................................................30
13.4 Sequential Writes without Interruption.....................................................................................................................31
13.5 Non Sequential Writes without Interruption.............................................................................................................32
13.6 Sequential Writes with minimum Interruption .........................................................................................................33
13.7 Reads between Page/Bank........................................................................................................................................34
13.8 Writes between Page/Bank.......................................................................................................................................35
13.9 Minimum Read to Write Interval..............................................................................................................................36
13.10 Minimum Write to Read Interval............................................................................................................................37
13.13 Self-Refresh and Host Accesses.............................................................................................................................40
14.2 Using PC Modules....................................................................................................................................................44
...............................................................................................................4414.3 General Rules for Optimized Performance
...............................................................................................................................................................44 16 Document History
The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller (EE-178) Page 3 of 44
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3 Signal Chain of SDRAM
The signal chain between the ADSP-TS101S, the on-chip SDRAM controller, and the external memory
device is illustrated in Figure 1 for a 64-bit bus configuration:
ADSP-TS101S
Core
DMA
SCLK
int. RD
int. WR
int. Reset
int. ACK
External
Port
Buffers
busy
~MSSD
A25:0
A31:0
(non SDRAM)
m
m
o
L
C
d
A
M
Pipe depth
D63:0
SDCKE
d
n
a
c
i
g
~SDWE
o
[H:L]DQM
~MSSD
s
s
e
x
r
e
d
l
p
i
t
l
A1:10,
u
buffer
~RAS
~CAS
SDA10
A14
r
e
A13
A12
Data
SCLK
Figure 1. ADSP-TS101 to SDRAM Signal Chain (64-bit bus configuration)
CLK
CKE
~RAS
~CAS
~WE
DQM
A10
SDRAM
~CS
BA0
BA1
A0:9,
A12,
DQ31:0
The 3 parts for the signal flow to be considered are:
• ADSP-TS101S (core, DMA engine, I/O-Processor and the address buffer
• The SDRAM Controller (control interface, delay buffer, and address multiplexer).
• SDRAM device.
The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller (EE-178) Page 4 of 44
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4 On-Chip Controller Architecture
The synchronous interface between the ADSP-TS101S and the on-chip controller can be described in 4
basic parts:
4.1 Controller Command Interface
Because of the 2 different timing protocols, the internal TigerSHARC commands are converted to comply
with the JEDEC standard for SDRAMs. The external clock, 100 MHz maximum, is used for synchronous
operation. The TigerSHARC’s internal request lines or strobes are used to access the SDRAM with pulsed
commands. The controller’s internal ACK line inserts variable wait states to the DSP during overhead
cycles, caused by DRAM technology.
4.2 TigerSHARC Output FIFO
The TigerSHARC’s output FIFO is active for external port addresses like SDRAM. With the FIFO depth
6, address pipelining for high-speed non-sequential read operations (CAS latency=3) is supported without
performance losses.
4.3 Controller Address Multiplexer
Every first read or write action is issued in multiplexed mode. A maximum of 8192 rows (64-bit bus
configuration) and 16384 rows (32-bit bus configuration) within 1024 columns can be addressed.
4.4 Controller Data Delay Buffer
If systems incorporate a heavy busload, an additional data buffers is used to decouple the input from the
capacitive load. This delay buffer in conjunction with an external buffer for SDRAM control and address
lines reduces additional logic to a minimum.
4.5 SDRAM Types
The ADSP-TS101S on-chip SDRAM controller interface supports various LVTTL SDRAM devices
depending on size and internal organization (I/O capability, number of rows, and page size). The
following table summarizes all the supported types:
Size I/O capability Row x Page SizeI/O capability Row x Page
1M x 16 2k x 2568M x 32 8k x 256
16 Mbits
64 Mbits
128 Mbits
2M x 8 2k x 51216M x 16 8k x 512
4M x 4 2k x 1024
2M x 32 2k x 2568M x 32 8k x 256
4M x 16 4k x 25616M x 16 8k x 512
8M x 8 4k x 512
16M x 4 4k x 1024
4M x 32 4k x 256
8M x 16 4k x 512
16M x 8 4k x 1024
256 Mbits
32M x 8 8k x 1024
512 Mbits
32M x 8 8k x 1024
The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller (EE-178) Page 5 of 44
5 Command Coding
5.1 Controller’s Pin Definition
Pin Type Description
~MSSD I/O/T (pu) Memory select signal
~RAS I/O/T (pu) Row select signal
~CAS I/O/T (pu) Column select signal
~SDWE I/O/T (pu) Write enable signal
HDQM O/T (pu) Mask data high lane signal
LDQM O/T (pu) Mask data low lane signal
SDA10 O/T (pu) Address10 /command select signal
SDCKE I/O/T (pu/pd) Clock enable signal
A[1:10,:12-15] I/O/T addresses for 64-bit
A[0:9,11-15] I/O/T addresses for 32-bit
A[11:15] I/O/T Bank select signal
D[63:0] I/O/T Data signals
I = input, O = output, T = Hi-Z, pd = pull-down, pu = pull-up
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5.2 Controller Command Truth Table
This section provides a table to get an overview of all commands provided by the SDRAM controller.
These commands are automatically handled by the interface.
X = don’t care, v = valid data input, 0 = logic 0, 1 = logic 1, E = entry, M = maintain, X = exit
Although the SDCKE line toggles in an asynchronous manner, the commands are sampled synchronous to
the CLK signal.
Note that Power-down and Suspend modes are not supported, and that the controller does not allow auto precharge. Lastly, keep in mind that all SDRAM commands are fully transparent to the user.
The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller (EE-178) Page 6 of 44
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5.3 Setup and Hold Times
The synchronous operation uses the external clock as a reference. Commands, addresses, and data are
latched at the rising edge of clock. The valid time margin around the rising edge is defined as setup time
(time before rising edge) and hold time (time after rising edge) to guarantee that both the controller and
the SDRAM are working reliably together. Signal’s slew rates, propagation delays (PCB), and capacitive
loads (devices) influence these parameters and should be taken into consideration. The SDRAM interface
AC Signal Specifications can be found in the “ADSP-TS101S Data Sheet” [2].
5.4 Simplified State Diagram
The following state diagram (Figure 2) shows all possible SDRAM commands sequences to help analyze
the controller’s functionality.
The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller (EE-178) Page 7 of 44
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Mode
Register
Core
DMA
MMS
Host
only one bank at the time
can be active
tRCD=CL
CL
1-3
MRSSREF
tMRD=2tXSR=2+tRC
BST
RD
tRCD
1-3
Read
burst
B
T
S
ACT
Idle
State
Row
activate
B
S
BST
WR
tRCD
T
Exit
Refresh
Counter
expired
1-3
Write
burst
Self
Refresh
(Host)
REF
Auto
Refresh
PREA
SDR A M burst:
full page
(256-512 -102 4 w ord s)
set bit
"SDRAM
enable"
Automatic sequence
Con t ro ll e r in p u t
The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller (EE-178) Page 8 of 44
Trigger MRS
Sequence
Figure 2 ADSP-TS101S SDRAM Controller Simplified State Diagram
Pre-
charge
all
Controller burst:
Quad-word (128-bits)
32-bit => 4 words
64-bit => 2 words
tRAS
2-8
tRP
2-5
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6 SDRAM Controller Properties
Following, the ADSP-TS101S on-chip SDRAM controller properties are examined:
6.1 Address Mapping Scheme
There are various possibilities when accessing the SDRAM. For instance, all rows in a bank can be
accessed sequentially, or all banks in a row. PC DIMM modules are accessed in a different manner
compared to a typical DSP application. The ADSP-TS101S controller uses a hardware map scheme
optimized for digital signal processing.
The address mapping scheme is decoded from the page size and the bus width (both configurable by
software in the SDRCON and SYSCON registers respectively; refer to section 7 SDRAM Programming).
For more information regarding the address mapping scheme, refer to the SDRAM chapter of the ADSP-TS101 TigerSHARC Processor Hardware Reference [1].
Figure 3 reproduces an example of the controller’s address mapping for 64-bit data. In bank A, the
SDRAM’s columns are sequentially accessed until the end of the row. Similarly, the SDRAM’s rows are
sequentially selected until the bank’s end.
Example: Address Multiplexing of a 128MBits SDRAM (4k x 512 x 4 Banks x 16bit)
(64-bit bus configuration)
~MSSD
~CS
2522
2631
Bank
21
23 222110
14 13
23 22
14 13
Row
4096512
121
10
Row
8
Column
9
Column
Input:
Controller
0
address
1. Output:
Row address
08
1
2. Output:
Column address
Figure 3 ADSP-TS101S SDRAM Controller Mapping Scheme Example
Note that only one bank at a time can be active, which results in some overhead cycles when switching
between banks (off-bank accesses). Similarly, moving from one row to another (off-page access) results in
the same overhead cycles. Figure 4 shows how the ADSP-TS101S TigerSHARC on-chip SDRAM
controller accesses SDRAM.
The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller (EE-178) Page 9 of 44
4M x 4bit x 4 Banks, 4096 Rows, Page size 1024 words
The fixed dedicated bank ~MSSD (A[31:26]=0x0b000001) must be used for SDRAM accesses only. In
this memory region, the controller’s address multiplexer will be active.
6.3 Burst Stop (BST)
Although the controller works in burst mode, there is one way to interrupt the burst with the burst stop
command. BST is issued if the next instruction is:
• Non external SDRAM access (access to another TigerSHARC bank)
• Core access (depending on the number of accesses, delay and external port FIFOs state)
• DMA operation (external port DMA to SDRAM interrupted by a higher priority DMA)
• Refresh counter expired (refresh period counter)
• SDRAM read to write and write to read transitions
• SDRAM off page/bank access
• ~HBR asserted (host interface)
The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller (EE-178) Page 10 of 44
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• During a Bus Transition Cycle (multiprocessing)
6.4 Data Mask Function ([H:L]DQM)
The [H:L]DQM pins are used by the controller to mask write operations. HDQM masks the SDRAM DQ
buffers when performing 32-bit writes to even addresses in a 64-bit bus configuration. LDQM masks the
SDRAM DQ buffers when performing writes to odd addresses in a 64-bit bus configuration. This data
mask function does not apply for read operations, where the LDQM and HDQM pins are always low
(inactive).
This is summarized in the following table:
Bus Width* 64-bit 32-bit
Access type 32-bit Even 32-bit Odd 64-bit 32-bit Even/Odd
HDQM
LDQM
x = don’t care 0 = logic 0, 1 = logic 1
*Bus Width bit setting in SYSCON
6.5 SDRAM Bank Select
The next tables show the address lines selection for the different banks:
Note: Any address line from address range A[11:15] can be used for bank select as long as they are not
driven as a row or column address.
Banks A[11,13,15] A[12,14] SDA10
1 0 0 x
0 1 0 0
0 0
1 0
x 1
4-banked access
Bank_A
Bank_B
Bank_C
Bank_D
All Banks
x = don’t care, 0 = logic 0, 1 = logic 1
Note: Any address line pair from address range A[11:15] can be used for bank select as long as they are
not driven as a row- or column address.
The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller (EE-178) Page 11 of 44
0 0 0
1 0 0
0 1 0
1 1 0
X X 1
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6.6 Controller Address 10 (SDA10)
This pin provides a special solution to gain control of the SDRAM, even when the DSP operates as a slave
(multiprocessing). The SDA10 pin allows access to all banks simultaneously during a refresh and
precharge-all command. This pin must be connected to the A10 pin of the SDRAM.
Note that the SDA10 pin replaces the DSP’s A[10] and A[11] pins in a 32-bit and 64-bit bus width configuration, respectively. Also, during access to the ~MSSD space, these pins are inactive.
6.7 Burst Mode
Although the SDRAM device is programmed for full page burst, the controller uses quad-word (128-bits)
burst mode. For 32-bit bus width, the burst length is 4 words, and for 64-bit width, the burst length is 2
words. Only the first read or write command is accompanied with an external address, which is driven by
the controller until the burst is interrupted by another address.
It’s also important to note that the SDRAM Controller burst mode cannot be changed.
6.8 Precharge All (PREA)
This command precharges all SDRAM banks simultaneously (SDA10 high to select all banks), which
brings the banks into idle state.
Although only one bank at a time can be active, the controller does not support a single bank precharge.
6.9 Circular Access
The controller supports circular accesses during sequential read or writes within a page, performing a
fixed throughput of 1 cycle/word. At the end of the page (defined in the SDRCON register), the
instructions xR3:0=Q[j1+=last_word];; followed by xR7:4=Q[j1+=first_word];; are
also executed with a 1 cycle/word throughput.
This functionality is similar to the IALU’s circular buffering mode supported by the TigerSHARC core.
6.10 Auto-Refresh (REF)
After the SDRAM registers the auto-refresh command, it internally asserts CAS and delays RAS to
execute a row’s refresh. The row interval is typically tRC=15,625 µs, which is a good compromise
between data access time and the refresh reliability. The limit of refresh period is given through the
tREFmax spec.
Note that the controller does not support burst refresh.
6.11 Self-Refresh (SREF)
The self-refresh is a very effective way of reducing the application’s power consumption to a minimum.
When a host processor gains control of the cluster bus, the TigerSHARC SDRAM controller brings the
SDRAM into self-refresh mode before the bus is relinquished to the host. The SDRAM starts refreshing
itself triggered by an internal timer. The controller does not allow bringing the SDRAM into self-refresh
mode by software, only during host accesses.
The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller (EE-178) Page 12 of 44
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6.12 Mode Register Set (MRS)
During the MRS command, the SDRAM controller initializes the SDRAM with the following fixed
settings:
• Burst length is hardwired to full page burst
• Burst type is hardwired to sequential burst
• Read Latency (CL) is user specified (1-3 cycles)
The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller (EE-178) Page 13 of 44
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7 SDRAM Programming
Before external bus transactions to SDRAM start, the system and SDRAM control registers must be
configured accordingly.
7.1 SYSCON Register
The SYSCON register is the system configuration register and must be configured after hardware reset at
the beginning of the source code. This register may only be configured once, and additional write to
SYSCON after the first are ignored.
This register is composed of different fields, although only the following applies for SDRAM:
Bus Width: For proper operation, ensure that the dedicated bus width bits settings is:
• 0: 32-bit bus
• 1: 64-bit bus
Note that if either the host or memory bus width is 64-bits, the multiprocessing width must also be 64-bits.
Also, using 64-bit mode, the DSP address 0 pin becomes redundant, since its information is contained in
the strobes. Therefore, this pin is not connected for SDRAM accesses in 64-bit mode (see Figure 1).
The following diagram shows the ADSP-TS101S external port data alignment for both, 32 and 64-bit bus
configurations:
Figure 5 ADSP-TS101S External Port Data Alignment
7.2 SDRCON Register
The SDRAM programming is done by the SDRCON register. Similar to SYSCON, it can only be
programmed once after reset and its value should remain unchanged during normal operation. In systems
where more than one DSP is used, this register must be programmed to the same setup in every processor.
The SDRCON bit fields are:
SDRAM Enable: set whenever an SDRAM is present in the system.
The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller (EE-178) Page 14 of 44
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