Analog Devices EE174 Application Notes

Engineer To Engineer Note EE-174

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Technical Notes on using Analog Devices' DSP components and development tools

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ADSP-TS101S TigerSHARC® Processor Boot Loader Kernels Operation

Contributed by Boris Lerner April 01, 2003

Introduction

This EE-note explains the functional operation of
the power-on booting procedure and the boot
loader kernels for the ADSP-TS101S
TigerSHARC® processor. A loader kernel is a
program executed by the DSP that is appended to
your application code by the linker utility
(linker.exe) of the VisualDSP++™ development
tools which is executed by the DSP at boot time
to allow the processor to initialize its internal and
external memory sections defined in the
application code.

The loader kernel is a self-modifying program
which is transferred into the DSP’s internal
memory. The ADSP-TS101 supports three
booting methods; EPROM booting (via the
external port), host booting (via an external host
processor or another TigerSHARC), or link
booting (via the DSP’s link ports.) Therefore,
there are three distinct loader kernels to support
each of the processor’s booting modes.

Booting Procedure For The ADSP-TS101S

The booting mode is selected by the /BMS pin of
the DSP. While the processor is held in reset, the
/BMS pin is an active input. If /BMS is sampled
low during reset, EPROM boot mode is selected;
after the /RESET signal of the DSP is de­asserted, the /BMS pin becomes an output acting
as the EPROM chip select. If /BMS is sampled
high during reset, the TigerSHARC will be in an

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IDLE state, waiting for a host boot or a link port
boot to occur.

Additionally, there is a weak internal pull-down
resistor on the /BMS pin, but it is important to
note here that the pull-down may not be
sufficient, depending upon the external line
loading on this pin. Thus, an external pull-down
resistor may be necessary to select EPROM
booting mode. If host or link boot is desired,
/BMS must be held high during reset and may be
tied directly to VCC.

Each booting method is described in detail in the
following sections.

EPROM Boot

When EPROM boot mode is selected, the
TigerSHARC initializes its external port DMA
channel 0 to transfer 256 32-bit words of code
from the boot EPROM into the TigerSHARC’s
internal memory block 0, locations 0x00-0xFF.
The corresponding interrupt vector (for DMA
channel 0) is initialized to 0. Thus, upon
completion of the DMA, the TigerSHARC
continues its program execution from location
0x00. It is intended that these 256 words of code
act as a boot loader to initialize the rest of the
TigerSHARC’s memory. Analog Devices
provides a default boot loader kernel source file
with the VisualDSP++ development tools, called
“TS101_prom.asm”, which can be used as a
reference.

The default EPROM boot loader works in
conjunction with the loader utility (elfloader.exe)

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supplied with the VisualDSP++ tools. The loader
utility takes the user’s executable file (*.dxe)
from their project and the boot loader executable
file (default: TS101_prom.dxe) and produces the
EPROM loader output file (*.ldr). This loader
output file defines how the various blocks of
TigerSHARC’s internal and external memory are
to be initialized during the booting process. Its
format is described in figure 1. The format of the
block tag word is described in figure 2.

The supplied boot loader (TS101_prom.dxe)
operates as described below:

1. After the boot loader kernel is loaded into the
internal memory block 0 of the DSP, the
DMA0 interrupt exits the TigerSHARC from
its idle state. The DSP then begins execution
of the boot loader at location 0x00000000. At
this stage, the TigerSHARC is at the interrupt
level of DMA0 and, thus, further DMA0 and
global (PMASK[60]) interrupts are disabled.

2. The boot loader kernel sets the NMOD bit in
the SQCTL register to ensure that the DSP
will be running in supervisor mode. An RDS
instruction reduces the current interrupt to a
subroutine level. Next, DMA0 and global
interrupts are enabled again.

3. DMA0 is configured to move data from the
boot EPROM starting at address 0x0400 of
the EPROM (0x0000-0x03ff was the boot
loader) to the DSP’s internal memory starting
at address 0x00000000. The DMA routine
will start the DMA by programming the
TCBs, advance the prom pointer and sit in
IDLE until the DMA interrupt wakes it up and
sends the program sequencer to point to the
DMA0 interrupt vector. There, an RTI
instruction returns to the DMA routine, which
in turn, returns to continue execution of the
boot loader kernel.

4. Since this is not a link port boot, all of the link
port DMA channel control registers are reset
and all of the link port DMAs are disabled.

Figure 1 EPROM Loader Format

5. The processor ID (for this processor) is
computed and stored in register xR10.

6. Next, the boot loader kernel parses the blocks
of data from the EPROM. Two words are

Type: 0=Final init, 1=Non-zero init, 2=Zero Init
ID: ID of the processor to which the block belongs
COUNT: Number of 32-bit words in the block

moved to memory locations 0x00000000 and
0x00000001. These are the tag words of the
block to follow. In the first word, bits 31:30
are the block TYPE (0=final init, 1=non-zero
init, 2=zero init), bits 29:27 are the processor

Figure 2 Tag Word Format

ADSP-TS101S TigerSHARC® Processor Boot Loader Kernels Operation (EE-174) Page 2 of 9

ID, bits 26:16 are reserved, and bits 15:0 are

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the block COUNT. The second tag word is a
pointer to the DESTINATION address.

7. The ID of the block is compared to the
processor ID stored in register xR10. If the
two IDs are not the same, then this EPROM
block is skipped. The size of the block to be
skipped is obtained using the values from
TYPE and COUNT.

8. If the IDs are the same, then the TYPE is
examined.

9. If the TYPE is 1, COUNT number of words
are moved one word at a time via location
0x00000000 to the DESTINATION address.
Once finished, the algorithm returns to step 5
and repeats.

10. If the TYPE is 2, COUNT number of zeros
are moved to the DESTINATION address.
Once finished, the algorithm returns to step 5
and repeats.

11. If TYPE is 0, the boot loader kernel performs
the “Final Init”, i.e. it overwrites itself with
the user application code. A final DMA of
256 words into addresses 0x00000000­0x000000ff with a wake up from an IDLE
condition would do this, but in this case, this
would begin execution of the user application
code at interrupt level of DMA0. To avoid
this scenario, the following algorithm is used:

a. The first four instructions of the user

application code (destined to reside in
locations 0x00000000-0x00000003) are
DMAed from the EPROM and stored in
the registers xR11:8.

b. The following code is written into

locations 0x00000000-0x00000003:

RETI = 0;;
NOP;;
RTI (NP); Q[j31+=0] = xR11:8;;

d. The Branch Target Buffer is invalidated

(BTBINV) to clear any cached branches.

e. The DMA is setup to transfer 252 words of

user code destined to 0x00000004­0x000000ff.

f. The DMA is started by writing to the

TCBs; then processor goes into an IDLE
state.

g. When the DMA is finished, the DMA

complete interrupt wakes the TigerSHARC
up and the program sequencer jumps to the
to code inserted at 0x00000000 in step b,
and begins execution of this code.

h. This code executes the following

instruction,

RTI (NP); Q[j31+=0]=xR11:8;;

which reduces the interrupt level to none,
puts the user application code into
locations 0x00000000-0x00000003, and
the sequencer jumps to address
0x00000000 to continue execution (since
RETI is set to 0x00000000). The user
application code starts cleanly at
0x00000000, with no interrupt level. Note
that the “no predict” (NP) option is
necessary so that this RTI instruction does
not cache into the BTB.

It is important to note if external memory which
is being used in the system requires special
initialization (such as SDRAM, for example),
then this memory needs to be configured by the
boot loader kernel. This memory configuration
must precede its initialization in the boot loader
kernel. Thus, the boot loader has to be modified
by the user and re-built to their specific
application and system requirements.

Host Boot

c. The DMA0 interrupt vector is set to

0x00000000.

ADSP-TS101S TigerSHARC® Processor Boot Loader Kernels Operation (EE-174) Page 3 of 9

When a host or link boot is selected, the
TigerSHARC enters an idle state after reset,
waiting for the external host processor or link
port to boot it. Host booting uses the