Analog Devices EE172 Application Notes
Engineer To Engineer Note EE-172
s
a
Technical Notes on using Analog Devices' DSP components and development tools
Contact our technical support by phone: (800) ANALOG-D or e-mail: dsp.support@analog.com
Or vi sit ou r on-l ine re sourc es ht tp:// www.analog.com/dsp and http://www.analog.com/dsp/EZAnswer
Using the Dynamic Power Management Functionality of the ADSP-BF535
Blackfin® Processor
Contributed by Ching Lam May 13, 2003
Introduction
The ADSP-BF535 Blackfin® processor is ideal
for power-sensitive multimedia applications
because it provides support for a multi-tiered
approach to power management. That is, the
processing performance level can be tuned within
an application to maximize power savings.
The ADSP-BF535 Dynamic Power Management
functionality includes the following components:
• Software control of Core Clock (CCLK)
• Software control of System Clock (SCLK)
• Software control of the Phase Locked Loop
(PLL)
• Dynamic Voltage Control by interfacing to an
external voltage controller
Changes in operating voltage and frequency
result in significant savings in power
consumption. These savings can be modeled by
the following equation:
PR/PN=(FCR/FCN)(V
DDR/VDDN
where
• PR/PN is the ratio of reduced power to nominal
power
• FCN is the nominal core clock frequency
• F
• V
• V
• T
• T
Copyright 2003, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of customers’
products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property of their
respective holders. Information furnished by Analog Devices Applications and Development Tools Engineers is believed to be accurate and reliable, however no
responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices’ Engineer-to-Engineer Notes.
is the reduced core clock frequency
CR
is the nominal internal supply voltage
DDN
is the reduced internal supply voltage
DDR
is the duration running at FCR
FR
is the duration running at FCN
FN
)2(TFR/ TFN)
As an example, consider the following scenario:
• FCN = 300 MHz
• FCR = 100 MHz
• V
• V
DDN
DDR
= 1.5 V
= 1.0V
• TFR = 3
• TFN = 1
Thus,
(PR/PN)=(100/300)(1.0/1.5)²(3/1) = 0.44 Î
56% savings
Since Blackfin Processors not only have a
programmable operating frequency, but also
allow core voltage to be changed in concert with
frequency changes, less power will be consumed
when running a section of code at a lower
frequency and a lower voltage, even if execution
time is longer.
The remainder of this application note details how
the frequency can be modified on the ADSPBF535. In addition, an example of changing core
voltage on the ADSP-BF535 EZ-KIT Lite™ is
included. The ADSP-BF535 EZ-KIT Lite
provides a prototype capability to allow core
voltage changes by setting programmable flag
pins connected to an external power management
chip.
The data sheet for the ADSP-BF535
L
contains a frequency vs. voltage graph
outlining acceptable CCLK and
VddCore combinations. The data sheet
a
must be reviewed prior to running your
application with different frequency and
voltage combinations.
Clock
The input clock, CLKIN, provides the necessary
clock frequency to allow for the derivation of the
core clock (CCLK) and system clock (SCLK)
frequencies. The ADSP-BF535 has external pins
that are sampled on reset to determine a
multiplication factor (MSEL) and a divide factor
(SSEL). MSEL is used to determine the core
clock frequency (CCLK) and SSEL is used to
determine the system clock (SCLK) frequency.
Both of these values can additionally be
controlled by programming registers. CLKIN is
multiplied up by the MSEL value to obtain
CCLK. SSEL is used to divide down the CCLK
value to obtain SCLK.
CCLK is the core execution clock rate and SCLK
is used by the peripherals and external memory.
Control Register. The possible dividing factors
are 2, 2.5, 3, or 4.
Dynamic Power Management Controller
The Dynamic Power Management Controller
consists of two main components which allows
flexibility in managing power dissipation on the
ADSP-BF535:
• Operating Modes
• Peripheral Clocking
Operating Modes
Four different operating modes control the power
savings of the ADSP-BF535:
• Full-On Mode
• Active Mode
• Sleep Mode
• Deep Sleep Mode
Phase Locked Loop (PLL)
Figure 1. PLL Control Register (PLL_CTL)
The PLL provides a multiplying factor between
the ranges of 1 to 31 times the input clock,
CLKIN, by programming the MSEL bits in the
PLL Control Register. The PLL also supplies the
factor by which CCLK is divided to produce
SCLK by programming the SSEL bits in the PLL
Full-On Mode
In this mode, the PLL, CCLK, and SCLK are
enabled. However, the PLL is not in bypass.
This mode does not allow the CLKIN to CCLK
multiplying factor to be changed. From this
mode, the processor can transition to any of the
other three modes.
Active Mode
In this mode, the PLL, CCLK, and SCLK are
enabled. However, the PLL is in bypass as well.
This puts CCLK at one-half the value of CLKIN.
The option to disable the PLL in this mode is also
available. From this mode, the processor can
transition to any of the other three modes.
Sleep Mode
In this mode, the PLL and SCLK are enabled.
However, CCLK is disabled. Depending on the
previous state, the PLL could be bypassed or
Using the Dynamic Power Management Functionality of the ADSP-BF535 Blackfin® Processor (EE-172) Page 2 of 8
a
enabled. Since CCLK is disabled, SCLK
continues to run at the previous state’s frequency.
From this mode, the processor can transition to
either Full-On Mode or Active Mode. A wakeup
event causes the processor to transition out of this
mode.
Deep Sleep Mode
In this mode, the PLL, CCLK, and SCLK are all
disabled. From this mode, the processor can
transition to the Active Mode through a Real
Time Clock interrupt. The processor can also
transition to either Full-On Mode or Active Mode
through a hardware reset.
Peripheral Clocking
In addition to the different operating modes
described above, the peripherals can be
individually enabled or disabled. By default, the
peripherals are all enabled. However, each
peripheral can be disabled by setting the
corresponding bit in the Peripheral Clock Enable
Register (PLL_IOCK).
modify the operating voltage of the ADSPBF535.
For the purpose of this EE-Note, only the
implementation on the ADSP-BF535 EZ-KIT
Lite will be discussed.
Implementation
As described above, there are four possible
operating modes to transition among. There are
also a range of operating voltages and frequencies
that the core can be programmed to run at. The
following sections will describe in detail how to
implement some of these mode, voltage, and
frequency transitions.
Changing Modes
To transition between the different operating
modes, a specific setup sequence must be
followed. The general procedure that should be
followed is:
1) Program the wakeup event to bring the core
out of idle mode.
2) Program the PLL.
3) Disable interrupts.
4) Flush the pipeline, and place the core into an
idle state.
5) Reinstate interrupts.
6) Transitioned into new mode.
Figure 2. Peripheral Clock Enable Register
Dynamic Voltage Control
The ADSP-BF535’s operating voltage can be
changed dynamically via two methods.
For the ADSP-BF535 EZ-KIT Lite, a prototype
solution has been implemented to dynamically
change the core voltage via three programmable
flag pins, PF12, PF13, and PF14.
For production silicon, an external programmable
voltage regulator, the ADP-3053, is available to
Using the Dynamic Power Management Functionality of the ADSP-BF535 Blackfin® Processor (EE-172) Page 3 of 8
Wakeup Events
The ADSP-BF535’s peripherals can be enabled to
generate a wakeup event to bring the core out of
an idle state. The System Interrupt WakeupEnable Register (SIC_IWR) configures which
peripherals are enabled to wakeup the core.
In the examples that follow, the software
watchdog timer will be used as the peripheral that
generates a wakeup event to the core.
Loading...