Analog Devices EE170v01 Application Notes

Engineer-to-Engineer Note EE-170

a

Technical notes on using Analog Devices DSPs, processors and development tools

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Estimating Power for ADSP-TS201S TigerSHARC® Processors

Contributed by Greg F. Rev 1 - January 3, 2005

Introduction

This EE-Note discusses techniques for
estimating the power consumption for an ADSP­TS201S TigerSHARC® processor. This
document assists board designers by providing
data and recommendations, allowing them to
estimate their budgets for power supply and
thermal relief designs for a given system.

ADSP-TS201S processors are members of the
ultra-high-performance, static superscalar, 32-bit
TigerSHARC processor family. This processor is
offered in two different speed grades, which
allow the core to operate at a maximum clock
frequency of either 500 or 600 MHz. The
processor also requires three separate external
voltage supplies, as shown in Table 1.

ADSP-TS201S
Voltage Domain

VDD 1.05V +/- 5% 1.20V +/- 5%
V
V

Table 1. Voltage Supply Requirements

1.50V +/- 5% 1.60V +/- 5%

DD_DRAM

2.50V +/- 5% 2.50V +/- 5%

DD_IO

Core Clock Rate
500 MHz

Core Clock Rate
600 MHz

The following sections explain how to derive
power numbers for a given system based on the
different internal dynamic activity levels
(instruction, data, and DMA sequence), I/O
activity, and environmental operating conditions.
Details describing the activity levels are also
provided.

VDD Current Consumption

The total internal current consumption (IDD) on
the VDD supply is the sum of the static and
dynamic components of the processor.

Since the dynamic activity of the processor is
dependent on the instruction execution sequence
of the application code and the data operands
involved, a good understanding of the instruction
execution is important in estimating the dynamic
current (I

DD_DYN

core. The dynamic current consumption can be
calculated by multiplying the weighted average
of the different activity levels by a baseline
dynamic current characteristic. For details on this
characteristic, see IDD_BASELINE Dynamic

Current Characteristic Graph.

) consumed by the processor

A precise understanding of the application

Power Consumption

The total power consumed by the ADSP-TS201S
device is the sum of the power consumed on each
of the voltage domains (V
of the processor. This sum consists of the
internal core logic, the I/O logic, the internal
DRAM, and the related circuitry for each of
these domains.

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DD

, V

DD_DRAM

, V

DD_IO

)

program can be achieved by profiling the
program execution (or by accurately estimating
the average code activity levels for specific
portions of the program). The goal of profiling is
to determine the percentage of execution time
each activity level occupies. These dynamic core
activity levels are explained in detail in the
following section.

a

Internal Dynamic Activity Level Definitions

The following definitions apply to the internal
dynamic activity levels (I

Table 2. Excluding the I

DD_DMA

DD_DYN

) shown in

and I

DD_IDLE

activity levels, each activity level contains no
stall cycles, and therefore represents worst-case
processor core activity.

• IDD_CLU_HIGH – Sustained high-activity

operations of the CLU defined as an
XCORRS instruction along with two parallel
quad-word data fetches executing every
cycle. Concurrently, either a 64-bit parallel
ALU, a SIMD quad 16-bit complex multiply,
or a 64-bit dual-Trellis History register
update operation is executed in the same
cycle. The data fetched and operated on are
random; the data and instructions reside in
independent memory segments to allow the
highest data throughput and to ensure that no
stall cycles are incurred. This I

DD_CLU_HIGH

activity level also includes a concurrent
external port DMA sequence, as described in
the I

DD_DMA

activity level.

• IDD_CLU_TYP – Sustained typical activity

operations of the CLU defined as a
combination of the ACS and PERMUTE
instructions: The ACS instruction occurs in
parallel with a quad-word Trellis History
register read, along with a long-word
memory access; the PERMUTE instruction
occurs in parallel with two quad-word data
fetches. The data fetched and operated on are
random; the data and instructions reside in
independent memory segments to allow the
highest data throughput and to ensure that no
stall cycles are incurred. This I

DD_CLU_TYP

activity level also includes a concurrent
external port DMA sequence, as described in
the I

DD_DMA

activity level.

• IDD_CLU_LOW – Sustained low-activity

operations of the CLU defined as either a
TMAX or MAX instruction, along with two
parallel quad-word data fetches, and a shifter
operation occurring in each compute block

executing every cycle. The data fetched and
operated on are random; the data and
instructions reside in independent memory
segments to allow the highest data
throughput and to ensure that no stall cycles
are incurred. This I

DD_CLU_LOW

activity level
also includes a concurrent external port DMA
sequence, as described in the I

DD_DMA

activity

level.

• IDD_FFT – Sustained high-activity floating-

point operations of the computational units of
the processor core. This activity level is a
SIMD floating-point add/subtract dual
operation along with one of the following: a
quad-word merged access, a single quad­word data access, a SIMD floating-point
multiply, and a quad-word merged access; or
a SIMD floating-point multiply, a quad-word
merged access, and a long-word access to
two general-purpose registers within one of
the computational units. The data fetched and
operated on are random; data and instructions
reside in independent memory segments to
allow the highest data throughput and to
ensure that no stall cycles are incurred. This

I

DD_FFT

activity level also includes a
concurrent external port DMA sequence, as
described in the I

DD_DMA

activity level.

• IDD_COMPUTE_HIGH – Sustained high-

activity operations of the computational units
of the processor core. This activity level is
one of the following: a SIMD quad 16-bit
fixed-point multiply and a SIMD quad 16-bit
fixed-point addition in parallel, or a SIMD
extended floating-point multiply and a SIMD
extended floating-point addition in parallel.
Concurrently, dual merged-memory fetches
are executed. The data fetched and operated
on are random. This I

DD_COMPUTE_HIGH

activity
level definition also includes a concurrent
external port DMA sequence, as described in
the I

DD_DMA

activity level definition below.

Estimating Power for ADSP-TS201S TigerSHARC® Processors (EE-170) Page 2 of 16

a

• IDD_COMPUTE_TYP – Sustained typical

activity operations of the computational units
of the processor core. This activity level is
one of the following: a SIMD quad 16-bit
fixed-point multiply, a SIMD quad 16-bit
fixed-point addition, a SIMD extended-
precision floating-point multiply, or a SIMD
extended-precision floating-point addition.
One of these instructions occurs in parallel
with two quad-word data fetches. The data
fetched and operated on are random. This

I

DD_COMPUTE_TYP

activity level also includes a
concurrent external port DMA sequence, as
described in the I

DD_DMA

activity level.

• IDD_CTRL – Control activity is a

continuous decision-making sequence of
instructions and predicted branches. The
branch prediction is deliberately set to be
incorrect 50% of the time to allow for equal
distribution. This I

DD_CTRL

activity level
definition also includes the DMA activity
level as described in the I

DD_DMA

activity

level.

• IDD_DMA – DMA activity is a single-

channel external port DMA from external
memory to internal memory, using
quad-word transfers of 32 words total. The
DMA is chained to itself (in order to run
continuously), and does not use interrupts.
After initializing the DMA sequence, the
processor core is not involved; it executes the

IDLE;; instruction only.

• IDD_IDLE – VDD supply current for idle

activity. This activity level is defined as the
processor core executing an

IDLE;;

instruction only, with no active DMAs or
interrupts.

Estimating Dynamic Current Consumption

Two steps are involved in estimating the
dynamic current consumption on the V

DD

domain. The first step determines the dynamic
baseline current. The second step determines the
percentage of activity for each of the discrete
vectors with respect to the entire application
code.

I

DD_BASELINE

Dynamic Current

Characteristic Graph

The ADSP-TS201S I

DD_BASELINE

dynamic current
characteristic graph is shown in Figure 1.
(Appendix B contains a larger image of this
graph.) Each line in the graph represents a
baseline I

dynamic internal current value for a

DD

specific given voltage. To calculate the baseline
dynamic current (I

DD_BASELINE

) on the VDD voltage
domain, take the line on the graph that represents
the operating voltage of the processor and find
the point on this line for the specific operating
frequency of each processor in the system. From
this point on the curve, the baseline value for the
dynamic current can be determined by finding its
point of intersection with the vertical axis on the
left side labeled “Dynamic Current”.

ADSP-TS201S Dynamic IDD Compute High Activity

3.5

3

2.5

2

1.5

Dynamic Current (Amp)

1

0.5

0

0 100 200 300 400 500 600 700

Figure 1. Dynamic Baseline Current Characteristic

Core Freqency (MHz)

1.25V

1.20V

1.15V

1.10V

1.05V

1.00V

Assume that the TigerSHARC processors in the
example system are operating at 500 MHz at

1.05 V. From the graph in Figure 1, these two
parameters will yield a result of 2.05 A for the
dynamic baseline current.

Estimating Power for ADSP-TS201S TigerSHARC® Processors (EE-170) Page 3 of 16

a

From the activity level definitions described in

Internal Dynamic Activity Level Definitions, and

after profiling the application program, the
percentage of overall execution time for each
activity level can be determined.

Table 2 lists the scale factor for each activity

level, which are used to estimate the dynamic
current (I

Power Vector Name Activity Factor Value

I

DD_CLU_HIGH

I

DD_CLU_TYP

I

DD_CLU_LOW

I

DD_FFT

I

DD_COMPUTE_ HIGH

I

DD_COMPUTE_ TYP

I

DD_CTRL

I

DD_DMA

I

DD_IDLE

DD_DYN

1.17

0.71

0.57

0.55

Table 2. Internal Dynamic Core Current (IDD_DYN)

) for a specific application.

1.45

1.14

0.98

1.00

0.85

The processor core dynamic current can be
calculated by multiplying the value of the
dynamic baseline current by the activity factor
value for each discrete vector, and then
multiplying this result by the percentage of time
spent for each vector in the application program.
This step is shown in Equation 1.

(% I

DD_CLU_HIGH

(% I

DD_CLU_TYP

(% I

DD_CLU_LOW

(% I

DD_FFT

(% I

DD_COMPUTE_ HIGH

(% I

DD_COMPUTE_ TYP

(% I

DD_CTRL

(% I

DD_DMA

+ (% I

DD_IDLE

= Total Weighted Average Dynamic Current for V
= I

DD_DYN

Equation 1. I

x I

DD_CLU_HIGH

x I

DD_CLU_TYP

x I

DD_CLU_LOW

x I

x I

DD_FFT

x I

x I

Activity Factor x I

x I

x I

Activity Factor x I

DD_CTRL

Activity Factor x I

DD_DMA

Activity Factor x I

DD_IDLE

Core Dynamic Current

DD_DYN

Activity Factor x I

Activity Factor x I

Activity Factor x I

DD_COMP_HIGH

DD_COMP_TYP

Activity Factor x I

DD_BASELINE

DD_BASELINE

DD_BASELINE

DD

)

)

)

)

DD_BASELINE

DD_BASELINE

Activity Factor x I

DD_BASELINE

DD_BASELINE

DD_BASELINE

)

)

)

DD_BASELINE

)

Example: Assume that for a given system, the
profile of the application code is as follows:

0% IDD_CLU_HIGH Activity Level

0% IDD_CLU_TYP Activity Level
0% IDD_CLU_LOW Activity Level
15% IDD_FFT Activity Level
20% IDD_COMPUTE_ HIGH Activity Level
50% IDD_COMPUTE_ TYP Activity Level

15% IDD_CTRL Activity Level
0% IDD_DMA Activity Level
0% IDD_IDLE Activity Level

Example 1. Internal System Activity Level

From the percentages of this example, the core
dynamic current (I

DD_DYN

) for a single processor

can be calculated using Equation 1 as follows:

(15% x 1.17 x 2.05)
(20% x 1.00 x 2.05)
(50% x 0.85 x 2.05)

+ (15% x 0.71 x 2.05)
= 1.86 A

Example 2. Total Estimated Dynamic Current

Therefore, the total estimated dynamic current on
the VDD supply is 1.86 A.

I

DD_STATIC

Baseline Characteristic

Curve

The I

DD_STATIC

baseline characteristic curve is
used to calculate the static power on the VDD
voltage domain. Because the static power
consumed on VDD is a function of temperature
and voltage (and not a function of frequency),
this static power level does not need to be
calculated for each discrete internal power vector

)

definition. The static power is simply added to
the total estimated dynamic current value
(I

DD_DYN

), which was calculated earlier.

Figure 2 shows the static baseline current for

typical devices. A typical device is defined as a
device whose static current consumption lies at
the mid-point of the probability density
distribution of the entire population of devices.
The curves in Figure 2 can be used to calculate

Estimating Power for ADSP-TS201S TigerSHARC® Processors (EE-170) Page 4 of 16

a

the statistical average static power for all of the
ADSP-TS201S devices in a system.

ADSP-TS201S - Typical Baseline Static Idd Current vs. Case Temperature

2

1.8

1.6

1.4

1.2

1

Current (Amps)

0.8

0.6

0.4

0.2

0

-45 -25 -5 15 35 55 75 95 115

Case Temperature (degC)

1.25V

1.20V

1.15V

1.10V

1.05V

1.00V

Figure 2. Typical Static Current Characteristic Graph

Each line in Figure 2 represents a baseline static
internal current value at a given voltage. To
calculate the total static current (I

DD_STATIC

) on the
VDD voltage domain, take the line on the graph
that represents the voltage of the device and find
the point on this line for the specific case
temperature at which the processors in the
system will operate. From this point on the
curve, the value for the baseline static current
can be estimated by finding the point of
intersection on the vertical axis on the left side of
the graph labeled, “Static Current”.

For the example system, assume that all of the
processor cores operate at V

= 1.05 V, and that

DD

due to system conditions, the maximum value for

T

is 25°C. Therefore, from these operating

CASE

conditions, Figure 2 shows that the static current
consumed on the VDD voltage domain is 0.20 A.

Total Estimated Core Current (IDD)

To find the total IDD current consumption for
each processor in a specific system, simply add
the total dynamic and static current components
on the V

supply domain, as shown in

DD

Equation 2:

IDD = I

Equation 2. Total IDD Current

DD_DYN

+ I

DD_STATIC

For the example system, calculate the total IDD
current as follows:

I

= I

DD

= 1.86 A + 0.20 A

= 2.06 A

DD_DYN

+ I

DD_STATIC

Example 3. Total IDD Current Estimation

V

Current Consumption

DD_A

Each ADSP-TS201S processor includes an
analog phase lock loop (PLL) and related
circuitry to provide clock signals to the core and
peripheral logic. This circuitry is powered from
an external source that supplies power to the

V

pins of the processor. Since this logic is

DD_A

always active, it must be considered when
calculating the overall power consumed by each
processor core.

There are two different speed grades (500 and
600 MHz) for the ADSP-TS201S processor, as
well as two specific V

voltage requirements

DD_A

for each operating frequency. Therefore there are
two different values for the typical and maximum

I

current for each speed grade, respectively.

DD_A

For 500 MHz speed grade devices, the typical
current (I

DD_A (TYP)

) consumed by the analog
circuitry of each processor is 20 mA. The
maximum I

current (I

DD_A

DD_A (MAX)

) for each

processor at 500 MHz is 50 mA.

I

DD_A (TYP)

Equation 3. Typical 500 MHz I

I

DD_A (MAX)

Equation 4. Maximum 500 MHz I

For 600 MHz speed grade devices, the I

= 20 mA

DD_A

= 50 mA

Current

Current

DD_A

DD_A

current increases slightly due to the increased
operating voltage of the device. The typical
current (I

DD_A (TYP)

) consumed by the analog
circuitry of each processor is 25 mA. The
maximum I

current (I

DD_A

DD_A (MAX)

) for each

processor at 600 MHz is 55 mA.

Estimating Power for ADSP-TS201S TigerSHARC® Processors (EE-170) Page 5 of 16