Analog Devices EE169 Application Notes

Engineer To Engineer Note EE-169

Technical Notes on using Analog Devices' DSP components and development tools

a

Estimating Power For The ADSP-TS101S

Contributed by Greg F. February 24, 2003

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Introduction

This EE note will discuss power consumption
estimation based on characterized measurements
for the ADSP-TS101S digital signal processor.
The motivation for this document is to assist
board designers by providing data as well as
recommendations that will allow the designer to
estimate their power budget for their power
supply and thermal relief designs.

The ADSP-TS101S is an ultra-high-performance,
static superscalar, 32-bit processor from the
TigerSHARC DSP family of Analog Devices.
The DSP operates at a core clock frequency of
300 MHz with the core operating at 1.2V (V
and the I/O operating at 3.3V (V

). The data

DD_IO

DD

)

presented in this EE note is actual measured
power consumption for silicon revision 0.2 of the
ADSP-TS101S.

Power Consumption

Total power consumption has two components,
one due to internal circuitry and one due to the
switching of external output drivers. The
following sections will show how to derive both
of these power numbers.

Devices provides current consumption numbers
for discrete activity levels. System application
code can be mapped to these discrete numbers to
estimate internal power consumption for an
ADSP-TS101S processor for a given application.

Table 1 below shows the current consumption for
the DSP at different levels of activity. From these
internal activity levels (and from an
understanding of the program flow using
profiling or some other means), you can calculate
a weighted-average of power consumption for
each ADSP-TS101S processor in a system.

Parameter Test Conditions IDD (A)

T

=25C, VDD=1.20V, @ 300

I

DDMAX

I

DDTYP

I

DDCTRL

I

DDDMA

I

DDIDLE

I

DDIDLELP

Table 1: Internal Power Vectors

CASE

MHz
T

=25C, VDD=1.20V, @ 300

CASE

MHz
T

=25C, VDD=1.20V, @ 300

CASE

MHz
T

=25C, VDD=1.20V, @ 300

CASE

MHz
T

=25C, VDD=1.20V, @ 300

CASE

MHz
T

=25C, VDD=1.20V, @ 300

CASE

MHz

1.5460

1.5130

0.8380

0.6835

0.6650

0.1723

Internal Power Vector Definitions

Internal Power Consumption Estimation

The internal power consumption (on the VDD
supply) is dependent on the instruction execution
sequence and the data operands involved. Analog

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The following power vector definitions apply to
the internal average power vectors shown above
in Table 1:

• I

Maximum activity is a SIMD quad 16-bit fixed-point

DDMAX

--- V

supply current for maximum activity.

DD

a

multiply and an add in parallel with two quad-word data
fetches. The data fetched and operated on are random. This
vector includes DMA activity as described below in the

I

definition.

DDDMA

• I

activity is a SIMD quad 16-bit fixed-point compute
operation in parallel with two quad-word data fetches. The
data fetched and operated on are random. This vector
includes DMA activity as described below in the I
definition.

•

I

Control activity is continuous decision-making and
predicted branches. The branch prediction is deliberately
set to be incorrect 50% of the time for equal distribution.
This vector includes DMA activity as described below in
the I

• I

activity is a single external port DMA from external to
internal memory, quad-word transfers of 32 words total.
The DMA is chained to itself (in order to run continuously),
and the DMA does not use interrupts. After setup, the core
is not involved, executing the IDLE instruction only.

•

I

activity is the core executing the IDLE instruction only
with no DMA or interrupts.

•

I

Low Power activity is the core executing the IDLE(LP)
instruction only with no DMA or interrupts.

--- V

DDTYP

DDCTRL

DDDMA

DDIDLE

DDIDLELP

--- V

DDDMA

--- V

--- V

supply current for typical activity. Typical

DD

supply current for control activity.

DD

definition.

supply current for DMA activity. DMA

DD

supply current for idle activity. Idle

DD

--- V

supply current for idle low power. Idle

DD

DDDMA

The average current consumption for an ADSP­TS101S for a specific application is calculated
according to the following formula, where “%” is
the percentage of the overall time that the
application spends in that state:

(% Maximum Activity Level x I
(% Typical Activity Level x I
(% Control Activity Level x I
(% DMA Activity Level x I
(% Idle Activity Level x I
+ (% Idle Low Power Activity Level x I

= Total Current for V
= I

DD

Equation 1: Internal Current (IDD) Calculation

DD

DDTYP
DDCTRL

DDDMA

DDIDLE

DDMAX

)

)

)

)

)

DDIDLELP

)

Therefore, the estimated average internal power
consumption (PDD) can be calculated as follows:

P

= IDD x V

DD

DD

Equation 2: Internal Power (PDD) Estimation Calculation

For example, after profiling the application code
the entire system activity is determined as
follows:

- 30% Maximum Activity Level

- 30% Typical Activity Level

- 20% DMA Activity Level

- 20% Idle Activity Level

Example 1: Internal System Activity Level Example

From the percentages of this example, one can
estimate a value for the current consumption of a
single processor as follows:

(30% x 1.5460A)
(30% x 1.5130A)
(20% x 0.6835A)

+ (20% x 0.6650A)

= 1.1874A
= I

Example 2: Internal Current Estimation Example

DD

Therefore, the average internal power estimation
for the processor can be calculated from example
2 above as follows:

P

= 1.1874A x 1.20V

= 1.43W

Example 3: Internal Power Estimation Example

DD

External Power Consumption Estimation

The external power consumption (on V
consumed by the switching of the output pins
and is system dependent. For each unique group
of pins, the magnitude of power consumed
depends on the following:

• The number of output pins that switch
during each cycle, O

• The load capacitance of the output pins, C

• Their voltage swing, V

DD_IO

• The maximum frequency at which the pins
can switch, f

DD_IO

) is

Estimating Power For The ADSP-TS101S (EE-169) Page 2 of 5