Analog Devices ee-138 Application Notes

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Engineer To Engineer Note EE-138

Technical Notes on using Analog Devices’ DSP components and development tools

Phone: (800) ANALOG-D, FAX: [phone], EMAIL: [e-mail], FTP: ftp.analog.com, WEB: www.analog.com/dsp

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ADSP-21161: Recommended Handling of Unused Pins

Introduction

The ADSP-21161 (SHARC) processors contain 225 pins offered in either a 17 mm x 17 mm PBGA or
MBGA package. Many of these pins are only necessary for specific functions, such as the serial ports,
link ports or SPI signals. If your application does not make use of a peripheral feature, the associated
signals (pins) may still require a connection rather than be left floating (unconnected). This EE-Note
suggests recommended methods of handling the pins associated with unused functions. Compared to
previous SHARC DSPs, the ADSP-21161 has some modifications in the internal I/O drivers that the
DSP hardware designer should be aware of, especially if migrating from a previous SHARC-based
design. This information can aid in determining if series terminating, pull-up, or pull-down resisters
would be required when a system is designed.

The EE-Note is broken as follows: A table listing the I/O pins on the ADSP-21161, with a description
of which pins contain internal keeper latches and pull-up/pull-down resisters. This is followed by a
description of the internal keeper latch circuitry and the combined series resistance (internal & added
resistance) of all I/O pins are discussed. Finally, we will examine each peripheral grouping on the
ADSP-21161 and provide general recommendations for handling an unused pin in your system.

TABLE 1: ADSP-21161 I/O PINS

Pin Name Type Notes Other Information

ADDR(23-0)
DATA(47-16)
MS~(3-0)
RD~
WR~
BRST
ACK
SBTS~
CAS~
RAS~
SDWE~
DQM
SDCLK0
SDCLK1
SDCKE
SDA10
IRQ~(2-0)
FLAG(11-0)

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I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
I/O/T
I/O/S
I/S
I/O/T
I/O/T
I/O/T
O/T
I/O/S/T
O/S/T
I/O/T
O/T
I/A
I/O/A

Keeper Latch (Only for ID = 00X)
Keeper Latch (Only for ID = 00X)

20K Pull-Up (Only for ID = 00X)
20K Pull-Up (Only for ID = 00X)
Keeper Latch (Only for ID = 00X)
20K Pull-Up enabled during reset or when ID2-0 = 00X"

TIMEXP
HBR~
HBG~
CS~
REDY
DMAR~(1-0)
DMAG~(1-0)
BR~(6-1)
BMSTR
ID(2-0)
RPBA
PA~
Dxy
SCLKx
FSx
SPICLK
SPIDS~
MISO
MOSI
LxDAT(7-0)
LxCLK
LxACK
EBOOT
LBOOT
BMS~
CLKIN
XTAL
CLK_CFGx
CLKDBL~
CLKOUT
RESET~
TCK
TMS
TDI
TDO
TRST~
EMU~

Notes:

1) When configured as DATA15-0, LKDATxy are I/O/T just like DATA47-16

2) ID=00X indicates the pull-ups and keeper latches are activated for processors hardwired as ID=0 in a single processor system or
ID=1 in a multiprocessor system

O
I/A
I/O
I/A
O(o/d)
I/A
O/T
I/O/S
O
I
I/S
I/O/T
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I
I/O/T
I
O
I
I
O/T
I/A
I
I/S
I/S
O
I/A
O(o/d)

(1)

20K Pull-Up (Only for ID= 00X)
20K Pull-Up (Only for ID = 00X)

20K Pull-Up (Only for ID = 00X)
50K Pull-Up
50K Pull-Up

50K Pull-Up

50K Pull-Up
50K Pull-Up
50K Pull-Down
50K Pull-Down
50K Pull-Down

Keeper Latch (Only for ID = 00X)

20K Pull-Up
20K Pull-Up

20K Pull-Up
50K Pull-Up

ADSP-21161 I/O Pins Include 50 Ohm Internal Resistance

The ADSP-21161 DSP has very fast drivers on all output pins, therefore the edge rates are steep, even at
low-speed clock rates (i.e., slow SCLK or SPICLK rates). To compensate for these faster edge rates
with smaller 0.18 micron CMOS geometries, the ADSP-21161 I/O drivers have been modified to reduce
undesirable transmission line effects when connecting to other devices. Unlike all previous SHARC

processors, the ADSP-21161 contains a total internal series resistance equivalent to 50 ohms on all
I/O drivers (EXCEPT for the CLKIN and XTAL pins). As shown in figure 1, the internal resistance

in the driver is 10 Ohms, therefore the inclusion of an additional 40 ohm series resister results in a total
resistance of 50 Ohms. This 50-Ohm resistance perfectly matches the characteristic impedance of a
transmission line. Notice that the ESD protection feedback path is only found in pins which are bi­directional. Pins listed as "O" (output) only, do not include this signal feedback (ESD protection) path.

EE-138 Page 2

Technical Notes on using Analog Devices’ DSP components and development tools

Phone: (800) ANALOG-D, FAX: [phone], EMAIL: [e-mail], FTP: ftp.analog.com, WEB: www.analog.com/dsp

ESD
Protection
Circuit

Clocks,
control,

Internal Driver

resistance = 10 Ohms

40 Ohms

data,
address

Figure 1: 50 Ohm Series Resistance in ADSP-21161 I/O Pins

The DSP hardware designer needs to be aware of the total 50 Ohm internal combined resistance of the
DSP I/O pins, which then can remove the need for the designer to add external series terminating
resisters in point-to-point DSP interconnections, such as the for link port signals between multiple
SHARC DSPs. Therefore, for traces longer than 6 inches, external series resisters on control, data,
clocks or frame sync pins are no longer required for point-to-point connections between SHARCs in
order to dampen reflections which result from transmission-line effects. If the connection is to another
device other than the ADSP-21161, then source termination is not required on the DSP pin, but a series
resister may still be required for the other device's pin, depending on it's internal driver resistance. Note
that for more complex trace interconnections (such as star configurations), termination techniques will
still need to be employed in order to reduce ringing and reflections.

ADSP-21161 I/O Pins With Keeper Latches
As indicated in Table, 1, keeper latches are used on some ADSP-21161 pins when their corresponding
ID2-0 pins are hardwired to either a 0 or a 1. A Keeper latch is a logic level hold circuit, and basically
consists of a two weak inverter connected back to back. The Figure 2 below shows the basic concept of
a keeper latch:

EE-138 Page 3

Technical Notes on using Analog Devices’ DSP components and development tools

Phone: (800) ANALOG-D, FAX: [phone], EMAIL: [e-mail], FTP: ftp.analog.com, WEB: www.analog.com/dsp