Analog Devices ee-122 Application Notes

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a Engineer To Engineer Note

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EE-122

Technical Notes on using Analog Devices’ DSP components and development tools

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CODING FOR PERFORMANCE ON THE ADSP-219x

To write a DSP algorithm for maximum performance, you must maximize the activity of the ADSP­219x's on-chip resources (such as buses and computation units) within the constraints of the register set
size and the instruction set. Optimal coding for an algorithm uses the DM and PM buses, performs a
useful computation, and performs one or two useful address operations in each cycle. Under these
circumstances the processor is being used at it’s highest efficiency. Realistically, it is impossible to
achieve that efficiency level.

To help improve processor efficiency, many instructions can be executed in parallel with other
instructions. Parallel operation means that more than one operation occurs in a single cycle. Instructions
where multiple operations execute in a single cycle are called multifunction instructions. Multifunction
instructions are critical for optimal performance and should be well understood by every assembly
language programmer. There are two rules of thumb worth noting when using multifunction instructions:

1. The degree of register flexibility varies with each instruction type.

2. The more powerful the instruction, the less flexible it is.

This means that some multifunction instructions are very restrictive with permissible input and output
registers, but those instructions also maximize use of the processor’s resources.

Table 2-1 lists the multifunction operations, listed from most restrictive to least restrictive:

Table 2-1. Multifunction Operations

Instruction
Type

l ALU/MAC with DM&PM dual read

4 Multifunction ALU/MAC with DM/PM

8, 14 ALU/MAC/Shift & any DREG-to-

9, 16 Conditional ALU/MAC/Shift
9A Unconditional Register File ALU/MAC

Description

using DAGs 1&2 post-modify

read or write using DAG post-modify

DREG transfer

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The Type 1 instruction is the least flexible, in terms of register usage, but the most powerful instruction in
the instruction set. The computation operations at the top of this list are limited to a specific set of input and
output registers. The limitation is a direct result of the fixed, 24-bit opcode. For specific descriptions of
multifunction instructions, see the Instruction Set Reference chapter.

What Are the Register Restrictions for Multifunction Instructions?

Computation operations fall into two categories: those that accept any DREG as operands, and those that
only recognize XOP and YOP. When the operand set is limited, it will generally require the X operand
to come from a list of eight XOP registers, and the Y operand to come form a list of three YOP registers.
The available registers are determined by the type of operation performed, as illustrated in Table 2-2.

Table 2-2. Available Registers for Multifunction Instructions

Operation Available XOPs Available YOPs

ALU AX0, AX1 AY0, AY1
AR AF
MR0, MR1,

MR2
SR0, SR1
MAC MX0, MX1 MY0, MY1

MR0, MR1,

SR0, SR1
Shifts SI, SR0, SR1,

AR, AX0, AX1,

MR0, MR1,

AR SR1

MR2,

SR2

AY0, AY1,

MX0, MX1,

MY0, MY1

MR2

the value zero

the value zero

N/A

Table 2-3 lists the 16 DREGs. Notice that AF, SE, and SB are not DREGs.

Table 2-3. Data Registers (DREGs)

DREGs
AX0, AX1, AY0, AY1

MX0, MX1, MY0, MY1
AR, SI
MR2, MR1, MR0
SR2, SR1, SR0

In the ALU, a constant, or third operand type, is often available. These constants are listed in the

Instruction Set Reference chapter and the Visual DSP Programmer’s Quick Reference for the ADSP­219x.

Why Is the “Type 1” Instruction So Powerful?

The Type 1 instruction is the most powerful instruction in the instruction set because it performs a
computation and uses both memory buses simultaneously. This is the instruction at the core of FIR
filters, matrix multiplications, and many other algorithms.

You can combine any of the following operations into a Type 1 instruction:

• A DM read into an X input register (AX0, AX1, MX0, or MX1)

• A PM read into a Y input register (AY0, AY1, MY0, or MY1)

• An ALU or MAC operation (except DIVS, DIVQ, SAT SR/MR, or the bit operations TSTBIT,

SETBIT CLRBIT, and TGLBIT)

Type 1 instructions also have the following restrictions:

• The computations must use XOPs and YOPs

• ALU operations must use AR, MAC operations must use MR

You can also perform a dual-memory read and omit the computation as long as you use the destination
registers listed above.

How Flexible Is an ALU/MAC Multifunction Instruction?

ALU/MAC instructions have four levels of flexibility for using operands. The level of flexibility
depends on the multifunction context, see Table 2-4.

Table 2-4. Operand Flexibility for ALU/MAC Multifunction Instructions

Multifunction Context Operands Results