Analog Devices ee-121 Application Notes

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Engineer To Engineer Note EE-121

Technical Notes on using Analog Devices’ DSP components and development tools

Porting Code From ADSP-218x
To ADSP-219x

Last modified 5/17/01

This tech-note is intended for existing users of the ADSP­218x, who are familiar with the architecture and
instruction set of the ADSP-218x, and plan to upgrade
their design to the ADSP-219x. It is divided into two
main sections - the first describes the enhancements and
differences between the ADSP-218x family of DSPs and
the ADSP-219x in terms of the DSP architecture and the
instruction set, while the second section illustrates the new
ELF assembler and linker formats with the help of an
example.

One of the goals in designing the ADSP-219x has been to
keep its instruction-set and assembly syntax as closely
compatible with the ADSP-21xx family of DSPs as
possible. The exceptions (which have been kept to a
minimum and intended to be as minimally intrusive to the
customer as possible) will be documented in this
Application note. The changes allow for a DSP
architecture that is more C-friendly, resulting in a more
efficient C compiler. It also allows users additional
instructions to improve efficiency of assembly code.
These changes facilitate the increased core processor
operating speeds.

The program sequencer will be able to fetch two data
operands from any two memory blocks in a single cycle.
While having a unified memory map allows for more
flexible memory addressing, it’s important to understand
that on the ADSP-219x, the addresses PM(0x0000) and
DM(0x0000) access the same physical memory location.
The first syntax fetches/writes 24-bit data, while the
second syntax fetches/writes 16-bits of data.

A linker description file (LDF) provided at the end of this
tech-note describes the memory map for the ADSP-2192.

Figure 1. ADSP-2192 memory map

DIFFERENCES IN ARCHITECTURE

1. Unified Memory Space

The ADSP-218x had two separate memory spaces – PM
and DM. The ADSP-219x on the other hand, has a unified
memory space with separate memory blocks to
differentiate between 24 and 16-bit memory. For example,
the first GP member of the ADSP-219x family, ADSP­2192 has dual DSP cores, with core 0 having 16Kx24 and
64Kx16 words of on-chip memory, and core 1 having
16Kx24 and 32Kx16 words of on-chip memory. A
detailed description of the ADSP-2192 memory map can
be obtained from the ADSP-2192 datasheet. Figure 1
shows the memory organization of the ADSP-2192.

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2. 16-bit DAG Registers and Memory Paging

The ADSP-219x has a paged architecture that uses 16-bit
DAG Registers to access 64K pages. But since the address
buses in the ADSP-219x are 24 bits wide, there are also
two new page registers, DMPG1 and DMPG2, which are
used to store the upper 8 bits of the 24-bit address.
DMPG1 works with DAG registers I0-I3 and DMPG2
works with I4-I7, respectively. Page registers can be
initialized as shown in the following example

I2 = 0x3456;

DMPG1 = 0x12; /* Page register can be set to an
absolute page value…*/

DMPG2 = page(data_buffer); /* ..OR could also be
initialized to a buffer */

L2 = 0;

: In terms of syntax, the ADSP-219x assembler

Note
supports a new and more intuitive “C-style” format in
addition to the existing format as shown in the table
below. It is hoped that this new representation will make
code more readable and easier to understand.

Post-modify

Legacy

AX0 = DM(I5,M6);

AX0 = DM(I5 += M6);

AX0 = DM(I5,M6);

New

OR

PM(I1 + -4) = MR2;

OR

PM(-4,I1) = MR2;

Pre-modify

N/A

4. Increased Variety and Types of Jumps and
Function Calls (Relative and Absolute/Long)

AX0 = 0xaaaa;

AR = MR1 - AX0;

DM(I2,M2) = AR;

Note that program execution continues linearly through
memory. Local jumps, loops, and calls within page
boundaries do not affect page registers.

3. Increased variety in DAG Addressing Modes

The ADSP-219x architecture has been enhanced to
provide added flexibility in DAG addressing modes.
There are four new enhanced addressing modes such as

• Pre-modify-without update addressing (in addition to
the existing post-modify with update mode that
existed on the ADSP-218x)

e.g., DM(M1,I0) = AR;

• Pre-modify and post-modify with an 8-bit 2’s­complement immediate modify value instead of an M
register

e.g., AX0 = PM(I5,-4);

• DAG modify with an 8-bit 2’s complement
immediate-modify value

e.g., MODIFY(I7,24);

The ADSP-218x with its 16K words of accessible space
only required a single form of conditional/unconditional
jump/call instruction of the form

[IF COND] CALL <address>;

The address could either be an absolute 14-bit value
provided in the instruction, or could be an indirect address
pointed to by one of the DAG2 Index registers (I4, I5, I6,
or I7).

However, the ADSP-219x has an available addressable
space of 64K words. Hence, it provides a wider variety of
conditional and unconditional jumps and calls, which may
be either delayed or non-delayed. The available options
are:

• 13-bit non-delayed or delayed relative conditional
jump

• Conditional indirect jump or call with address pointed

to by a DAG register. In this case, the upper 8 bits of

the address are stored in a “Jump Page Register”
called IJPG, which is new to the ADSP-219x. Note
that any one of the 8 DAG registers can be used for
jump address.

• 16-bit non-delayed or delayed relative unconditional
jump or call

• 24-bit conditional non-delayed long jump or call

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Jumps, calls and returns can take up to 4 DSP clock cycles
if the branch is taken and no penalty if the branch is not
taken ( as explained in section 5)

Note that the use of delayed branches and jumps will
effectively reduce the above latency by 2. This is because
the two instructions following the jump are also executed.

Address Instruction

L:
M: IF COND JUMP X (DB);
N:
O:
P:
Q:

5. The ADSP-219x Instruction Pipeline

The ADSP-219x has a six-stage Instruction pipeline,
comprising the L(ook-ahead), P(re-fetch), F(etch),
A(ddress), D(ecode), and E(xecute) stages. The pipeline
is completely transparent from a user standpoint.
Incorporated within the instruction pipeline is a two-stage
memory pipeline. The additional depth in the pipeline
means that memory is no longer double pumped leading to
less power consumption. The added depth of the pipeline
is also required to accommodate the increased operating
speed of the processor. For a detailed description of the
ADSP-219x pipeline, please refer to EE-Note EE-123
titled “An Overview of the ADSP-219x Pipeline”.

The added depth to the pipeline enables a programmer to
use delayed branches and function calls. Figure 2 shows
the pipeline structure for a delayed jump that is taken
(Figure 2). Note that the two instructions immediately
following the jump are executed, while the instructions
further down, P and Q (corresponding to the F and P
stages of the pipeline) are flushed. If the jump had not
been taken, normal program execution would have
continued without any lost cycles.

Figure 2

CLOCK CYCLES

Q X Y Z : :

L

P Q X Y Z : :

P

O P nop X Y Z :

F

N O nop nop X Y Z

A

M N O nop nop X Y

D

L M N O nop nop X

E

Figure 3

There is a 4-cycle delay in servicing an interrupt (Fig 4).
On receiving an interrupt request, the DSP completes
execution of the present instruction, flushes the pipeline,
and fetches the first instruction of the interrupt vector.

CLOCK CYCLES

L
P

F
A
D
E

R j j+1 j+2 : : :
Q R j j+1 j+2 : :

P Q nop j j+1 j+2 :
O P nop nop j j+1 j+2
N O nop nop nop j j+1

M N nop nop nop nop j

Interrupt First instruction of
occurs and interrupt vector is
recognized loaded into top of pipeline

where j = first instruction of ISR

Figure 4

6. Base Registers For Circular Buffers (Removes

Restriction on Starting Addresses That Used To Exist
On 218x)

EE-121 Page 3

Technical Notes on using Analog Devices’ DSP components and development tools

Phone: (800) ANALOG-D, FAX: [phone], EMAIL: [e-mail], FTP: ftp.analog.com, WEB: www.analog.com/dsp