Analog Devices CMP04FS, CMP04FP, CMP04BY Datasheet

Quad Low Power,

a

FEATURES
High Gain: 200 V/mV typ
Single or Dual Supply Operation
Input Voltage Range Includes Ground
Low Power Consumption (1.5 mW/Comparator)
Low Input Bias Current: 100 nA max
Low Input Offset Current: 10 nA max
Low Offset Voltage: 1 mV max
Low Output Saturation Voltage: 250 mV @ 4 mA
Logic Output Compatible with TTL, DTL, ECL, MOS and

CMOS
Directly Replaces LM139/239/339 Comparators
Available in Die Form

GENERAL DESCRIPTION

Four precision independent comparators comprise the CMP04.
Performance highlights include a very low offset voltage, low
output saturation voltage and high gain in a single supply de­sign. The input voltage range includes ground for single supply
operation and V– for split supplies. A low power supply current
of 2 mA, which is independent of supply voltage, makes this the
preferred comparator for precision applications requiring mini­mal power consumption. Maximum logic interface flexibility is
offered by the open-collector TTL output.

V+

+INPUT

*

*

SUBSTRATE DIODES

Q1

100mA 3.5mA3.5mA 100mA

Q2

Q3

Q6Q5

Q4

Q7

OUTPUT

Q8

–INPUT

*

Precision Comparator

PIN CONNECTIONS

14-Lead Cerdip

14-Lead Plastic DIP

OUT 2
OUT 1

V+
IN 1–
IN 1+
IN 2–
IN 2+

TYPICAL INTERFACE

3

1/4

CMP04

12

Figure 2a. Driving CMOS

5.0

3

1/4

CMP04

12

Figure 2b. Driving TTL

14-Lead SOIC

1

2

3

4

5

6

7

1

2

CMP04

100kV

10kV

14

13

4

12

11

10

3

9

8

5.0

CMP04

OUT 3
OUT 4
GND
IN 4+
IN 4–
IN 3+
IN 3–

1/4
CD4011

1/4 SN7400

Figure 1. Simplified Schematic (1/4 CMP04)

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

CMP04–SPECIFICATIONS

WARNING!

ESD SENSITIVE DEVICE

ELECTRICAL CHARACTERISTICS

(@ V+ = +5 V, TA = +25ⴗC, unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Units

Input Offset Voltage V
Input Offset Current I
Input Bias Current I
Voltage Gain A
Large-Signal Response Time t

Small-Signal Response Time t

OS

B

r

r

OS

V

R

= 0 Ω, RL = 5.1 kΩ, V

S

IIN(+) – IIN(–), R

= 5.1 kΩ, V

L

IIN(+) or IIN(–) 25 100 nA
R

≥ 15 kΩ, V+ = 15 V

L

VIN = TTL Logic Swing, V
VRL = 5 V, R

= 5.1 kΩ 300 ns

L

O

2

= 1.4 V

REF

VIN = 100 mV Step3, 5 mV Overdrive
V

= 5 V, R

RL

= 5.1 kΩ 1.3 µs

L

1

= 1.4 V 2 10 nA

O

80 200 V/mV

= 1.4 V

3

0.4 1 mV

Input Voltage Range CMVR (Note 4) 0 V+ –1.5 V
Common-Mode Rejection Ratio CMRR (Notes 2, 5) 80 100 dB
Power Supply Rejection Ratio PSRR V+ = +5 V to +18 V
Saturation Voltage V
Output Sink Current I
Output Leakage Current I

OL

SINK

LEAK

V

(–) ≥ 1 V, V

IN

V

(–) ≥ 1 V, V

IN

V

(+) ≥ 1 V, V

IN

2

(+) = 0, I

IN

(+) = 0, V

IN

(–) = 0, VO = 30 V 0.1 100 nA

IN

≤ 4 mA 250 400 mV

SINK

≤ 1.5 V 6 16 mA

O

80 100 dB

Supply Current I+ RL = ∞, All Comps V+ = 30 V 0.8 2.0 mA

NOTES

1

At output switch point, VO = 1.4 V, R

2

Guaranteed by design.

3

Sample tested.

4

The input common-mode voltage or input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode voltage range
is V+ –1.5 V, but either or both inputs can go to +30 V without damage.

5

R

≥ 15 kΩ, V+ = 15 V, V

L

Specifications subject to change without notice.

= 1.5 V to 13.5 V.

CM

= 0 Ω with V+ from 5 V; and over the full input common-mode range (0 V to V+ –1.5 V).

S

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .36 V or ±18 V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . 36 V dc

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +36 V

Operating Temperature Range

CMP04BY . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

CMP04FP, FS . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature (T

) . . . . . . . . . . . . . –65°C to +150°C

J

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

(P Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C

Input Current (V

< –3.0 V) . . . . . . . . . . . . . . . . . . . 50 mA

IN

Output Short-Circuit to GND . . . . . . . . . . . . . . . .Continuous

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . .+300°C

1

Package Type ␪

14-Lead Hermetic DIP (Y) 94 10 °C/W
14-Lead Plastic DIP (P) 83 39 °C/W
14-Lead SOIC 120 36 °C/W

NOTES

1

Absolute maximum ratings apply to both DICE and packaged parts, unless

otherwise noted. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

θJA is specified for worst case mounting conditions, i.e., θ

in socket for cerdip and plastic DIP packages; θ

to printed circuit board for SO package.

ORDERING GUIDE

TA = +25ⴗC Temperature Package Package

Model V

OS

Ranges Descriptions Options

CMP04BY/883C 1 mV –55°C to +125°C 14-Lead Cerdip Q-14
CMP04FP 1 mV –40°C to +85°C 14-Lead Plastic DIP N-14
CMP04FS 1 mV –40°C to +85°C 14-Lead SOIC R-14/SO-14

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the CMP04 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

2

JA

␪

JC

is specified for device

JA

is specified for device soldered

JA

Units

–2–

REV. C

CMP04

(@ V+ = +5 V, –55ⴗC ≤ TA ≤ +125ⴗC for CMP04BY, –40ⴗC ≤ TA ≤ +85ⴗC for

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Units

Input Offset Voltage V

Input Offset Current I

Input Bias Current I

Voltage Gain A

Large-Signal Response Time t

Small-Signal Response Time t

Input Voltage Range CMVR (Note 5) 0 V+ –1.5 V

Common-Mode Rejection Ratio CMRR (Notes 1, 3) 60 100 dB

Power Supply Rejection Ratio PSRR V+ = +5 V to +18 V 80 100 dB

Saturation Voltage V

Output Sink Current I

Output Leakage Current I

Supply Current I+ RL = ∞, All Comps 1.2 3.0 mA

NOTES

1

R

≥ 15 kΩ, V+ = 15 V, V

L

2

At output switch point, VO = 1.4 V, R

3

Guaranteed by design.

4

Sample tested.

5

The input common-mode voltage or input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode
voltage range is V+ –1.5 V, but either or both inputs can go to +30 V without damage.

Specifications subject to change without notice.

= 1.5 V to 13.5 V.

CM

OS

OS

B

V

r

r

OL

SINK

LEAK

= 0 Ω with V+ from 5 V; and over the full input common-mode range (0 V to V+ –1.5 V).

S

CMP04FP/FS, unless otherwise noted)

CMP04B/F

R

= 0 Ω, RL = 5.1 kΩ 12 mV

S

VO = 1.4 V

2

IIN(+) – IIN(–) 4 20 nA

= 5.1 kΩ 420nA

R

L

VO = 1.4 V 4 20 nA

IIN(+) or IIN(–) 40 200 nA

R

≥ 15 kΩ, V+ = 15 V

L

VIN = TTL Logic Swing 300 ns
V

REF

VRL = 5 V, R

= 1.4 V

4

= 5.1 kΩ 300 ns

L

VIN = 100 mV Step

3

4

70 125 V/mV

5 mV Overdrive 1.3 µs

VRL = 5 V, R

V

(–) ≥ 1 V, V

IN

I

≤ 4 mA 250 700 mV

SINK

V

(–) ≥ 1 V, 5 16 mA

IN

VIN(+) = 0, V

V

(+) ≥ 1 V, 0.1 200 nA

IN

= 5.1 kΩ 1.3 µs

L

(+) = 0, 250 700 mV

IN

≤ 1.5 V 5 16 mA

O

VIN(–) = 0, VO = 30 V 0.1 200 nA

V+ = 30 V 1.2 3.0 mA

1

12 mV

300 ns

1.3 µs

REV. C

–18V

+18V

ONE EACH

PER BOARD

100kV

3.6kV

3.6kV

ZENER

5.8V TO 6.2V
1 WATT

TO ADJACENT SOCKETS

3.6kV

13 12 11

4

CMP04

3

2345617

3.6kV

470kV

+30V

Figure 3. Burn-In Circuit

–3–

–18V

914 8

10

1

2

+18V

MIL-STD-883, METHOD 1015, CONDITION B

CMP04

DICE CHARACTERISTICS

DIE SIZE 0.058 × 0.055 inch, 3190 sq. mils

(1.47

×

1.40 mm, 2.058 sq. mm)

WAFER TEST LIMITS

(@ V+ = +5 V, TA = +25ⴗC, unless otherwise noted)

CMP04N CMP04G

Parameter Symbol Conditions Limit Limit Units

Input Offset Voltage V

Input Offset Current I

OS

OS

R

= 0 Ω, RL = 5.1 kΩ

S

VO = 1.4 V

1

IIN(+) – IIN(–)

= 5.1 kΩ

R

L

1 2 mV max

VO = 1.4 V 10 25 nA max

Input Bias Current I

Voltage Gain A

B

V

IIN(+) or IIN(–)

R

≥ 15 kΩ, V+ = 15 V

L

1

3

100 100 nA max

80 50 V/mV min

Input Voltage Range CMVR (Notes 2, 3) V+ –1.5 V+ –1.5 V max

Common-Mode Rejection Ratio CMRR (Note 4) 80 80 dB min

Power Supply Rejection Ratio PSRR V+ = +5 V to +18 V 80 80 dB min

Saturation Voltage V

Output Sink Current I

Output Leakage Current I

OL

SINK

LEAK

V

(–) ≥ 1 V, V

IN

I

≤ 4 mA 400 400 mV max

SINK

V

(–) ≥ 1 V,

IN

VIN(+) = 0, V

V

(+) ≥ 1 V,

IN

(+) = 0,

IN

≤ 1.5 V 6 6 mA min

O

VIN(–) = 0, VO = 30 V 100 100 nA max

Supply Current I+ RL = ∞, All Comps

V+ = 30 V 2 2 mA max

NOTES
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

TYPICAL ELECTRICAL CHARACTERISTICS

(@ V+ = +5 V, unless otherwise noted)

CMP04N CMP04G

Parameter Symbol Conditions Typical Typical Units

Large-Signal Response Time t

Small-Signal Response Time t

r

r

VIN = TTL Logic Swing
V

REF

VRL = 5 V, R

VIN = 100 mV Step

= 1.4 V

5

= 5.1 kΩ 600 600 ns

L

5

5 mV Overdrive
VRL = 5 V, R

NOTES

1

At output switch point, VO = 1.4 V, R
full input common-mode range (0 V to V+ –1.5 V).

2

The input common-mode voltage or either input signal voltage should not be allowed
to go negative by more than 0.3 V. The upper end of the common-mode voltage
range is V+ –1.5 V, but either or both inputs can go to +30 V without damage.

= 0 Ω with V+ from 5 V; and over the

S

= 5.1 kΩ 1.3 1.3 µs

L

3

Guaranteed by design.

4

R

≥ 15 kΩ. V

L

5

Sample tested.

Specifications subject to change without notice.

= 1.5 V to 13.5 V.

CM

–4–

.

REV. C

Typical Performance Characteristics

TEMPERATURE – 8C

I

OS

– INPUT OFFSET CURRENT – nA

3.0

–40 0

2.0

1.0

0

–1.0

–2.0

–3.0

–20 20 40 60 80 100 120 140

–60

CMP04

+0.3

+0.2

+0.1

0

–0.1

– OFFSET VOLTAGE – mV

OS

–0.2

V

–0.3

–60

–20 20 40 60 80 100 120 140

–40 0

TEMPERATURE – 8C

Figure 4. Offset Voltage vs.
Temperature

160
150
140
130
120
110
100

90

– VOLTAGE GAIN – V/mV

V

80

A

70
60

–60

–20 20 40 60 80 100 120 140

–40 0

TEMPERATURE – 8C

Figure 7. Voltage Gain vs.
Temperature

80

60

= 08C

T

A

40

TA = +1258 C

20

– INPUT BIAS CURRENT – nA

B

I

0

10 20 25 30 35 400

515

V+ – SUPPLY VOLTAGE – V

T

= –558 C

A

TA = +258 C/708C

DC

Figure 5. Input Bias Current vs. V+
and Temperature

1.1
T

= –558 C

= 08C

T

0.9

0.7

0.5

SUPPLY CURRENT – mA

0.3

0.1

A

515

A

T

= +258 C

A

T

T

= +1258 C

A

10 20 25 30 35 400
SUPPLY VOLTAGE – V

= +708 C

A

DC

Figure 8. Supply Current vs. Supply
Voltage

Figure 6. Input Offset Current vs.
Temperature

10

DC

1.0

0.1

0.01

– SATURATION VOLTAGE – V

OL

V

0.001

OUT OF SATURATION

= +1258 C

T

A

= –558 C

T

A

= +258 C

T

A

0.1 1.0 10 1000.01

IO – OUTPUT SINK CURRENT – mA

Figure 9. Output Voltage vs. Out­put Current and Temperature

REV. C

Figure 10. Response Time for Various Input
Overdrives—Negative Transition

6.0

5.0

4.0
20mV

3.0

– Volts

O

V

2.0
100mV

OUTPUT VOLTAGE

1.0

0
0

–50

– mV

IN

V

–100

INPUT VOLTAGE

INPUT OVERDRIVE =

5.0mV

V

IN

0.5 1.0 1.5 2.00
TIME – ms

+5V

DC

5.1kV
V

OUT

TA = +258 C

6.0
INPUT OVERDRIVE =
100mV

5.0

4.0

3.0

– Volts

O

V

2.0

OUTPUT VOLTAGE

1.0
0
0

–50

– mV

IN

V

–100

INPUT VOLTAGE

0.5 1.0 1.5 2.00
TIME – ms

20mV

V

IN

TA = +258 C

5mV

+5V

DC

Figure 11. Response Time for Various Input
Overdrives—Positive Transition

–5–

5.1kV
V

OUT

CMP04

TYPICAL APPLICATIONS

V+

1/4

CMP04

OR LOGIC WITHOUT

*

PULLUP RESISTOR

6.2kV

Figure 12. Output Strobing

2R

+V

HI

REF

+V

+V

LOW

REF

S

R

S

IN

2R

S

Figure 13. Limit Comparator

*

CMP04

CMP04

1/4

1/4

V

O

STROBE
INPUT

V+

+V

IN

V+

1MV

1MV

1/4

CMP04

1MV

3kV

V

O

Figure 15. Inverting Comparator with Hysteresis

V+

100kV

75pF

1/4

CMP04

100kV

V+

100kV

100kV

4.3kV

V+

0

V

f = 186kHz

O

Figure 16. Square Wave Oscillator

V+

+V

REF

+V

IN

10kV

1/4

CMP04

10MV

3kV

V

O

Figure 14. Noninverting Comparator with Hysteresis

100kV

V

IN1

100kV

V

IN2

1N914

1/4

CMP04

V+

5.1kV

V

O

Figure 17. Comparing Input Voltages of Opposite Polarity

–6–

REV. C

CMP04

1/4

CMP04

V+

V+
0

t0t1t

2

15kV

D2

1N914

80pF

R2

100kV

D1

1N914

R1

1MV

1MV

1MV

1MV

V+

FOR LARGE RATIOS OF R1/R2,
D1 CAN BE OMITTED.

V+

0

t

0

100pF

+V

IN

1N914

1MV

1MV

1MV

Figure 18. One-Shot Multivibrator

100kV

V+

0

"0" "1"

A

100kV

B

100kV

C

Figure 19. AND Gate

V+

1/4

CMP04

1N914

V+

1kV

0.01mF

39kV

+0.375V

1kV

10kV

1/4

CMP04

PW1ms

t0t

V

O

1 = A • B • C

V+
0

1

Figure 20. Pulse Generator

V+

1kV

200kV

+0.075V

1kV

1/4

CMP04

3kV

f

1 = A + B + C

3kV

100kV

"0" "1"

A

100kV

B

100kV

C

f

V+

0

Figure 21. OR Gate

V+

1MV

100kV

1MV

1/4

CMP04

100pF

62kV

1S

+4V

0

100kV

+V

IN

10MV

560kV

CMP04

240kV

1/4

10MV

15kV

V

O

t0t

T = 0.3ms

V+

T

0

1

Figure 22. One-Shot Multivibrator with Input Lockout

REV. C

–7–

CMP04

TYPICAL APPLICATIONS

V+

V+

V3

V2

V

C1

V1

0

t

0

V+

0

INPUT GATING SIGNAL

t1t2t

t

0

V+

V+

3.0kV

3.0kV

3.0kV

V+

0

t

t

0

t0t

t0t

3

C3107a–0–7/98

2

1

V

O3

V+

0

V

O2

V+

0

V

O1

10kV

t

4

3

10kV

+V

t

IN

4

1/4

CMP04

15kV

C1

0.001mF

200kV

10kV

V3

51kV

10kV

V2

51kV

10kV

V1

51kV

10MV

1/4

CMP04

10MV

1/4

CMP04

10MV

1/4

CMP04

Figure 23. Time Delay Generator

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

0.005 (0.13) MIN

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

14

1

0.785 (19.94) MAX

0.023 (0.58)

0.014 (0.36)

14-Lead Cerdip

0.098 (2.49) MAX

PIN 1

0.100
(2.54)

BSC

(Q-14)

8

0.310 (7.87)

0.220 (5.59)

7

0.060 (1.52)

0.015 (0.38)

0.070 (1.78)

0.030 (0.76)

0.150
(3.81)
MIN

SEATING
PLANE

0.320 (8.13)

0.290 (7.37)

15°

0°

0.1574 (4.00)

0.1497 (3.80)

0.0098 (0.25)

0.0040 (0.10)

0.015 (0.38)

0.008 (0.20)

14-Lead SOIC

0.3444 (8.75)

0.3367 (8.55)

14 8

PIN 1

0.0688 (1.75)

0.0532 (1.35)

(R-14)

0.2440 (6.20)

71

0.2284 (5.80)

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.93)

14-Lead Plastic DIP

(N-14)

0.795 (20.19)

0.725 (18.42)

14

17

PIN 1

0.022 (0.558)

0.014 (0.356)

0.0196 (0.50)

0.0099 (0.25)

(2.54)

x 45°

0.100
BSC

8

0.070 (1.77)

0.045 (1.15)

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.130
(3.30)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

PRINTED IN U.S.A.

SEATING

PLANE

0.0500
(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

–8–

0.0099 (0.25)

0.0075 (0.19)

8°
0°

0.0500 (1.27)

0.0160 (0.41)

REV. C