Analog Devices AN665 Application Notes

AN-665

OUTPUT

MUX

AIN1

AIN2

AIN3

AIN4

AD7708/AD7718

AGND

AIN9/REFIN2(+)

AIN10/REFIN2(–)

AIN5

AIN6

AIN7

AIN8

AINCOM

V

BIAS

= 2.5V

AD7708 16-BIT

ADC

AD7718 24-BIT ADC

REFIN(+)

REFIN(–)

SIGNAL

CONDITIONING

BUF

PGA

ADC

REF

AVDD

DGND

DVDD

APPLICATION NOTE

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Channel Switching Using - ADCs

By Mary McCarthy

INTRODUCTION

This application note refers to the AD7708 and AD7718. Data
sheets specify the update rate for - ADCs. The update
rate is the rate at which conversions are performed when
a single channel is selected and the ADC is continuously
converting. The update rate that can be used depends on
the application in which the ADC is being used. The peak­to-peak resolution of t he device degrades as t he update
rate is increased. In a multichannel application such as a
data acquisition system, conversions from several chan­nels are read, i.e., each channel is selected in turn and
a conversion is performed for that channel. In such an
application, the rate at which conversions are performed
is different compared to a single-channel system. This
application note describes the switching procedure used
by these parts.

MULTICHANNEL SYSTEM

Figure 1 shows the AD7708 or AD7718 being used in a
data acquisition system. Each channel is connected to a
sensor. With its PGA and programmable update rate, the
AD7708/AD7718 can be used to convert signals of different
amplitudes and at different update rates. The AD7708 and
AD7718 can be used with chopping enabled or disabled.
Chopping leads to low offset and low offset drift. With
chopping disabled, the offset error and offset error drift
are a little higher, but a higher conversion rate can be
obtained from the device.

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Figure 1. Data Acquisition System Using the AD7708/AD7718

AN-665

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AN-665

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Chopping Disabled

When a channel is selected, the rst conversion is available
after a period (24  SF/fS), where fS = sampling frequency
= 32.768 kHz, and SF is the word loaded into the lter reg­ister on-board the device (3 – 255). The second conversion
is available after a further (8  SF/fS) seconds. RDY will go
low each time a conversion is available.

These ADCs use a Sinc lter, which has a settling time of
(24  SF/fS) in unchopped mode. Each time a channel is
selected, the lter requires this settling time to calculate
the rst digital word. Subsequent conversions, such as the
second conversion, occur at a rate of (fS/(8  SF)). Each
time that a different channel is selected, the lter must
settle as the analog input on the new channel differs from
the analog input on the previous channel. After switching
channels, RDY will stay high until a valid conversion is
available.

Chopping Enabled

When chopping is used, the conversion rate is reduced
for a given SF word. With chopping, the analog inputs are
repeatedly switched within the ADC. Consecutive samples
are then averaged by 2. This switching and averaging
removes the offset error of the ADC. When switching from
one channel to another, the settling time required by the
Sinc lter to calculate the digital word relevant to the analog
input voltage on the selected chan nel is (48  SF/fS)
with chopping enabled. As in unchopped mode, RDY
remains high until a valid conversion is available. Since RDY
remains high until a valid conversion is available, the DSP/
microcontroller does not have to count RDY pulses after
switching channels to nd the valid conversion. The RDY
signal can be used as an interrupt to a DSP/microcontroller,
the DSP/microcontroller not communicating with the ADC
until RDY goes low. Subsequent conversions on this chan-
nel will occur at a rate of (24  SF/fS).

ZERO LATENCY

When using the AD7708 or AD7718, a longer time is
required to calculate the rst conversion when a chan­nel is selected. Subsequent conversions on this channel
occur at a higher rate. With a zero-latency ADC, available
from other manufacturers, the complete lter settling time
elapses between all conversions. Therefore, zero latency
is achieved by reducing the conversion rate of the ADC.
Analog Devices’ ADCs are designed to operate at the high­est speed possible for a given accuracy.

Figure 2 (i) describes the operation of the AD7708/AD7718
when switching between channels in unchopped mode.
Using a single channel, conversions are obtained at the
high rate (illustrated by the dashed line). When the analog
input channel is switched, the ADC requires a longer
interval of time to perform a conversion (three times longer
in unchopped mode). Figure 2 (ii) shows the zero-latency
system. In such a system, the digital lter requires the

complete settling time at all times. This results in an ADC
with a much slower update rate.

The AD7708 and AD7708 also have a single conversion
mode in which the device performs a conversion and then
goes into idle mode. In idle mode, the ADC’s modulator
and lter are held in a reset state. The user can begin a
conversion by writing to the MD2, MD1, and MD0 bits in
the mode register. When these bits are set appropriately,
the modulator and lter are released from the reset state
and begin conversion. Because the lter must settle, a con­version is completed after a period (24  SF/fS). The ADC
places this valid conversion into the data register, takes
RDY low, and then returns to idle mode. In this mode, the
AD7708/AD7718 operates as a zero-latency ADC because
the settling time is required to perform each conversion.

RDY goes low only when a valid conversion is available.
Therefore, from the DSP/microcontroller’s point of view,
all modes of conversion use a single conversion cycle in
which the extra conversion cycles required to generate
a valid digital word after switching channels, or in single
conversion mode, are hidden from the microprocessor.
The microprocessor does not care about the length of
time for which RDY is high. It knows that it will read a valid

word from the ADC each time RDY goes low.

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