Analog Devices AN663 Application Notes

AN-663

FOR UNIPOLAR RANGES:
DATA = ((ADC RESULT – R  ADC ZS CAL. REG.) XADC FS REG./
200000h – R  CH. ZS CAL. REG.) XCH. FS CAL. REG./200000h

FOR BIPOLAR RANGES:
DATA = ((ADC RESULT – R  ADC ZS CAL. REG.) XADC FS REG./
400000h + 800000h – R  CH. ZS CAL. REG.) XCH. FS CAL. REG./200000h

WHERE THE ADC RESULT IS IN THE RANGE OF 0 TO FFFFFh.
AND R = 1 ON 2.5 V AND 1.25 V RANGES AND R = 2 ON THE 0.625 V.

CONVERSION

DATA

AVAILABLE

SUBTRACT

ADC OFFSET

REGISTER

MULTIPLY BY

ADC GAIN
REGISTER

SUBTRACT

PER CHANNEL

OFFSET REGISTER

MULTIPLY BY

PER CHANNEL

GAIN REGISTER

APPLY CLAMP

IF SELECTED

WRITE TO

DATA REGISTER

FROM FILTER

APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: [phone] • Fax: [phone] • www.analog.com

AD7732/AD7734/AD7738/AD7739 Calibration Registers

By Tom Meany

This application note concentrates on the AD7739 but is
also applicable to the AD7732, AD7734, and AD7738.The
purpose of this application note is to explore the calibration
registers in more detail than is found on the data sheets.

INTRODUCTION

The AD7739 features two sets of calibration registers. The
main function of these registers is to store the offset and gain
coefcients for the various calibration modes. However,
since all nine sets of registers can be read to and written
from over the serial interface, these registers are available
to manipulate raw ADC conversion results.

The rst set of registers is a 24-bit offset (ADC offset)
register and 24-bit gain (ADC gain) register, which affect
all channels. The second set includes a per channel 24-bit
offset register and a 24-bit per channel gain register, which
affect a specic channel only.

The effect of the calibration registers is independent of
conversion time, but does depend on the range. All calibra­tion registers on the AD7732, AD7734, AD7738, and AD7739
can be read to or written from over the serial interface.
However, a write to the registers will be ignored if the ADC
is converting or calibrating when the write takes place.
This avoids corrupting the conversion result. Therefore,
you must set the ADC into its sync mode by writing 000
to the mode bits before writing to any of the calibration
registers.

Figure 1. Flow Chart for Calibration Register Contents

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ADC OFFSET COEFFICIENT

The shared ADC offset register is a 24-bit register used in
the calculation of all ADC results on any channel. Although
this register may be read from and written to, this register
should be modied only by self-ZS calibrations. The per
channel offset registers were provided to allow users to
manipulate the output code.

The format of the register is offset binary so that 0x000,000
is negative full-scale, 0xFFF,FFF is positive full-scale, and
0x800000 is 0. The default value of the register is 0x800000,
which results in an adjustment of zero in the output code.
The maximum absolute change is ±224.

If the mode is set to 000 and then 0x70BDC0 (minus one
million in decimal) is written to the ADC ZS register, the
effect on the output code for a 0 V input is as follows:

Table I. 24-Bit Output Codes for VIN = 0,

ADC Coefcient = 0x70BDC0

as Measured on Applications Board

Output Code
VIN Range Increase

0.0 ±2.5 2,000,000

0.0 ±1.25 2,000,000

0.0 ±0.625 4,000,000

0.0 0/2.5 4,000,000

0.0 0/1.25 4,000,000

0.0 0/0.625 8,000,000

ADC GAIN COEFFICIENT

The shared ADC gain register is a 24-bit register and is
used in calculating all ADC results on any channel. Although
this register may be read from and written to, this register
should be modied by only self-FS calibrations. The per
channel gain registers were provided to allow users to
manipulate the output code.

Table II. Bit Map of the ADC Gain Register

MSB MSB-1 MSB-2 MSB-3 MSB-4 MSB-5 ....... LSB

1 1/2 1/4 1/8 1/16 1/32 1/2

The range of the adjustment in gain is therefore from 0 to 2.

The default value of the register is 0x800000, which cor­responds to a gain of 1.

23

If the mode is set to 000 and then 0x900,000 is written to
the ADC FS register, the effect on the output code for a

0.5 V input is as follows:

Table III. Change in Output Code Due to

Change in ADC Gain Coefcient

Output with Output with
ADC Gain ADC Gain
Coefcient Coefcient
VIN Range = 0x800000 = 0x900000

0.5 ±2.5 1,695,000 1,906,794

0.5 ±1.25 3,386,431 3,808,826

0.5 ±0.625 6,772,522 7,617,452

0.5 0/2.5 3,389,465 3,812,643

0.5 0/1.25 6,771,653 7,617,749

0.5 0/0.625 13,544,211 15,233,216

INTRODUCTION TO THE PER CHANNEL OFFSET AND GAIN COEFFICIENTS

On each of the generics there are eight sets of per channel
calibration registers, each comprised of a 24-bit offset and
a 24-bit gain register. These registers are assigned to the
physical input channels as shown in Table IV.

Table IV. Assignment of Physical Pins to

Per Channel Calibration Registers

Channel AD7738/AD7739 AD7734 AD7732

000 [AIN0, AIN1],
[AIN0, Common] AIN0 [AIN0+, AIN0–]
001 [AIN2, AIN3],
[AIN1, Common] AIN1
010 [AIN4, AIN5],
[AIN2, Common] AIN2 [AIN1+, AIN1–]
011 [AIN6, AIN7],
[AIN3, Common] AIN3
100 [AIN0, AIN1],
[AIN4, Common] AIN0 [AIN0+, AIN0–]
101 [AIN2, AIN3],
[AIN5, Common] AIN1
110 [AIN4, AIN5],
[AIN6, Common] AIN2 [AIN0+, AIN0–]
111 [AIN6, AIN7],
[AIN7, Common] AIN3

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