Analog Devices AN663 Application Notes

AN-663
FOR UNIPOLAR RANGES: DATA = ((ADC RESULT – R ADC ZS CAL. REG.) XADC FS REG./ 200000h – R CH. ZS CAL. REG.) XCH. FS CAL. REG./200000h
FOR BIPOLAR RANGES: DATA = ((ADC RESULT – R ADC ZS CAL. REG.) XADC FS REG./ 400000h + 800000h – R CH. ZS CAL. REG.) XCH. FS CAL. REG./200000h
WHERE THE ADC RESULT IS IN THE RANGE OF 0 TO FFFFFh. AND R = 1 ON 2.5 V AND 1.25 V RANGES AND R = 2 ON THE 0.625 V.
CONVERSION
DATA
AVAILABLE
SUBTRACT
ADC OFFSET
REGISTER
MULTIPLY BY
ADC GAIN REGISTER
SUBTRACT
PER CHANNEL
OFFSET REGISTER
MULTIPLY BY
PER CHANNEL
GAIN REGISTER
APPLY CLAMP
IF SELECTED
WRITE TO
DATA REGISTER
FROM FILTER
APPLICATION NOTE
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AD7732/AD7734/AD7738/AD7739 Calibration Registers
By Tom Meany
This application note concentrates on the AD7739 but is also applicable to the AD7732, AD7734, and AD7738.The purpose of this application note is to explore the calibration registers in more detail than is found on the data sheets.

INTRODUCTION

The rst set of registers is a 24-bit offset (ADC offset) register and 24-bit gain (ADC gain) register, which affect all channels. The second set includes a per channel 24-bit offset register and a 24-bit per channel gain register, which affect a specic channel only.
The effect of the calibration registers is independent of conversion time, but does depend on the range. All calibra­tion registers on the AD7732, AD7734, AD7738, and AD7739 can be read to or written from over the serial interface. However, a write to the registers will be ignored if the ADC is converting or calibrating when the write takes place. This avoids corrupting the conversion result. Therefore, you must set the ADC into its sync mode by writing 000 to the mode bits before writing to any of the calibration registers.
Figure 1. Flow Chart for Calibration Register Contents
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ADC OFFSET COEFFICIENT

The format of the register is offset binary so that 0x000,000 is negative full-scale, 0xFFF,FFF is positive full-scale, and 0x800000 is 0. The default value of the register is 0x800000, which results in an adjustment of zero in the output code. The maximum absolute change is ±224.
If the mode is set to 000 and then 0x70BDC0 (minus one million in decimal) is written to the ADC ZS register, the effect on the output code for a 0 V input is as follows:
Table I. 24-Bit Output Codes for VIN = 0,
ADC Coefcient = 0x70BDC0
as Measured on Applications Board
Output Code VIN Range Increase
0.0 ±2.5 2,000,000
0.0 ±1.25 2,000,000
0.0 ±0.625 4,000,000
0.0 0/2.5 4,000,000
0.0 0/1.25 4,000,000
0.0 0/0.625 8,000,000

ADC GAIN COEFFICIENT

The shared ADC gain register is a 24-bit register and is used in calculating all ADC results on any channel. Although this register may be read from and written to, this register should be modied by only self-FS calibrations. The per channel gain registers were provided to allow users to manipulate the output code.
Table II. Bit Map of the ADC Gain Register
MSB MSB-1 MSB-2 MSB-3 MSB-4 MSB-5 ....... LSB
1 1/2 1/4 1/8 1/16 1/32 1/2
The range of the adjustment in gain is therefore from 0 to 2.
The default value of the register is 0x800000, which cor­responds to a gain of 1.
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If the mode is set to 000 and then 0x900,000 is written to the ADC FS register, the effect on the output code for a
0.5 V input is as follows:
Table III. Change in Output Code Due to
Change in ADC Gain Coefcient
Output with Output with ADC Gain ADC Gain Coefcient Coefcient VIN Range = 0x800000 = 0x900000
0.5 ±2.5 1,695,000 1,906,794
0.5 ±1.25 3,386,431 3,808,826
0.5 ±0.625 6,772,522 7,617,452
0.5 0/2.5 3,389,465 3,812,643
0.5 0/1.25 6,771,653 7,617,749
0.5 0/0.625 13,544,211 15,233,216

INTRODUCTION TO THE PER CHANNEL OFFSET AND GAIN COEFFICIENTS

On each of the generics there are eight sets of per channel calibration registers, each comprised of a 24-bit offset and a 24-bit gain register. These registers are assigned to the physical input channels as shown in Table IV.
Table IV. Assignment of Physical Pins to
Per Channel Calibration Registers
Channel AD7738/AD7739 AD7734 AD7732
000 [AIN0, AIN1], [AIN0, Common] AIN0 [AIN0+, AIN0–] 001 [AIN2, AIN3], [AIN1, Common] AIN1 010 [AIN4, AIN5], [AIN2, Common] AIN2 [AIN1+, AIN1–] 011 [AIN6, AIN7], [AIN3, Common] AIN3 100 [AIN0, AIN1], [AIN4, Common] AIN0 [AIN0+, AIN0–] 101 [AIN2, AIN3], [AIN5, Common] AIN1 110 [AIN4, AIN5], [AIN6, Common] AIN2 [AIN0+, AIN0–] 111 [AIN6, AIN7], [AIN7, Common] AIN3
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It can be seen from this table that most channel combina­tions have two available register sets. For example, AIN0 on the AD7738 uses channel register set 0 when converting on channel 000, but if the conversion is done on channel 100, then it uses register set 100.
On all four generics including the AD7732, AD7734, system zero-scale and system full-scale calibrations can be used to remove all offset and gain errors in the signal chain includ­ing offset and gain due to the on-chip resistor matching on the AD7732/AD7734. A system ZS calibration changes the per channel offset coefcient for a specic channel, and a system FS calibration changes the gain coefcient for the selected channel. If the system ZS and the system FS calibrations are performed in the factory and stored in external memory, they can be downloaded to the ADC after power-up.

PER CHANNEL OFFSET COEFFICIENT

With the per channel gain register at its default value, increasing the offset register contents by 1 increases or decreases the output of all future conversions on that channel, depending on the sign bit.
Table V. Bit Map of Per Channel Offset Register
MSB MSB-1 Bits MSB-2 to LSB
Sign 0 Magnitude 0 to 2,097,151
The MSB of the per channel offset coefcient is the sign bit. If the sign bit is 1, the offset coefcient is negative and it causes the ADC output code to increase. If the MSB is 0, then the offset coefcient is positive and the output code decreases. Bit 23 of the per channel offset register must be 0 and the remaining 22 bits are magnitude bits.
As an illustration, if 0x8F4240, sign = 1, magnitude = 1 million decimal is written to the channel 0 ZS calibration register, the resulting change in all Channel 0 conversions will be as shown in Table VI.
Table VI. 24-Bit Output Codes Change
Per Channel Offset Register = 0x8F4240
Output Code VIN Range Increase
0.0 ±2.5 1,000,000
0.0 ±1.25 1,000,000
0.0 ±0.625 2,000,000
0.0 0/2.5 2,000,000
0.0 0/1.25 2,000,000
0.0 0/0.625 4,000,000
Therefore for the ±2.5 V and ±1.25 V ranges, an LSB change in the per channel offset register corresponds to an LSB change in the ADC output code. For the ±0.625 V, 0/2.5 V, and 0/1.25 V ranges, a 1 LSB change in the cali­bration register gives a 2 LSB change in the output code; nally for the 0/0.625 V range, the change is 4 LSB.

PER CHANNEL GAIN COEFFICIENT

The default gain coefcient is 0x200000. This corresponds to multiplying all outputs by 1. The MSB bit corresponds to multiply by 4 and each successive bit multiplies by 2, 1, 0.5, and so on.
Table VII. Bit Map of the Per Channel Gain Register
MSB MSB-1 MSB-2 MSB-3 MSB-4 MSB-5 ---- LSB
4 2 1 1/2 1/4 1/8 1/2, 097, 152
The range of the adjustment is therefore from 0 to 8. This allows a digital PGA to be implemented to give input ranges smaller than ±0.625 V.
The per channel gain register is also used for system full­scale calibrations.

USE OF THE PER CHANNEL GAIN COEFFICIENT TO IMPLEMENT A PGA

The lowest available input range of the AD7739 is ±0.625 V. Suppose your signal range is only ±0.078 mV. The default per channel gain coefcient results in the out­puts shown in column 2 for the input shown in column 1. A per channel gain coefcient of all ones results in a digital gain of 8, and –78.125 mV corresponds to an output of all zeros and +78.125 mV to all ones.
Table VIII. Effect of Digital PGA with Gain = 8
Output Code with Output Code with Coefcient Coefcient VIN = 0x800000 = 0xFFFFFF
–78 mV 0x8FF972 0xFFCB92 0 0x800000 0x800000 +78 mV 0x7FFBE9 0x00346E
With a conversion time of 2.7 ms, the AD7739's output noise on the ±0.625 V range is only 1.2 V rms or19.9 bits rms. With a digital gain of 8, the user still has 16.9 bits of rms resolution on the ±0.078 mV range. Another important fac­tor for implementing a digital PGA is the 24-bit no missing codes performance of these parts at high output rates.
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PICKING COEFFICIENTS TO GIVE A SPECIFIC GAIN

If a user wants the input range to correspond to ±1.0 V, it is necessary to pick the per channel gain coefcient. The easiest way is to select the ±1.25 V range, put 1.0 V on the analog input, perform a system full-scale calibration, and record the contents of the per channel gain coefcient.
An alternative mathematical method is as follows: divide the actual input range by the desired input range and mul­tiple by 221, i.e., multiply 1.25 by 221 = 2621440d, which is 280000h. For this case, 1.25/1.0 is 1.25.

REMEMBER

You must set the mode bits in the mode register to 000 before writing to any of the calibration registers. Oth­erwise, if a calibration or conversion is in progress, the write will be ignored.
E03816–0–7/03(0)
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies.
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