Analog Devices AN641 Application Notes
AN-641
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/326-8703 • www.analog.com
A 3-Phase Power Meter Based on the ADE7752
By Stephen English and Rachel Kaplan
INTRODUCTION
This application note describes a high accuracy, low cost
3-phase power meter based on the ADE7752. The meter
is designed for use in a Wye-connected 3-phase, 4-wire
distribution system. The ADE7752 may be designed into
3-phase meters for both 3-wire and 4-wire service. This reference design demonstrates the key features of an ADE7752
based meter, and is not intended for production.
The ADE7752 is a low cost single-chip solution for electrical
energy measurement that surpasses the IEC 61036 Class
1 meter accuracy requirement. It typically realizes less
than 0.1% error over a 500:1 current dynamic range for
balanced polyphase loads. The chip contains a reference
circuit, analog-to-digital converters, and all of the digital
signal processing necessary for the accurate measurement
of active energy. A differential output driver provides
direct drive capability for an electromechanical counter, or
impulse counter. A high frequency pulse output is provided
for calibration. An additional logic output on the ADE7752,
REVP, indicates negative active power on any phase or a
possible miswiring. The ADE7752 data sheet describes
the device’s functionality in detail and is referenced several
times in this document.
DESIGN GOALS
Specifi cations for this Class 1 meter design are in accordance
with the accuracy requirements of IEC 61036, and Indian
Standards IS 13779-99. Tables I and II review the overall
accuracy at unity power factor and at low power factor.
Table I shows the specifi cations of the meter for both balanced loads and balanced lines. Table II addresses balanced
polyphase voltages with a single-phase load.
The meter was designed for an I
of 50 A/phase, an Ib of
MAX
5 A/phase, and a 100 impulses/kWh meter constant. The
ADE7752 provides a high frequency output at the CF pin.
This output is used to speed the calibration process and
provide a means of quickly verifying meter functionality
and accuracy in a production environment. CF is 16 times
F1, F2, the frequency outputs. In this case, CF is calibrated
to 1600 impulses/kWh. The meter is calibrated by varying the attenuation of the line voltage using the resistor
networks on each phase. Each phase to neutral voltage is
240 V. See the Channel 2 Input Network section.
An additional specifi cation for this meter design is taken
from IS 13779-99. The specifi cation states that the meter
must work with only one phase active at 30% lower and
20% higher than the nominal line value.
Table I. Accuracy Requirements
(for a polyphase balanced load)
Percentage Error Limits3
Current Value
1
PF2 Accuracy
Class 1 Class 2
0.05 Ib £ I < 0.1 Ib 1 ±1.5% ±2.5%
0.1 I
0.1 I
£ I < I
b
£ I < 0.2 Ib
b
1 ±1.0% ±2.0%
MAX
0.5 inductive
±1.5% ±2.5%
0.8 capacitive ±1.5%
NOTES
1
The current ranges for specifi ed accuracy shown in Table I are expressed
in accordance with IEC 61036, Table 15 percentage error limits, Section 4.6.1, p. 53.
2
Power factor (PF) in Table I relates to the phase relationship between the
fundamental voltage and current waveforms. In this case, PF can be
defi ned as PF = cos(), where is the phase angle between pure sinusoidal
current and voltage.
3
Accuracy is defi ned as the limits of the permissible percentage error. The
percentage error is defi ned as:
Percentage Error
energy registered by meter –true energy
=×
Table II. Accuracy Requirements
true energy
*
100%
(1)
(for a polyphase meter with single-phase load)
Percentage Error Limits
Current Value PF
Accuracy
Class 1 Class 2
0.1 Ib £ I < I
£ I < I
0.2 I
b
1 ±2.0% ±3.0%
MAX
MAX
0.5 inductive
±2.0% ±3.0%
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*
Accuracy class for unbalanced load as defi ned in IEC 61036, Table 13,
Section 4.6.1, p. 53, Edition 2.1.
AN-641
Figure 1 is a block diagram of a low cost, simple watthour
meter using the ADE7752. It shows the three phases and
how they are connected to the meter. Three current transformers sense the load current and convert the signals to
a proportional voltage required by the ADE7752. The total
energy is registered by a mechanical counter.
240V 240V
240V
MECHANICAL
COUNTER
VAP VBP
N VCP
16
15
14
5
6
7
ADE7752
8
9
10
13
1
CF
24
23
4
REVP
LOAD
ATTENUATION
NETWORKS
ANTI-
ALIASING
FILTERS
ANTI-
ALIASING
FILTERS
ANTI-
ALIASING
FILTERS
Figure 1. 3-Phase, 4-Wire/Wye Watthour Meter Block
Diagram
DETAILED DESCRIPTION
The front end of the meter is made up of three pairs
of voltage and current input networks. Each of the three line
voltages is attenuated and fi ltered through identical antialiasing fi lters. See the Channel 2 Input Network section.
The current channels’ signals are converted from current
to a voltage through current transformers and burden
resistors. The signals are then fi ltered by the antialiasing
fi lter on each of the three phases, and the result is applied
to the current inputs of the ADE7752.
Each phase of the meter has a power supply associated
with it. The power supply is shown in Figure 8. If power
is lost in two of the three phases, the meter will continue
to operate. Each phase has a corresponding LED that is
on when the respective phase is active.
A calibration network is associated with each of the three
line voltages. These circuits use binary-weighted resistor
values connected in series to set the amount of attenuation
needed for each of the three input voltages. Having ±25%
calibration ability to compensate for variations in the voltage reference and input fi lter components is recommended.
See the Design Calculations section.
An opto-isolator is provided on this meter, connected to
the CF pin of the ADE7752. This allows calibration of the
meter while isolating the calibration equipment from the
line voltages.
The instantaneous power and energy are calculated per
phase, and the net active energy is accumulated as a sum
of the individual phase energies inside the ADE7752. With
the ABS pin set low, the sum represents the absolute values
of the phase energies. With the ABS pin high, the ADE7752
takes into account the signs of the individual phase energies
and performs a signed addition. In the meter described in
this application note, ABS is set high.
If negative active power is detected on any of the three
phases, the REVP output LED of the ADE7752 is lit. This
feature is useful to indicate meter tampering or to fl ag
installation errors. The ADE7752 continues to accumulate
energy despite the status of the REVP output pin. REVP will
reset when positive power is detected again. The output
of REVP and the CF pulse are synchronous. If more than
one phase detects negative power, the REVP LCD remains
lit until all phases detect positive power.
An LED connected to the CF output of the ADE7752 displays
the energy measured in impulses/kWh. The ADE7752 data
sheet describes this operation in detail. The frequency outputs, F1 and F2, are used to drive the electromechanical
counter. See the Design Equations section.
This design has a startup current of 13.75 mA and a no-load
threshold of 3.3 W. See the Starting Current section.
DESIGN EQUATIONS
The ADE7752 produces an output frequency that is proportional to the summed values of the three phase energies.
A detailed description of this operation is available in the
ADE7752 data sheet. To calibrate the meter, the inputs to
the ADE7752 must be defi ned based on the equation:
VIVIV I F
××+×+×
22
()
11 2 2 3 3 17
2
V
REF
×
−
(2)
FF
12
, =
5.9
where:
I is the differential rms voltage signal on respective current channels
V is the differential rms voltage signal on respective voltage channels
is the reference voltage (2.4 V ± 8%) (V)
V
REF
is one of fi ve possible frequencies selected by using
F
1–7
the logic inputs SCF, S0, and S1. See Table II.
The calculations for this meter design are shown in the
Design Calculations section.
ADE7752 REFERENCE
Pin 12 of the ADE7752 can be used to connect an external
reference. This design does not include the optional reference circuit and uses the ADE7752 internal reference.
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AN-641
The on-chip reference circuit of the ADE7752 has a typical
temperature coeffi cient of 20 ppm/°C. Refer to the ADE7752
data sheet for graphs of typical performance characteristics
over temperature.
Current Transformer Selection
The current transformer is the device used in this design for
measuring load current. This sensor arrangement provides
isolation because the line-to-line voltage differs by more
than 498 V. Current transformers offer an advantage as
current sensors because they do not contact the conductor,
they handle high current and have low power consumption
and low temperature shift. Figure 3 illustrates the application used in this design for each channel of the 3-phase
meter. When selecting a current transformer, carefully
evaluate linearity under light load. The CT performance
should be better than the desired linearity of the meter
over the current dynamic range.
A current transformer uses the concept of inductance to
sense current. A CT is made up of a coil wound around
a ferrite core. The current-carrying wire is looped through
the center of this winding, which creates a magnetic fi eld
in the winding of the CT and a voltage output proportional
to the current in the conducting wire. The properties that
affect the performance of a given CT are the dimensions of
the core, the number of turns in the winding, the diameter
of the wire, the value of the load resistor, and the permeability and loss angle of the core material.
When choosing a CT, consider the dc saturation level. At
some high, fi nite value of current or in the presence of a
high dc component, the ferrite core material exhibits hysteresis behavior and the CT can saturate. Manufacturers
of CTs can specify this maximum level. The current range
is calculated using Equation 3.
I
MAX
2
N
ω
sec
R
BA
sat Fe
(3)
≈
where:
R is the resistance of the burden resistor and the copper wire
A
Fe
B
sat
.
represents the dimensions of the core.
is the value of the magnetic fi eld at which the core
material saturates.
is the number of turns in the CT.
N
sec
CTs may also cause a phase shift of the signal. A CT used
for metering should have a linear phase shift across the
desired current dynamic range. The phase error for a CT
is derived using Equation 4.
R
cosϕ
tan
δ=
L
ω
(4)
where:
R is the resistance of the burden resistor and the copper wire.
␦ represents the core losses.
L is a parameter based on the permeability of the core,
the dimensions of the core, and the square of the number
of turns.
The phase error caused by a particular CT should be measured with and compensated for by a low-pass fi lter before
the ADC inputs. Phase mismatch between channels will
cause energy measurement errors. See the Correct Phase
Matching between Channels section. Low-pass fi lters are
already required by the ADE7752 for antialiasing, and are
covered in more detail in the Antialias Filters section. The
corner frequency of these antialiasing fi lters on the current
channels can be fi ne tuned by changing the components
in the RC circuit in order to add additional compensation
for CT phase shift.
Channel 1 Input Network
Figure 3 shows the input stage to Channel 1 of the meter.
The current transformer has a turns ratio of 1500:1. The
burden resistor is selected to give the proper input voltage range for the ADE7752, less than 500 mV
PEAK
. See the
Design Calculations section. The additional components
in the input network provide fi ltering to the current signal.
The fi lter corner is set to 4.8 kHz for the antialias fi lters.
See the Antialias Filters section.
PHASE A
LOAD
CURENT
CURRENT TRANSFORMER
R82
R83
R15
R17
IAP
C16
IAN
C17
Figure 2. ADE7752 Phase A – CT Wiring Diagram
The burden is center tapped so that external capacitive
coupling may be reduced. The wires of the CT are twisted
tightly to reduce noise.
Channel 2 Input Network
The meter is calibrated by attenuating the line voltage
down to 70 mV. See the Design Calculations section. The
line voltage attenuation is carried out by a resistor divider
as shown in Figure 4. Phase matching between Channel
1 and Channel 2 is important to preserve in this network.
Figure 4 shows the attenuation network for the voltage
inputs. All three phases have the same attenuation network. The –3 dB frequency of this network, on Phase A
for example, is determined by R75 and C21 because the
sum of the other resistors in the network is much greater than
R75. The approximate equation is shown in Figure 3.
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–3–
AN-641
PHASE A
240V
R80 R81
R66
R68
R70
R79
R76
R64
R65
R78
R73
R75
f
= (2 ⴛ R75 ⴛ C21)
–3dB
C21
VAP
70mV
Figure 3. Attenuation Network
Because the ADE7752 transfer function is extremely linear,
a one-point calibration (I
) at unity power factor is all that is
b
needed to calibrate the meter on each phase. If the correct
precautions were taken at the design stage, no calibration
is necessary at low power factor (PF = 0.5).
CORRECT PHASE MATCHING BETWEEN CHANNELS
Correct phase matching is important in energy metering
applications because any phase mismatch between channels will translate into signifi cant measurement error at
low power factor. The errors induced in the system at
PF = 1 are minimal. A power factor of 0.5 with a phase
error of as little as 0.5
°
will cause a 1.5% error in the
power measurement. If current lags the voltage by 60°
(PF = –0.5) and pure sinusoidal conditions are assumed,
the power is easily calculated, on a single phase, as
V rms ⫻ I rms ⫻ cos(60°).
An additional phase error can be introduced to the overall
system with the addition of antialiasing fi lters. Phase error
(
) is introduced externally to the ADE7752 (e.g., in the
e
antialias fi lters). The error is calculated as
%Error cos – cos cos 100%
=° +
[]
e
°×() ( )/ ()δδφ δ
(5)
See Note 3 for Table I, where ␦ is the phase angle between
voltage and current and
is the external phase error.
e
With a phase error of 0.2°, for example, the error at PF = 0.5
inductive (60°) is calculated as 0.6%. As this example demonstrates, even a very small phase error will produce a
large measurement error at low power factor.
Current transformers often produce a phase shift between the
current and voltage channels. To reduce the error caused
at low power factor, the resistors in the antialias fi lter can
be modifi ed to shift the corner frequency of the fi lter (in the
current channel), introducing more or less lag.
The antialias
fi lters are described in detail in the next section.
The phase error should be measured independently on
each phase (A,
B, and C). To calibrate the phase error
on one phase of the meter, a two-point measurement
is required. The fi rst measurement should be at the test
current, I
, with unity power factor and the second at low
b
power factor (0.5 capacitive). The measurement error is
processed according to the following equation:
CF
PF
=1
Error
CF
=
–
PF
= 0.5
CF
2
PF
=1
2
(6)
The phase error is then:
Phase Error arcsin
= –
Error
3
(7)
For a single-pole RC low-pass fi lter, the phase lag is:
θπ=–arctan 2 fRC×
()
(8)
For example, if the antialias fi lters are single-pole lowpass fi lters with R = 1 k⍀ and C = 33 nF, the phase lag at
50 Hz is 0.59° according to Equation 8. If the measurements performed with this fi lter in place on the current
and voltage phases show that the CT causes 1° phase error
(using Equations 6 and 7), then the resistor value should be
2.68 k⍀ to give 1.59° total phase shift. Because there is
generally minimal part-to-part variation for CTs, the same
fi lters usually can be used in production on all three phases
to compensate for the constant phase error.
ANTIALIAS FILTERS
As mentioned in the previous section, one possible source
of external phase errors is the antialias fi lters on the input
channels. The antialias fi lters are low-pass fi lters placed
before the analog inputs of any ADC. They are required
to prevent aliasing, a possible distortion due to sampling.
Figure 4 illustrates the effects of aliasing.
ALIASING EFFECTS
IMAGE
FREQUENCIES
SAMPLING
FREQUENCY
0 2 417
FREQUENCY (kHz)
833
Figure 4. Aliasing Effects
Figure 4 shows how aliasing effects could introduce
inaccuracies in an ADE7752 based meter design. The
ADE7752 uses two ⌺-⌬ ADCs to digitize the voltage and
current signals for each phase. These ADCs have a very
high sampling rate, i.e., 833 kHz. Figure 4 shows how
frequency components (indicated by the darker arrows)
above half the sampling frequency (also known as the
Nyquist frequency), i.e., 417 kHz, get imaged or folded back
down below 417 kHz (indicated by the gray arrows). This
will happen with all ADCs, regardless of the architecture.
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In the example shown, only frequencies near the sampling
frequency, i.e., 833 kHz, will move into the band of interest
for metering (0 kHz to 2 kHz). This fact
very simple LPF (low-pass fi lter) to attenuate
allows the use of a
these high
frequencies (near 833 kHz) and thus prevent distortion in the
band of interest. The simplest form of LPF is the simple RC
fi lter, which has a single pole with a roll off or attenuation
of –20 dBs/decade.
Choosing the Filter –3 dB Frequency
In addition to having a magnitude response, fi lters also h ave
a phase response. The magnitude and phase response
of a simple RC fi lter (R = 1 k⍀, C = 33 nF) are shown in
Figures 5 and 6. Figure 5 shows that the attenuation near
900 kHz for this simple LPF is greater than 40 dBs. This is
suffi cient attenuation to ensure that no ill effects are caused
by aliasing.
0dB
–20dB
–40dB
frequency components to be aliased and cause accuracy
problems in a noisy environment.
0
–20
–40
–60
PHASE (Degrees)
–80
–100
10 100 1k 100k10k 1M
FREQUENCY (Hz)
Figure 6. RC Filter Phase Response
–0.4
(50Hz, –0.481)
–0.5
–0.6
(R = 900⍀, C = 29.7nF)
(50Hz, –0.594)
(R = 1k⍀, C = 33.0nF)
–60dB
10 100 1k 100k10k 1M
FREQUENCY (Hz)
Figure 5. RC Filter Magnitude Response
The phase response can introduce signifi cant errors if the
phase response of the LPFs on both current and voltage
channels are not matched. This is true for all of the phases
in which the desired (120°) phase shift between phases
should be preserved. Phase mismatch can easily occur
as a result of poor component tolerances in the LPF. The
lower the –3 dB frequency in the LPF (antialias fi lter), the
more pronounced these errors will be at the fundamental
frequency component or line frequency. Even with the corner frequency set at 4.8 kHz (R = 1 k⍀, C = 33 nF), the phase
errors due to poor component tolerances can be signifi cant.
Figure 7 illustrates this point.
In Figure 6, the phase response for the simple LPF is
shown at 50 Hz for R = 1 k⍀ ± 10%, C = 33 nF ± 10%.
Remember,
a phase shift of 0.2° can cause measurement
errors of 0.6% at low power factor. This design uses resistors of 1% tolerance and capacitors of 10% tolerance for
the antialias filters to reduce the likelihood of problems
resulting from phase mismatch. Alternatively, the corner
frequency of the antialias filter could be pushed out to
10 kHz to 15 Hz. The corner frequency should not be made
too high, however, because doing so could allow high
PHASE (Error)
–0.7
–0.8
45 50 55
FREQUENCY (Hz)
(50Hz, –0.718)
(R = 1.1k⍀, C = 36.3nF)
Figure 7. Phase Shift at 50 Hz Due to Component
Tolerances
Note that this risk is also why precautions were taken
with the design of the calibration network on the voltage
channels. The tolerance of the components used in these
networks is low to prevent errors.
CALIBRATING THE METER
The meter is calibrated by setting the appropriate value
to the S1 and S0 pins and by varying the gains of the voltage channels. The current channels are fi xed by the turns
ration of the CT and the burden resistor.
To ensure the proper output frequency, the meter is
calibrated using CF. The gains of the voltage channels
are varied to ensure that the product of the current and
voltage channels (active energy) is calibrated to 1600
impulses/kWh. The voltage channel uses a resistor divider
network to adjust the attenuation. The setup of this network
is described in the Channel 2 Input Network and Design
Calculations sections.
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