Analog Devices AN593 Application Notes

AN-593

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

VID0

VID1

VID2

VID3

LRFB1

LRDRV1

CS–

CS+

GND

DRVH

DRVL

VCC

LRFB2

LRDRV2

COMP

CT

FROM CPU

C1

100␮F

C15
1␮F

C13
100␮F

Q2

*

C12
1␮F

Q1

*

C3

150pF

R

B

10.5k⍀

R

A

78.7k⍀

C

OC

2.7nF

3.3V

C17 C18 C19C20 C21

V

LR2

1.5V,
2A

R12

4m⍀

L1

1.7␮H

Q3

SUB75N03-07

C8
1000␮F

C9
1000␮F

C7
22␮F

L2

1␮H

VCC CORE

1.30V TO

2.05V

15.1A

5V

5V STANDBY

12V

D3

MBR052LT1

D2

MBR052LT1

V

LR1

2.5V, 2A

C6
1␮F

R4

220⍀

R3

220⍀

C10
1nF

3.3V

ADP3178

+++++

+++

+

+

+

*

SUB45N03-13L

C2
68pF

C11
68pF

R2

24.9k⍀

R11

13.3k⍀

1000␮F ⴛ 5

RUBYCON ZA SERIES

24m⍀ ESR (EACH)

R1

16.9k⍀

R10

26.7k⍀

Q4

SUB45N03-13L

a

APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: [phone] • Fax: [phone] • www.analog.com

Stability and Transient Analysis of the Miller-Compensated

Linear Regulators on the ADP3178

By Jeritt Kent and Joe Buxton

Analog Devices’ power management group has been in
the desktop computer VRM controller market since the
mid-90s. The ADP3158 programmable synchronous
buck converter was positioned to fit into designs con­forming to Intel’s VRM 8.4 specifications. Designers
typically used the ADP3158’s buck converter for the CPU
core switching supply and its two integrated fixed linear
regulators to generate additional system voltages. In
one major application, the ADP3158 linear regulators
were used for generating a 2.5 V, 4.3 A DDR VDDQ sup­ply and the 1.5 V, 1.5 A GTL supply. In order to generate
the 1.5 V supply, designers used the 1.8 V linear regula­tor, driving its inverting input with the output of the 2.5 V

regulator through an R

1.8 10 / 7 –2.5 3 / 7 1.5

() ()

This approach added a minor tolerance error and noise
component to the resultant 1.5 V supply. Additional
compensation was added to control loop disturbances
initially thought to be sympathetic to the frequency of
the switching supply. Unfortunately, these techniques
did not optimize performance of both the loop stability
and overall transient response. Design using the
ADP3178 resolves these issues. The on-board references
of the ADP3178 are now based on a 1.0 V reference versus
the 1.8 V and 2.5 V references on the ADP3158.

ratio of 3/7:

f/Rin

= V

REV. 0

Figure 1. Complete Implementation of the ADP3178

© Analog Devices, Inc., 2002

AN-593

Figure 1 shows a complete implementation of the
ADP3178. Whereas the ADP3158 linear regulators use a
fixed 10 kΩ resistor, the ADP3178 uses voltage dividers
in the feedback. Equations 32 and 33 of the ADP3178
data sheet provide the calculations for these resistor
sizes. Figure 1 shows standard 1% resistors that
approximate a 10 kΩ equivalent for both 2.5 V and 1.5 V
supplies. The output voltage can be easily set from 1.0 V to
within V
tied to the drain of the external N-channel MOSFET. In
addition, the lower on-board reference voltages on the
ADP3178 versus the ADP3158 allow for better noise
immunity for sub 1.8 V output voltage requirements.

Miller compensation is used for the ADP3178 design.
The open-loop gain,
ers on the ADP3178 from simulation is approximately
450 V/V (see Figure 2). Taking advantage of this gain, a
relatively small compensation capacitor can be placed
in the feedback of the linear regulator amplifier from
LRFB to LRDRV. This capacitor, along with the parallel
combination of the resistive voltage divider used to set
the output voltage, sets the dominant pole for the linear
regulator loop via the equation:

where
open-loop gain of the linear regulator amplifier,
MOSFET gate capacitance (2.7 nF for the SUB45N03­13L), and
divider).

The dominant pole location should be set to roll off the
open-loop gain of the amplifier to 0 dB at approximately
the same point as the second pole comes into the pic­ture. The output impedance of the MOSFET and the load
capacitance set the second pole. The MOSFET shown in
the ADP3178 data sheet is the SUB45N03-13L. The method
for selecting a MOSFET for a particular application
should be driven by power dissipation requirements.
It should also have a logic level V
In addition, selection of a MOSFET with lower Qg (gate
charge) will improve the transient response and slew
rate. Ideally, one would use a drain supply voltage
sufficiently above the required output voltage to give
headroom on V
keeping the power dissipation to a minimum.
The 4.3 A requirement on the 2.5 V DDR VDDQ supply
would give a maximum power dissipation figure of

0.8 × 4.3 = 3.44 W given a 3.3 V supply. That figure can be

(for the required load current) from the supply

ds

A

, of the linear regulator amplifi-

V

P1/2 C A C R

=×××

dmVgf

C

is the Miller compensation capacitor,

m

R

is R1储R2 (the resistors used in the voltage

f

π

()

()

for a required output current while

ds

()

+

×

A

V

C

g

for easier drive.

th

is the
is the

dropped to 2.15 W if a 3 V drain supply is available. After
selecting a MOSFET and package capable of handling
the power, one should check the transconductance, g
For example, the SUB45N03-13L has a g
for a 1 A load current.

Because the output capacitance of the MOSFET is very
small compared to the load capacitance, the second
pole for this Miller configuration can be simplified to:

P1/2 R R C

=×××

2OESR L

Where
capacitance in this paper is meant to describe the physi­cal capacitor placed between the source of the MOSFET
and analog ground.

Some authors refer to the sum of the capacitances
driven by the MOSFET’s source as the bypass capaci­tance, C
load capacitance. For example, if the linear regulator
drives the supply voltage for five other devices, each of
which locally bypasses VDD to VGND through the typi­cal 0.1 µF ceramic capacitor (ESR is negligible for these
capacitors), this bypass capacitance would be only 0.5 µF
versus, say, a 10 µF load capacitance. The pole contrib­uted by the bypass capacitance for this compensation
approach is usually well beyond the “zone of concern.”

For example, if the load capacitor is a 10 µF MLCC (with
an ESR of around 10 mΩ) and the SUB45N03-13L
is used, the second pole lands at 208 kHz. The pole con­tributed by 0.5 µF of bypass capacitance is around
32 MHz, as:

Given a constant gain-bandwidth product for this volt­age feedback circuit, a dominant pole location near
P
through unity gain at 208 kHz. Figure 2 illustrates the
frequency response. Using a value of 10 kΩ for Rf, C
would be about 71 pF, per the equation for Pd above.
68 pF is the closest standard value, as seen in Figure 1.
Given that the ADP3178 requires a feedback voltage of

1.0 V, the 10 kΩ equivalent feedback resistance for gen­erating 2.5 V would be R
resistor in Figure 1) and R
ground). The Thevenin value of 10 kΩ is a convenient
value and can be changed (which also changes C
However, it should not be made too large due to the
input bias current of the linear regulator.

CL

is the load capacitance and

. This value is typically smaller than that of the

BP

P1/2 R C

3 ESR BP

= 208 kHz/450 = 462 Hz is needed in order to cross

2/AV

π

()

=×××

()

π

()

= 25 kΩ (replacing the 10 kΩ

1

= 16.7 kΩ (tied from LRFB to

2

of 15 Siemens

m

×

R

= 1/gm. Load

O

m

m

.

m

).

–2–

REV. 0