Analog Devices AN586 Application Notes

AN-586

a

APPLICATION NOTE

One Technology Way•P.O. Box 9106•Norwood, MA 02062-9106•Tel: [phone]•Fax: [phone]•www.analog.com

LVDS Data Outputs for High-Speed Analog-to-Digital Converters

by Cindy Bloomingdale and Gary Hendrickson

Analog-to-digital converter (ADC) sample rates have
been increasing steadily for years to accommodate
newer bandwidth-hungry applications in communication,
instrumentation, and consumer markets. Coupled with
the need to digitize signals early in the signal chain to
take advantage of digital signal processing techniques,
this has motivated the development of high-speed ADC
cores that can digitize at greater than 100 MHz to
200 MHz clock rates with 8- to 12-bit resolution.

In standalone converters, the ADC needs to be able to
drive receiving logic and accompanying PCB trace capaci­tance. Current switching transients due to driving the
load can couple back to the ADC analog front end,
adversely affecting performance. One approach to mini­mize this effect has been to provide the output data at
one-half the clock rate by multiplexing two output ports,
reducing required edge rates, and increasing available
settling time between switching instants. The
AD9054A, AD9884, AD9410, and AD9430 are
recent examples.

A new approach to providing high-speed data outputs
while minimizing performance limitations in ADC applica­tions is the use of LVDS (low voltage differential
signaling). ADI is incorporating LVDS output capability
in a new 170 MSPS, 12-bit ADC—the AD9430—and will
include LVDS in some of its future high-speed ADCs and
DACs (digital-to-analog converters).

LVDS is, as the name says, a low voltage differential
signaling scheme. The operative words here are

voltage

have developed specifications that will be discussed
later in this note. Lower voltage signal swings have the
intrinsic advantage of shorter switching times as well as
reduced EMI concerns (adjacent differential traces tend
to cancel each others’ EMI).

(~350 mV) and

Figure 1. LVDS Output Levels

differential

. Standards bodies

350mV~1.2V

low

Differential signaling also has the well-known common­mode rejection benefit. Noise that is coupled to the
signals tends to be common to both signal paths and
cancelled out by a well designed differential receiver.
LVDS outputs are current output stages requiring a 100 W
terminating resistor at the receiver, differing from
CMOS outputs that generally do not require termina­tion. The current output results in a fixed dc load current
on the output supplies—avoiding current spikes on the
supply that can couple to the sensitive analog front end.

OUT+

LVDS

DRIVER

Figure 2. LVDS Requires Far End Termination

STANDARDS

Two standards have been written to define LVDS. One is
the ANSI/TIA/EIA-644 which is titled, ”Electrical Charac­teristics of Low Voltage Differential Signaling (LVDS)
Interface Circuits.” The other is IEEE Standard 1596.3
which is titled, ”IEEE Standard for Low-Voltage Differen­tial Signals (LVDS) for Scalable Coherent Interface
(SCI).” A brief summary of these two standards is
provided below.

ANSI/TIA/EIA-644

The ANSI/TIA/EIA Standard was developed under the
Telecommunications Industry Association (TIA) Subcom­mittee TR-30.2 and contains only generic electrical
specifications for LVDS. Its purpose was to create a
general high-speed interface standard for use in point­to-point connections between data communications
equipment. The maximum data signaling rate is 655
Mbps. The TIA Subcommittee intended other
standards bodies to reference ANSI/TIA/EIA-644 in more
complete interface specifications between transmitters
and receivers.

OUT–

100

REQUIRED

TERMINATION

RESISTOR

LVDS

RECEIVER

REV. 0

© Analog Devices, Inc., 2002

AN-586

IEEE Standard 1596.3

The IEEE Standard 1596.3 was developed as an exten­sion to the 1992 SCI protocol (IEEE Standard 1596-1992).
The original SCI protocol was suitable for high-speed
packet transmissions in high-end computing and used
ECL levels. However, for low-end and power-sensitive
applications, a new standard was needed. LVDS signals
were chosen because the voltage swing is smaller than
that of ECL outputs, allowing for lower power supplies
in power-sensitive designs.

AD9430 LVDS Specifications

As mentioned above, the AD9430 is the first in a series
of high-speed A/D converters designed with an LVDS
output option (CMOS outputs are also available). It is
a 12-bit, 170 MSPS ADC optimized for outstanding
dynamic performance in wideband carrier systems. A
simplified equivalent circuit for the AD9430 LVDS
outputs is shown in Figure 3.

V

DD

IS T

Q1 Q2

A– A+

OUT+

operation can be explained as follows (also see Figure 4).
A current source (I

T) is established on-chip from VDD and

S

is steered through Q2. In this example, a logic 1 is being
transmitted (V+ > V–). The 100 W receiver termination
resistor provides a current path for the current to return
back to the driver to the lower current sink (I

B) to

S

ground through Q3. The nominal current source/sink is
set to approximately 3.5 mA, resulting in a 350 mV swing
for an external termination resistor of 100 W.

V

DD

IS T

Q1 Q2

100 R

A– A+

Q3 Q4

A+ A–

B

I

S

Z0 = 50

Z0 = 50

TERM

V+

V–

LVDS

RECEIVER

Figure 4. LVDS Output Current

OUT–

Q3 Q4

A+ A–

mately 1.2 V (common-mode control circuitry not shown),
the output resistor can be modeled as two 50 W resis-
tors in series with their center-tap sitting at 1.2 V. This
provides a match to a typical PCB trace characteristic

Assuming an output common-mode voltage of approxi-

B

I

S

impedance (Z

) of 50 W and minimizes reflections.

O

The AD9430 LVDS outputs are more closely aligned with

Figure 3. LVDS Data Outputs

the ANSI/TIA/EIA-644 specification. Table I compares
the ANSI/TIA/EIA-644 and AD9430-170 specifications.

The differential outputs are indicated in Figure 3 by
OUT+, the positive or true data output, and OUT–, the
complement data output of the differential signal. Circuit

Table I. Summary of ANSI/TIA/EIA-644 and AD9430 Specifications

ANSI/TIA/EIA-644 AD9430-170

Specification Min Max Typ

Output Current 2.47 mA 4.54 mA Determined by RSET (nominally 3.5 mA)
Differential Output Voltage Magnitude 247 mV 454 mV 350 mV
Output Offset Voltage (Common Mode) 1.125 V 1.375 V 1.2 V
Transition Time: Rise Time (t

) and £0.3  tUI = 0.3  5.88 ns 0.5 ns

R

Fall Time (tF); 20% to 80% = 1.76 ns

–2–

REV. 0