Analog Devices AN555 Application Notes

AN-555

CLK

WORD

GENERATOR

DATA IN

DIGITAL

DATA BUS

DUAL DAC

EVALUATION

BOARD

AVDD DVDD

ANALOG

VDD

(3V TO 5V)

DIGITAL

VDD

(3V TO 5V)

ACOM DCOM

CLOCK

SOURCE

OSCILLOSCOPE

SPECTRUM
ANALYZER

DATA

OUT

a

APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com

Using the AD9709, AD9763, AD9765, AD9767 Dual DAC Evaluation Board

By Steve Reine and Dawn Ostenberg

GENERAL DESCRIPTION

The AD9709, AD9763, AD9765 and AD9767 are high­speed, high-performance dual DACs (8-, 10-, 12-, 14­bits) designed for I/Q transmit applications and for appli­cations where board space is at a premium. The
evaluation board allows the user to take full advantage
of the various modes in which the AD976x can operate.
This includes operation as dual DACs with their own indi­vidual digital inputs, as well as interleaved DACs where
data is alternately written from digital input Port 1 to
either of the two DACs. Information on how to operate
the evaluation board is included in this application
note. However, for more detailed performance informa­tion, the reader should consult the individual data
sheets for the AD9709, AD9763, AD9765, and AD9767.

Figure 1. Typical Test Setup to Evaluate Performance
of AD976x Dual DAC Using Evaluation Board

The 8-, 10-, 12-, and 14-bit DACs in this family are all pin­for-pin-compatible and are MSB justified. Therefore, the
same evaluation board can be used to evaluate all
four parts.

EVALUATION SETUP

To evaluate the performance of the AD976x dual DAC
family, a small set of measurement and signal genera­tion equipment is needed. Figure 1 shows a typical test
setup. Power supplies capable of driving from 3 V to 5 V
are needed for both analog and digital circuitry on the
evaluation board. A signal generator and digital word
generator are needed to provide the data and clock
inputs. On the output, an oscilloscope or spectrum
analyzer may be needed, depending on the type of per­formance being analyzed.

TP10

L1

DVDD

BEAD

C2

0.01mF

C9
10mF
25V

0.1mF

C3

TP37 TP38

TP43

DVDD1 DVDD2 AVDD

DCOM1

DCOM2

REV. 0

DVDDIN

BAN-JACK

BAN-JACK

DVDD

C1

0.001mF

Figure 2. Analog and Digital Power Connections on Dual DAC Evaluation Board

TP39

DGND

DUAL DAC

AD9709
AD9763
AD9765
AD9767

POWER CONNECTIONS

The AD9709, AD9763, AD9765, AD9767 dual DACs all
have separate digital and analog power and ground
pins. Analog and digital power and ground have their own
banana-style connectors on the dual DAC evaluation
board. The best performance when using the evaluation
board is achieved when analog and digital power and
ground are connected to separate power supplies.

Figure 2 shows the power supply, grounding, and decou­pling connections for the evaluation board and for the
DAC itself. Note that for best noise rejection on the
power supplies, the high value bulk capacitors are
placed at the external power connectors, while the
smaller value capacitors, needed for high frequency
rejection, are located close to the DAC.

TP11

L2

AVDDIN

ACOM

BAN-JACK

BAN-JACK

C13

0.1mF

BEAD

AVDD

C12

0.01mF

C10
10mF
25V

AVDD

TP40 TP41

C11

0.001mF

TP44

TP42

AGND

AN-555

Analog and digital supplies can be run at either 3 V or
5 V, and do not have to run from the same supply volt­age. Regardless of supply voltage, the digital input data
can be safely run from 3 V or 5 V logic levels, as long as
the proper resistor packs are placed in the digital input
data path (see Digital Inputs section).

DIGITAL INPUTS

The digital inputs on the dual DAC evaluation board are
designed to accept inputs from any generic word gen­erator. However, when running the DAC at high sample
rates, the quality of the digital data can have an impact
on the performance of the DAC. As an example, if the
edges of the digital information are slow, or the edges of
the various bits are skewed from each other in time,
specifications such as SNR and SINAD may be degraded.

The digital input path on the evaluation board includes
both pull-up and pull-down plug-in resistor packs. The
pull down resistors allow the user to apply digital logic
at 5 V levels when the DAC digital supply is operating at
3 V, and the pull-ups allow 3 V logic levels when the DAC
is run from a 5 V digital supply. The digital input signal
path is shown in Figure 3.

DVDD

NOT SUPPLIED WITH

DIGITAL DATA

INPUT

NOT SUPPLIED WITH

EVALUATION BOARD

22V

EVALUATION BOARD

DATA INPUT ON
AD9763/AD9765/AD9767

NOT SUPPLIED WITH
EVALUATION BOARD

CLOCK INPUTS

SMA connectors S1 to S4 are intended to be used as

clock and control lines for the AD976x, and are 50 Ω ter-

minated. The selection of JP9 also allows the user to
select a clock generated on the same digital data bus as
the input data.

Jumpers JP1 to JP7, JP9, and JP16 control the clock
inputs for the various clock modes in which the dual
DACs can operate. It is recommended that the clock
source be a square wave with minimal overshoot and
undershoot. Overshoot and undershoot beyond the sup­ply rails can inject noise onto the clock, which may result
in jitter and reduced DAC performance. The dual DACs
can operate with a sine wave clock, but dynamic perfor­mance will be degraded. Figure 4 shows the clock input
section and jumper options for the dual DAC evaluation
board.

MODES OF OPERATION

The AD976x dual DAC family is designed to operate
either as two completely separate DACs in dual DAC
mode, or with a single digital input port in which the input
data is alternately sent to either of the two DACs (inter­leaving mode).

DGND

Figure 3. Input Structure of Digital Input Signal Path on
Dual DAC Evaluation Board

DCLKIN1 DCLKIN2

WRT1IN

IQWRT

CLK1IN

IQCLK

CLK2IN

RESET

WRT2IN

IQSEL

TP29

S1

TP30

S2

TP31

S3

TP32

S4

R1
50VR250VR350VR450V

Figure 4. Jumper Options for Clock Input Section on Dual DAC Evaluation Board

JP16

JP5

IC

JP4

IC

JP3

I

JP9

DVDD

JP2

DVDD

JP1

DVDD

C

JP6

LH

D

PRE

J
K

U1

CLK

Q

CLR

1

74HC112

JP7

DGND;8

HL

WRT1/IQWRT
CLK1/IQCLK
CLK2/IQRESET
WRT2/IQSEL

AD9709/AD9763/AD9765/AD9767

DVDD;16

–2–

REV. 0

AN-555

DUAL DAC MODE

Jumper J8 controls the logic level of the MODE pin on
the AD976x dual DAC. With this jumper in the D posi­tion, the mode pin is pulled to a high logic level and the
AD976x is in dual DAC mode.

The simplest method for operating the dual DAC evalua­tion board in the dual DAC mode is to select a common
clock for WRT1, WRT2, CLK1, and CLK2. An external
clock generator can be selected by inserting JP16, or a
clock from the word generator can be selected by insert­ing JP9. By inserting JP3, JP4, and JP5 all in the C position,
the selected clock can be applied to all four clock inputs.

Different combinations of JP3, JP4, and JP5 allow
multiple options if the user desires to drive the WRT
and CLK inputs from separate clocks.

In the dual mode, jumpers JP1 and JP2 should be
removed. The state of Jumpers JP6 and JP7 does not
matter in this mode.

Table I illustrates the jumper positions required to oper­ate in the dual DAC mode of operation.

Table I. Jumper Options for Dual DAC Mode

Jumper Position Description

JP1, JP2,
JP6, JP7 Removed These are only used in

interleaved mode.

JP3, JP4,
JP5 C With these in the B posi-

tion, the evaluation board
can be run with one com­mon clock.

detailed information on the functions of these inputs, as
well as the DAC input and output timing, see the
AD9709, AD9763, AD9765, and AD9767 data sheets.

Operation with a single clock can be achieved by select­ing JP16 or JP9 for the clock source and inserting JP5 in
the C position, and removing JP3. JP4 can be used to
control IQRESET, but for most evaluations can simply be
tied low (Position I).

In interleaving mode, digital data present at input Port 1
is written into the Port 1 or Port 2 input buffers internal
to the DAC on the rising edge of IQWRT. The port into
which data is written depends on the state of IQSEL at the
time of the IQWRT rising edge. If IQSEL is high when the
rising edge occurs, data will be written to input Port 1. If
IQSEL is low at that time, data will be written to input
Port 2.

U1 on the evaluation board provides an alternating
IQSEL signal by toggling on every falling edge of
IQWRT. To enable this function, insert JP1 and JP2 and
remove JP3. JP6 and JP7 are used to synchronize the
input data stream with the IQSEL pin. To perform this
synchronization, power up the evaluation board with the
IQWRT and input data clocks disabled and at logic low. If
the first word in the digital data stream is meant for
Channel 1, preset U1 by inserting JP7 in the H position,
temporarily insert JP6 in the L position, then permanently
in the H position. If the first word in the data stream in
intended for Channel 2, reset U1 by inserting JP6 in the
H position, insert JP7 temporarily in the L position, then
permanently in the H position.

Table II illustrates the jumper positions required to oper­ate in the dual DAC mode of operation.

JP8 D Enables Dual DAC Mode.

JP9 Optional Selects clock from word

generator. Remove JP9 if
clock source is from S1/JP16.

JP16 Optional Selects clock from connec-

tor S1. Remove JP16 if clock
source is from JP9/JP16/
DCLK1, DCLK2.

INTERLEAVING MODE

With jumper JP8 in the I position, the MODE pin on the
AD976x is pulled to a logic low level and the DAC is in
interleaving mode. In this mode, a single stream of digi­tal data drives Port 1 on the DAC. This stream of data
contains alternating bits from two data channels. By
using the correct clock and control signals, data in the
two channels will be separated and sent to the correct
DAC outputs. This is typical of an I/Q application.

In interleaving mode, the definitions for the four clock
inputs change. WRT1, WRT2, CLK1, and CLK2 become
IQWRT, IQCLK, IQRESET, and IQSEL, respectively. For

REV. 0

Table II. Jumper Options for Interleaved Mode

Jumper Position Description

JP1, JP2 Inserted These enable U1 to generate the

alternating logic signal for IQSEL.

JP3 Remove If the IQSEL logic is to be gener-

ated by U1, this is not needed.

JP4 I Use to allow S3 control of

IQRESET pin.

JP5 C Allows IQWRT and IQCLK to be

driven by a common clock.

JP6, JP7 These are used to preset the

IQSEL pin before the data clock
is enabled. See text for descrip-

tion of use.
JP8 I Enables Interleaved Mode.
JP9 Optional Selects clock from word genera-

tor. Remove JP9 if clock source

is from S1/JP16.
JP16 Optional Selects clock from Connector S1.

Remove JP16 if clock source is

from JP9/DCLK1, DCLK2.

–3–

AN-555

CLOCK TIMING/PERFORMANCE

To ensure that specified setup-and-hold times are met,
the digital data inputs should change state on the falling
edge of the clock. However, due to timing skews and
delays inherent in some circuits, this does not always
happen. If the timing of the data transition and the rising
edge of the clock violates the setup-and-hold times, SNR
performance will be seriously degraded. Figure 5 shows
the valid window during the clock cycle in which the
digital input data can transition with no degradation in
SNR performance.

tS t

H

DATA

CLOCK

DATA

CLOCK

CHANNEL 2

CHANNEL 1

Figure 5. Valid Window for Data Transition During
Clock Cycle

Correct timing can be verified by generating a word pat­tern that repeatedly toggles the LSBs between Logic 1
and Logic 0. The user will also need a digital oscillo­scope with persistence capability.

Place one probe from the scope on the clock input of the
DAC. The sensitivity of this measurement is in the tenths
of nanoseconds, so the probe should be placed as close
as possible to the DAC itself. In addition, the scope
should be set to trigger from this channel. Place a second
probe from the oscilloscope on the LSB input of the
DAC, again as close as possible to the DAC itself. The
barrels of both probes should be grounded to the
evaluation board, as close to the measurement point as
possible. A convenient way of doing this is to wrap a
piece of bus wire around the barrel and then solder the
other end of the bus wire to the PCB. Figure 6 illustrates
a typical oscilloscope display for this test, as well as the
proper way to use the scope probes.

For the most accurate results, identical high input
impedance, low input capacitance probes should be
used. If possible, they should also be calibrated.

The data setup time can be measured by placing a vari­able delay between the clock generator and the clock
input of the word generator. This is most often done by
using a pulse generator. By adjusting the delay of the
digital data, place the data transition point on the falling
edge of the clock. At this point, SNR should be opti­mized. Increase the amount of delay for the digital data,
moving the transition point closer to the rising edge. As
the data transition gets close to the rising edge, SNR will
begin to degrade. At this point, on the oscilloscope,
measure the time difference between the data transition
and the midpoint of the rising edge. This is the mea­sured data setup time.

Figure 6. Verifying Clock/Data Timing on Evaluation
Board, Proper Use of Scope Probes

To measure the input data hold time, perform the same
operation, but start with the data transition occurring at
the midpoint of the clock transition. SNR at this point
will be completely degraded. Increase the digital input
delay until the SNR is optimized. At this point, again
measure the time difference between the data transition
and the midpoint of the rising edge. This is the mea­sured data hold time.

REFERENCE OPERATION

The AD9709, AD9763, AD9765, AD9767 contain a single

1.2 V reference that is shared by both of the DACs on the
chip. This reference drives two control amplifiers that
independently control the full-scale output currents in
each of the two DACs. Using the 1.2 V reference and the
control amplifier, reference currents are produced for
each DAC in an external resistor attached to FSADJ1
(DAC1) and to FSADJ2 (DAC2). The relationship between
the external resistor current and the full-scale output
current is:

I

FS

OUT

= 32 ×

Reference Current

Using the internal reference, this can also be expressed
as:

I

FS

OUT

= 38.4 ÷

R

EXT

On the evaluation board, R9 and R10 are the two exter­nal resistors that define the full-scale current.

An external reference can also be used simply by driving
the REFIO pin on the dual DAC (TP36) with an external
reference. The input impedance of the REFIO pin is very
high, minimizing any loading of the external reference.
However, because some references behave poorly
when driving capacitive loads, the bypass capacitor on

–4–

REV. 0