Analog Devices AN502 Application Notes
AN-502
a
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com
Designing a Superheterodyne Receiver Using an IF Sampling Diversity Chipset
by Brad Brannon
Abstract: The paper introduces a chipset to simplify receiver design and puts forth a design example based on
GSM but can be extended to many open or closed air
interface. Advances in analog converter technology
now allow IF sampling which can greatly simplify receiver design. Advances in digital integrated circuits
also advance the state of the art in terms of digital tuning and filtering. Together these two chips can replace
many of the cumbersome stages of a traditional analog
receiver with predictable and reliable performance.
The superheterodyne receiver is still a workhorse in receiver technology. It has served its duty faithfully for
many years now. However new technologies in receiver
component designs are offering to extend the possibilities into the digital age.
A typical receiver design may consist of two or three
down conversions to provide the sensitivity and selectivity required of the individual receiver. With each
down conversion, a local oscillator, mixer and filter are
required. Each additional stage adds complexity, cost
and difficulty of manufacture.
sacrificing performance? Perhaps the real question is
can performance be enhanced. One solution is to digitize the analog signals and do the processing in a DSP.
Once in the digital domain, many creative and proprietary processes can take place to enhance and add
value, while eliminating many of the manufacturing
problems (alignment and component yield) that often
increase the cost of manufacturing and reduce margins.
Already, it is common practice to use an analog-todigital converter to form the detector and a DSP (digital
signal processor) to process the data. However, this
does not reduce the cost or complexity of the design (to
digitize the baseband), it simply adds flexibility. What is
needed is an analog to digital converter that can digitize
closer to the antenna. Sampling at the antenna is not
realistic since some amount of band select and filtering
must occur prior to the ADC to minimize adjacent channel issues. However, sampling at the first IF is practical.
FILTER &
LNA
FILTER &
LNA
ADC DSP
FILTER
&
LNA
LO
FILTER
&
LNA
LO
FILTER
&
LNA
LO
DETECTOR
PROCESS
Figure 1. Typical Receiver Block Diagram
As shown above in the block diagram, receiver technology can be “straight forward”, however, implementation and manufacture can be another story.
There are several key issues that must be addressed. Of
course, the issues of noise and intercept point are always of concern when it comes to receiver design.
However, in moderate and high volume applications,
questions about assembly and test begin to arise. It is
one thing to build one in the lab, but it is a completely
different story to build many in production. With three
local oscillators, mixers and IF strips, alignment can be
a real issue, even with automated tools. To keep
manufacturing cost low, several of these analog stages
must be eliminated, but how can this be done without
LO
Figure 2. Digital Receiver Block Diagram
IF SAMPLING
Recent advances in converter technology have allowed
data converters to faithfully sample analog signals as
high as several hundred MHz. Sample rates need only
be as high as twice the signal bandwidth to keep the
Nyquist principle. Since most air interface standards
are less than a few MHz wide, sample rates in the tens of
MHz are required, eliminating the need for extremely
fast sample rates in radio design. Thus allowing for low
cost digitizers.
One such analog to digital converter (ADC) that performs this function is the AD6600. The AD6600 can
digitize up to 20 MSPS and sample analog signals up to
250 MHz with 60 dB spurious free dynamic range. In addition to high performance data conversion, this ADC
also includes gain control and dual inputs to facilitate
diversity applications.
AN-502
VINA
V
IN
B
AD6600
ATTEN
3
3 1
ATTEN
GND V
FLT+ FLT–
GAIN
BLOCK
CC
600V
PEAK
DETECTOR
ENC
TIMING
UNIT
T/H
CONTROL
ENC
RSSI
A_SEL
11-BIT
ADC
B_SEL
3
2x
CLOCK
OUT
11
DIGITAL
OUTPUTS
AB_OUT
RSSI
Figure 3. AD6600 Block Diagram
The block diagram above shows the details of the
AD6600 IF data converter. The AD6600 Dual Channel,
Gain Ranging ADC with RSSI (Receiver Signal Strength
Indicator) consists of three stages. The first consists of a
pair of 1 GHz phase compensated step attenuators followed by an output selection multiplexor. The second
stage is a wide input bandwidth 11-bit ADC based on the
AD9042, 12-bit 41 MSPS analog-to-digital converter. The
third stage is a high speed synchronous peak detector
and RSSI control interface. Together these on-chip systems form a high dynamic range IF sampling ADC. The
AD6600 is fabricated on an advanced bipolar integrated
circuit process.
The input attenuator consists of two identical inputs.
These dual inputs may be diversity channels, two independent IF signals or only one input may be used. The
attenuation factor is controlled through a range of 30 dB
in 6 dB steps by on-chip switches. The matching between the gain settings is better than 0.5 dB and maintains a bandwidth of almost 1 GHz so the phase delay is
small. Likewise the phase mismatches between different attenuator settings is very small, less than 0.2 degrees up to 200 MHz analog input. Additionally, the
input impedance does not change with attenuator settings so there is no AM to PM distortion.
Since one ADC serves both attenuator inputs, two control pins are provided to select which attenuator is connected to the ADC. The options allow one or both inputs
to be connected to the ADC. When both inputs are selected, the ADC alternates between the two on a clock by
clock basis. An output pin, AB_OUT, indicates which input is currently available on the digital output simplifying interface logic.
The on-chip RSSI (Receive Strength Signal Indicator)
controls the Input attenuator. The RSSI peak detector
function consists of a high-speed comparator bank. The
peak detector has five reference points, with each reference point being 6 dB lower than the previous one.
A regenerative positive feedback comparator is tied to
each point and referenced to full-scale of the A/D converter. Once one of the comparators is tripped it stays in
the state until it is reset by the falling edge of the encode.
The 5 comparator outputs are decoded into a 3-bit word
that is used to select the proper attenuation.
Six dB of digital hysteresis is used to eliminate level uncertainty at the threshold points due to noise and amplitude variations. The peak detector monitors both
positive and negative excursions of the input signal to
accurately track complex modulated signals.
The RSSI follows the IF envelop one clock cycle before
the conversion is made. During this time period, the
RSSI watches for the signal peaks and prior to digitization, the RSSI word is set to the appropriate attenuation
factor to prevent the ADC from overranging on the following conversion cycle. The RSSI always allows an extra 6 dB of ADC headroom to prevent clipping if the
signal power has increased unexpectedly. This is true
until the last attenuator is selected. Then the ADC will
clip in a normal manner. The RSSI word is made available to read via the RSSI pins. The 11-bit ADC output
forms the mantissa of a binary floating point word, while
the RSSI the exponent. This data can be interpreted in
several ways. The data can be converted in software by
using the following pseudo-code:
r0 = dm(rssi);
r2 = 5;
r0 = r2-r0;
r1 = dm(adc);(11 bits, MSB justified into DSP word)
rshift r1, r0; (arithmetic shift to extend the sign bit)
An ASIC/PLD can be used to convert the code to fixed
point or a digital preprocessor such as the AD6620 (to be
discussed later) can be used to convert the data. The resulting data can then be treated as a standard 16-bit
fixed point word.
Since the analog front end has a bandwidth of nearly
one-gigahertz and the ADC a bandwidth of 450 MHz, a
filter is required to bandwidth limit the wideband noise
out of the attenuator and MUX stage. This simple external LC filter is tuned to the chosen IF frequency and is
designed to settle quickly between clock cycles. To expedite settling between samples, an internal clamp circuit
is utilized to discharge the filter. This minimizes feed
through between inputs (cross talk) because of the natural time constant of the resonant network. Overall, the
AD6600 achieves 60 dB SFDR and 57 dB SNR with analog inputs up to 300 MHz, providing true IF sampling
with baseband performance. See Figure 4.
Once digitized, the signal would have to be processed.
With a typical sample rate of 20 MHz, data would stream
too fast for even the hottest DSP to do much with in
terms of filtering, much less process the data for user
–2–
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information. Therefore, some preprocessing of the data
must occur. With a sample rate of 20 MHz, the data
bandwidth would be 10 MHz, much more than is needed
for most air interfaces. Therefore, one thing that preprocessing should achieve is to reduce the data bandwidth
as well as the data rate. Thus in addition to the ADC
(analog-to-digital converter) a DSP preprocessor is
required.
0
–12
–24
–36
–48
–60
dB
–72
–84
–96
–108
–120
0
FFT PERFORMANCE AT 250MHz A
1/4 3/8
IN
1/21/8
Figure 4. AD6600 FFT with 250 MHz Analog Input
DIGITAL PREPROCESSING
As shown in the diagram below, the AD6620 performs
many functions. First it functions as a quadrature demodulator, separating the I and Q signals for later processing. The CIC (cascaded integrator comb) filters
provide data rate decimation and low pass filtering.
Overall decimation rates can be programmed from 1 (inclusive) to over 8192. The RAM Coefficient Filter, a sum
of product design, provides programmable filter performance, covering a wide range of designs.
REAL,
DUAL REAL,
OR
COMPLEX
INPUTS
COMPLEX
NCO
I
Q
–SINCOS
2
CIC
FILTER
EXTERNAL
SYNC
CIRCUITRY
I
Q
CIC
FILTER
5
I
Q
JTAG
PORT
RAM
COEF
FILTER
I
OUTPUT
FORMAT
Q
mP OR
SERIAL
CONTROL
SERIAL
OR
PARALLEL
OUTPUTS
Figure 5. AD6620 Block Diagram
The numerically controlled oscillator (NCO) provides
spurious performance to better than –105 dBc. This ultra
clean digital local oscillator is mixed with the digitized
input through 18-bit multipliers. As shown in the spectral plot below of the NCO, spurious performance is hidden well in the 16-bit noise floor shown below.
Interstage precision is maintained at 18 bits while individual stages use much higher precision to prevent artifacts due to truncation. Data out of the AD6620 can be
delivered to the DSP through either a standard serial interface or through a parallel interface as a memory
mapped address device. Data can be delivered in 16-,
24- or 32-bit precision.
0
–12
–24
–36
–48
–60
–72
dB
–84
–96
–108
–120
–132
–144
0
1/8TH SCALE NCO PERFORMANCE
1/4 3/8
Figure 6. AD6620 NCO Spurious Performance at 1/8th
the Clock Rate
DIVERSITY CHIPSET
The AD6600 and AD6620 form the heart of a chipset for
IF sampling and processing. Between the two chips,
AGC, digitizing, data rate reduction and channel filtering
are performed. The benefits from this pair are immense.
First, the integration level allows reduced system size
and power reduction. This is achieved through the elimination of analog IF stages along with their respective
components. Second, alignment time is greatly reduced. Since filters and oscillators are now digitally
implemented there is no need to adjust them at the
point of manufacture.
MAIN
INPUT
DIVERSITY
INPUT
ENCODE
AD6600
2x CLK
A/B OUT
3 RSSI BITS
11 DATA BITS
CLK
A/B
E[2..0]
IN[15..5]
AD6620
SCLK
SDFS
Figure 7. AD6600/AD6620 Diversity Receiver Chipset
Aside from the figures of merit mentioned above, the
chipset also features a seamless interchip interface. The
interchip connections are point to point and are designed for single layer wiring. Additionally, the serial
output port of the AD6620 wires directly to a number of
industry standard DSPs including the ADSP-21xx and
ADSP-210x families.
The Diversity Chipset is applicable for many different air
interfaces including narrow band FM, IS-136, CDMA,
GSM and many others. The use of such a chipset requires many of the traditional techniques in receiver design as well as some new considerations. However, the
end result is a more economical solution capable of
much more than a traditional analog receiver.
GSM and the Diversity Chipset
The remainder of this report focuses on a design analysis of one such design. The chosen example is GSM because it is one of the most technically challenging in
terms of selectivity. The analysis shown can just as
–3–
SDI
SDO
1/21/8
SCLK
SDO
SDI
SDFS
DSP
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easily be applied to any of the other standards and have
already been implemented. The front end is traditionally
referred to as the “radio” and consists of the antenna
connection through the ADC.
This report reviews the RF performance requirements in
terms of the Diversity Chipset. Throughout this writing,
certain assumptions about the RF section, ADC noise
and process gains (to be explained later) are made. The
basis of this work is the GSM specification for 900 MHz
as proposed by ETSI recommendation 05.05. Since
variations in receiver design exist, many possible designs solutions exist, this being but one. Many options
exist in terms of sample rate, decimation and digital signal processing that change the receivers ability to deal
with noise. In fact, the post ADC processing (DSP) determines much of the total receiver performance, and as a
result, represents much of the proprietary information
surrounding many manufacturers total receiver design.
Block Diagram
The following diagram is the one analyzed and will form
the core discussion from this point forward. Various advantages will be discussed to many of the options.
The design consists of one RF strip and 1 IF strip. The RF
section has a net gain of only about 3 dB, considering
the filter losses and mixer conversion loss. As with traditional receiver designs, most of the gain is in the IF strip
where filters have improved selectivity sufficiently to
prevent overdrive from off channel signals (adjacent
channel rejection). This forms a single analog down conversion with a second down conversion being performed digitally by the AD6620.
In the front end, the LNA is in front of the mixer. This
arrangement minimizes noise figure because the lossy
element is behind a gain block. Another possibilities is
that the mixer could be ahead of the LNA which maximizes intermodulation performance, although, as seen
later in the analysis, meeting spurious performance is
not too difficult with the amplifier ahead of the mixer.
However, with the mixer ahead of the amplifier, receiver
noise figure is insufficient to meet sensitivity requirements due to the insertion loss of the mixer.
After the mixer and band pass filter is a fixed gain
amp. This amplifier is working with relatively small signals and has no difficulty with intermodulation performance. The bulk of the IF gain is located between the
two SAW filters. This allows adjacent signals to be attenuated prior to amplification, which improves the intermodulation performance. The last component in the
analog chain is the second SAW filter. This effectively
eliminates harmonics of the amplifier chain prior to
digitization.
The first amplifier between the SAWs could be a variable gain amp as shown. This is not used for AGC purposes but instead to remove variation in component
values either from lot to lot, or over temperature. Tolerances in insertion loss can be removed as a system calibration by setting the gain of this amplifier. Insertion
losses of filters, mixers and amplifiers often worsen as
temperature increases. The gain of this amplifier could
be configured to increase with temperature to compensate for reduced conversion efficiency as a function of
temperature.
Total RF and IF conversion gain is 35 dB to 40 dB. With a
maximum input signal of –13 dBm, this would overdrive
the ADC. The last IF amplifier should be a limit or clipping amplifier to prevent this. This does not adversely
effect performance since the input signal is phase
modulated. Adaptive equalization requires amplitude
information, however at the point where the signal is so
large as to overdrive the data converter, equalization is
no longer necessary. The demodulation/equalization
process will still recover the signal.
Total receiver dynamic range is derived from the RF/IF
processing above, plus the 30 dB of gain ranging provided by the AD6600 as well as the 11-bit ADC incorporated in the AD6600.
RF Filtering
The purpose of the helical (preselect or band select) filter is to block out of band signals from entering the RF
stages of the receiver. In a typical base station, this filter
could consist of the bandwidth characteristics of the antenna, the RF trap or coupler (to keep Tx out of the Rx),
and the broad band pass filter. As seen below, this filter
should exhibit the lowest insertion loss possible, because receiver NF is directly (1 dB per dB) related to insertion loss at the front of the chain. High performance
receivers would likely integrate a low loss microstrip filter directly on the PCB to minimize loss in this stage, especially 1800 MHz and 1900 MHz applications. This filter
may also be a helical or dielectric filter, which is used to
perform band filtering. This filter ensures that following
stages are not disrupted by any remaining out of band
signals, including the base station transmit signals. The
filters can be designed specifically to block the transmit
side as in TOKO part numbers 6DFSC and 6DFSD.
HELICAL
FILTER
–2dB
G = 13dB
NF = 2.6dB
G = 6.3dB
BANDPASS
LOSS 2dB
SAW #1
G = –5dB
G = 15dB
NF = 3.8dB
G = 1168dB
Figure 8. Signal Path Details
–4–
G = 16dB
SAW #2
G = –5dB
AD6600
ADC
AD6620
DDC
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