ANALOG DEVICES ADXRS450 Service Manual
High Performance,
V
Data Sheet
FEATURES
Complete rate gyroscope on a single chip
±300°/sec angular rate sensing
High vibration rejection over a wide frequency range
Excellent 25°/hour null offset stability
Internally temperature compensated
2000 g powered shock survivability
SPI digital output with 16-bit data-word
Low noise and low power
3.3 V and 5 V operation
−40°C to +105°C operation
Ultrasmall, light, and RoHS compliant
Two package options
Low cost SOIC_CAV package for yaw rate (Z-axis) response
Innovative ceramic vertical mount package, which can be
oriented for pitch, roll, or yaw response
APPLICATIONS
Rotation sensing medical applications
Rotation sensing industrial and instrumentation
High performance platform stabilization
Digital Output Gyroscope
ADXRS450
GENERAL DESCRIPTION
The ADXRS450 is an angular rate sensor (gyroscope) intended
for industrial, medical, instrumentation, stabilization, and other
high performance applications. An advanced, differential, quad
sensor design rejects the influence of linear acceleration, enabling
the ADXRS450 to operate in exceedingly harsh environments
where shock and vibration are present.
The ADXRS450 uses an internal, continuous self-test architecture. The integrity of the electromechanical system is checked
by applying a high frequency electrostatic force to the sense
structure to generate a rate signal that can be differentiated from
the baseband rate data and internally analyzed.
The ADXRS450 is capable of sensing angular rate of up to
±300°/sec. Angular rate data is presented as a 16-bit word, as
part of a 32-bit SPI message.
The ADXRS450 is available in a cavity plastic 16-lead SOIC
(SOIC_CAV) and an SMT-compatible vertical mount package
(LCC_V), and is capable of operating across both a wide voltage
range (3.3 V to 5 V) and temperature range (−40°C to +105°C).
Z-AXIS ANGUL AR
RATE SENSOR
HV DRIVE
PHASE-
LOCKED
LOOP
BAND-PASS
FILTER
Q DAQ
P DAQ
X
CP5
HIGH VOLT AGE
GENERATION
CLOCK
DIVIDER
AMPLITUDE
DETECT
ADC 12
FUNCTIONAL BLOCK DIAGRAM
ADXRS450
ALU
DECIMATION
FILTER
TEMPERATURE
Figure 1.
CALIBRATIO N
FAULT
DETECTIO N
EEPROM
DEMOD
Q FILTER
ST
CONTROL
REGISTERS/MEMORY
LDO
REGULATOR
SPI
INTERFACE
P
DD
DV
DD
AV
DD
MOSI
MISO
SCLK
CS
DV
SS
P
SS
AV
SS
08952-001
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
ADXRS450 Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
Rate Sensitive Axis ....................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Continuous Self-Test.................................................................... 9
Applications Information .............................................................. 10
Calibrated Performance............................................................. 10
Mechanical Considerations for Mounting.............................. 10
Applications Circuits ................................................................. 10
ADXRS450 Signal Chain Timing............................................. 10
SPI Communication Protocol....................................................... 12
Command/Response ................................................................. 12
SPI Communications Characteristics...................................... 13
SPI Applications ......................................................................... 14
SPI Rate Data Format..................................................................... 19
Memory Map and Registers.......................................................... 20
Memory Map .............................................................................. 20
Memory Register Definitions ................................................... 21
Package Orientation and Layout Information............................ 23
Package Marking Codes ............................................................ 25
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 27
REVISION HISTORY
12/11—Rev. A to Rev. B
Changes to the Rate Sensitive Axis Section .................................. 4
Changes to Figure 5.......................................................................... 6
Changes to Figure 28...................................................................... 23
Deleted Figure 31, Renumbered Sequentially ............................ 24
Changes to Back Side Terminals Notation, Figure 34 ............... 26
6/11—Rev. 0 to Rev. A
Changes to Ordering Guide.......................................................... 28
1/11—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet ADXRS450
SPECIFICATIONS
Specification conditions @ TA = T
Table 1.
Parameter Test Conditions/Comments Symbol Min Typ Max Unit
MEASUREMENT RANGE Full-scale range FSR ±300 ±400 °/sec
SENSITIVITY See Figure 2
Nominal Sensitivity 80 LSB/°/sec
Sensitivity Tolerance ±3 %
Nonlinearity1 Best fit straight line 0.05 0.25 % FSR rms
Cross Axis Sensitivity2 ±3 %
NULL
Null Accuracy ±3 °/sec
NOISE PERFORMANCE
Rate Noise Density TA = 25°C 0.015 °/sec/√Hz
LOW-PASS FILTER
Cut-Off (−3 dB) Frequency f0/200, see Figure 6 fLP 80 Hz
Group Delay3 f = 0 Hz tLP 3.25 4 4.75 ms
SHOCK AND VIBRATION IMMUNITY
Sensitivity to Linear Acceleration DC to 5 kHz 0.03 °/sec/g
Vibration Rectification 0.003 °/sec/g2
SELF TEST See Continuous Self-Test section
Magnitude 2559 LSB
Fault Register Threshold Compared to LOCST data 2239 2879 LSB
Sensor Data Status Threshold Compared to LOCST data 1279 3839 LSB
Frequency f0/32 fST 500 Hz
ST Low-Pass Filter
−3 dB Frequency f0/800, see Figure 7 2 Hz
Group Delay3 52 64 76 ms
SPI COMMUNICATIONS
Clock Frequency 8.08 MHz
Voltage Input High
Voltage Input Low
Output Voltage Low MISO, current = 3 mA 0.5 V
Output Voltage High MISO, current = −2 mA PDD − 0.5 V
Pull-Up Current
MEMORY REGISTERS See the Memory Register
Temperature Sensor
Value at 45°C 0 LSB
Scale Factor 5 LSB/°C
Quad, ST, Rate, DNC Registers
Scale Factor 80 LSB/°/sec
POWER SUPPLY
Supply Voltage PDD 3.15 5.25 V
Quiescent Supply Current IDD 6.0 10.0 mA
Turn-On Time Power on to 0.5°/sec of final 100 ms
TEMPERATURE RANGE Independent of package type T
1
Maximum limit is guaranteed through Analog Devices, Inc., characterization.
2
Cross axis sensitivity specification does not include effects due to device mounting on a printed circuit board (PCB).
3
Minimum and maximum limits are guaranteed by design.
MIN
to T
, PDD = 5 V, angular rate = 0°/sec, bandwidth = 80 Hz ±1 g, continuous self-test on.
MAX
CS
MOSI,
MOSI,
CS
CS
, SCLK
CS
, SCLK
, PDD = 3.3 V, CS = 0.75 × PDD
, PDD = 5 V, CS = 0.75 × PDD
Definitions section
0.85 × P
−0.3 P
PDD + 0.3 V
DD
× 0.15 V
DD
50 200 µA
70 300 µA
, T
−40 +105 °C
MIN
MAX
Rev. B | Page 3 of 28
ADXRS450 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Acceleration (Any Axis, 0.5 ms)
Unpowered 2000 g
Powered 2000 g
Supply Voltage (PDD) −0.3 V to +6.0 V
Output Short-Circuit Duration (Any Pin to
Indefinite
Ground)
Temperature Range
Operating
LCC_V Package −40°C to +125°C
SOIC_CAV Package −40°C to +125°C
Storage
LCC_V Package −65°C to +150°C
SOIC_CAV Package −40°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, for a device
soldered in a printed circuit board (PCB) for surface-mount
packages.
Table 3. Thermal Resistance
Package Type θJA θ
16-Lead SOIC_CAV 191.5 25 °C/W
14-Lead Ceramic LCC_V 185.5 23 °C/W
Unit
JC
RATE SENSITIVE AXIS
The ADXRS450 is available in two package options. The
SOIC_CAV package configuration is for applications that
require a z-axis (yaw) rate sensing device.
The vertical mount package (LCC_V) option is for applications
that require rate sensing in the axes parallel to the plane of the
PCB (pitch and roll). See Figure 2 for details.
RATE
AXIS
+
16
RATE
SOIC PACKAGE
9
Figure 2. Rate Signal Increases with Clockwise Rotation
AXIS
Z-AXIS
+
LCC_V PACKAGE
08952-002
The LCC_V package has terminals on two faces; however, the
terminals on the back side are for internal evaluation only and
should not be used in the end application. The terminals on the
bottom of the package incorporate metallization bumps that
ensure a minimum solder thickness for improved solder joint
reliability. These bumps are not present on the back side
terminals and, therefore, poor solder joint reliability can be
encountered if used in the end application. See Figure 34 in the
Outline Dimensions section for a schematic of the LCC_V
package.
ESD CAUTION
Rev. B | Page 4 of 28
Data Sheet ADXRS450
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DV
RSVD
RSVD
CS
MISO
P
P
VX
DD
DD
SS
1
2
3
ADXRS450
4
TOP VIEW
(Not to Scale)
5
6
7
8
16
SCLK
15
MOSI
14
AV
DD
13
DV
SS
12
RSVD
11
AV
SS
10
RSVD
9
CP5
08952-003
Figure 3. SOIC_CAV Pin Configuration
Table 4. 14-Lead SOIC_CAV Pin Function Descriptions
Pin No. Mnemonic Description
1 DVDD Digital Regulated Voltage. See Figure 21 for the applications circuit diagram.
2 RSVD Reserved. This pin must be connected to DVSS.
3 RSVD Reserved. This pin must be connected to DVSS.
4
CS
Chip Select.
5 MISO Master In/Slave Out.
6 PDD Supply Voltage.
7 PSS Switching Regulator Ground.
8 VX High Voltage Switching Node. See Figure 21 for the applications circuit diagram.
9 CP5 High Voltage Supply. See Figure 21 for the applications circuit diagram.
10 RSVD Reserved. This pin must be connected to DVSS.
11 AVSS Analog Ground.
12 RSVD Reserved. This pin must be connected to DVSS.
13 DVSS Digital Signal Ground.
14 AVDD Analog Regulated Voltage. See Figure 21 for the applications circuit diagram.
15 MOSI Master Out/Slave In.
16 SCLK SPI Clock.
Rev. B | Page 5 of 28
ADXRS450 Data Sheet
PDDPSSMOSI
14 13 12 11 10 9 8
1234567
SS
AV
DVSSCS
DD
DD
AV
MISO
DV
TOP VIEW
(Not to Scale)
VX
RSVD
CP5
SCLK
RSVD
08952-005
Figure 4. LCC_V Pin Configuration
CP5
RSVD
SCLK
DVDDMISO
VX
CS
DV
RSVD
NOTES
1. THE LCC_V PACKAGE HAS TW O TERMI NALS ON T WO FACES; HOWEVER, THE TERMINALS O N THE BACK
SIDE ARE FO R INTERNAL E VALUATIO N ONLY AND SHO ULD NOT BE USED IN THE END APP LICATION. THE
TERMINALS ON THE BOT TOM OF THE PACKAGE INCORPORAT E METALL IZATI ON BUMPS THAT ENSURE A
MINIMUM SOLDER THI CKNESS FOR I MPROVED SOLDER JOI NT RELI ABILIT Y. THESE BUMPS ARE NOT
PRESENT ON T HE BACK SIDE T ERMINALS AND, THEREFO RE, POOR SOLDER JOINT RELI ABILIT Y CAN BE
ENCOUNTERED IF USED IN T HE END APPLICATION. S EE THE OUT LINE DIM ENSIONS S ECTION F OR A
SCHEMATIC O F THE LCC_V PACKAGE.
(Not to Scale)
Figure 5. LCC_V Pin Configuration, Horizontal Layout
SS
AVDDAV
1234567
141312111098
SS
SS
DD
P
P
MOSI
08952-037
Table 5. 14-Lead LCC_V Pin Function Descriptions
Pin No. Mnemonic Description
1 AVSS Analog Ground.
2 AVDD Analog Regulated Voltage. See Figure 22 for the applications circuit diagram.
3 MISO Master In/Slave Out.
4 DVDD Digital Regulated Voltage. See Figure 22 for the applications circuit diagram.
5 SCLK SPI Clock.
6 CP5 High Voltage Supply. See Figure 22 for the applications circuit diagram.
7 RSVD Reserved. This pin must be connected to DVSS.
8 RSVD Reserved. This pin must be connected to DVSS.
9 VX High Voltage Switching Node. See Figure 22 for the applications circuit diagram.
10
CS
Chip Select.
11 DVSS Digital Signal Ground.
12 MOSI Master Out/Slave In.
13 PSS Switching Regulator Ground.
14 PDD Supply Voltage.
Rev. B | Page 6 of 28
Data Sheet ADXRS450
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.18
0.16
0.14
0.12
0.10
0.08
% OF POPULATION
0.06
0.04
0.02
0
–1.6
–2.0
–1.2
–0.8
NULL ERROR (° /sec)
0
–0.4
0.8
0.4
1.6
1.2
2.0
08952-006
Figure 6. SOIC_CAV Null Error @ 25°C
0.30
0.40
0.35
0.30
0.25
0.20
0.15
% OF POPULATION
0.10
0.05
0
–2.0 –1.6 –1.2 –0.8 –0.4 0 2.01.61.20.80.4
NULL ERROR (° /sec)
Figure 9. LCC_V Null Error @ 25°C
0.30
08952-009
0.25
0.20
0.15
0.10
% OF POPULATION
0.05
0
–2.5
–2.0
–1.5
–1.0
–3.0
–0.5
NULL DRIFT ERROR (°/ sec)
Figure 7. SOIC_CAV Null Drift over Temperature
0.25
0.20
0.15
0.10
% OF POPULATION
0.05
0.25
0.20
0.15
0.10
% OF POPULATION
0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
08952-007
0
–2.5
–2.0
–3.0
–1.5
NULL DRIFT ERROR (° /sec)
0
–0.5
–1.0
1.5
1.0
–0.5
3.0
2.5
2.0
08952-010
Figure 10. LCC_V Null Drift over Temperature
0.25
0.20
0.15
0.10
% OF POPULATION
0.05
0
–3.0
–2.5
–2.0
–1.5
CHANGE IN SENSITIVITY (%)
0
–1.0
–0.5
Figure 8. SOIC_CAV Sensitivity Error @ 25°C
0.5
1.0
1.5
2.0
2.5
3.0
08952-008
0
–3.0
–2.5
–2.0
–1.5
CHANGE IN SENSITIVITY (%)
0
0.5
1.0
1.5
2.0
2.5
–1.0
–0.5
3.0
08952-029
Figure 11. LCC_V Sensitivity Error @ 25°C
Rev. B | Page 7 of 28
ADXRS450 Data Sheet
R
0.30
0.25
0.20
0.15
0.10
% OF POPULATION
0.05
0
–3
–2
–1
DRIFT (%)
1
0
Figure 12. SOIC_CAV Sensitivity Drift over Temperature
1
0.1
3
2
08952-030
0.45
0.40
0.35
0.30
0.25
0.20
0.15
% OF POPULATION
0.10
0.05
0
–3
–2
CHANGE IN SENSITIVITY (%)
0
–1
Figure 15. LCC_V Sensitivity Drift over Temperature
40
30
20
10
DUT1
DUT2
DUT AVERAGE (°/s)
REF
3
2
1
08952-033
60
50
40
30
/Hz)
2
(g
0.01
0.001
065k4k3k2k1k
VIBRATION F REQUENCY (Hz)
k
Figure 13. Typical Response to Random Vibration, 15 g rms, 50 Hz to 5 kHz
3
N = 16
2
1
0
–1
NULL OUTPUT ERRO
–2
–3
–50 1109070503010–10–30
DUT TEMPERATURE (°C)
Figure 14. Null Output over Temperature, Device Soldered on PCB
0
–10
GYRO OUTPUT (°/s)
–20
–30
–40
0.1 0.15 0.20 0.25 0.30 0.35 0.40
08952-031
TIME (sec)
20
10
0
–10
–20
INPUT ACCELERAT ION (g)
08952-034
Figure 16. Typical Shock Response
3
N = 16
2
1
0
–1
–2
SENSITIVITY OVER TEMPERATURE ERROR
–3
08952-032
–50 1109070503010–10–30
DUT TEMPERATURE (°C)
08952-035
Figure 17. Sensitivity over Temperature, Device Soldered to PCB
Rev. B | Page 8 of 28
Data Sheet ADXRS450
S
THEORY OF OPERATION
The ADXRS450 operates on the principle of a resonator gyroscope. A simplified version of one of four polysilicon sensing
structures is shown in Figure 18. Each sensing structure contains
a dither frame that is electrostatically driven to resonance. This
produces the necessary velocity element to produce a Coriolis
force when experiencing angular rate. In the SOIC_CAV package,
the ADXRS450 is designed to sense a z-axis (yaw) angular rate;
whereas the vertical mount package (LCC_V) orients the device
such that it can sense pitch or roll angular rate on the same PCB.
When the sensing structure is exposed to angular rate, the
resulting Coriolis force couples into an outer sense frame,
which contains movable fingers that are placed between fixed
pickoff fingers. This forms a capacitive pickoff structure that
senses Coriolis motion. The resulting signal is fed to a series of
gain and demodulation stages that produce the electrical rate
signal output. The quad sensor design rejects linear and angular
acceleration, including external g-forces and vibration. This is
achieved by mechanically coupling the four sensing structures
such that external g-forces appear as common-mode signals
that can be removed by the fully differential architecture
implemented in the ADXRS450.
CONTINUOUS SELF-TEST
The ADXRS450 gyroscope uses a complete electromechanical
self-test. An electrostatic force is applied to the gyroscope frame,
resulting in a deflection of the capacitive sense fingers. This
deflection is exactly equivalent to deflection that occurs as a
result of external rate input. The output from the beam structure is
processed by the same signal chain as a true rate output signal,
providing complete coverage of the electrical and mechanical
components.
The electromechanical self-test is performed continuously during
operation at a rate higher than the output bandwidth of the
device. The self-test routine generates equivalent positive and
negative rate deflections. This information can then be filtered
with no overall effect on the demodulated rate output.
RATE SIGNAL WITH
CONTINUOUS S ELF TES T SIGNAL .
X
Y
Z
Figure 18. Simplified Gyroscope Sensing Structure
The resonator requires 22.5 V (typical) for operation. Because
only 5 V is typically available in most applications, a switching
regulator is included on chip.
ELF TEST AMPLIT UDE. INTERNAL LY
COMPARED TO THE SPECIFICATION
TABLE LI MITS.
Figure 19. Continuous Self-Test Demodulation
LOW FRE QUENCY RATE I NFORMATI ON.
The difference amplitude between the positive and negative
self-test deflections is filtered to 2 Hz, and it is continuously
monitored and compared to hardcoded self-test limits. If the
measured amplitude exceeds these limits (listed in Tab l e 1 ), one
of two error conditions asserts depending on the magnitude of
self-test error. For less severe self-test error magnitudes, the CST
bit of the fault register is asserted; however, the status bits (ST[1:0])
in the sensor data response remain set to 0b01 for valid sensor
data. For more severe self-test errors, the CST bit of the fault register is asserted, and the status bits (ST[1:0]) in the sensor data
response are set to 0b00 for invalid sensor data. Ta b le 1 lists the
08952-011
thresholds for both of these failure conditions. If desired, the user
can access the self-test information by issuing a read command to
the self-test memory register (Address 0x04). For more information about error reporting, see the SPI Communication Protocol
section.
08952-012
Rev. B | Page 9 of 28
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