ANALOG DEVICES ADV 7391 BCPZ Datasheet

Low Power, Chip Scale,

Data Sheet

ADV7390/ADV7391/ADV7392/ADV7393

FEATURES

3 high quality, 10-bit video DACs

16× (216 MHz) DAC oversampling for SD 8× (216 MHz) DAC oversampling for ED 4× (297 MHz) DAC oversampling for HD 37 mA maximum DAC output current

Multiformat video input support

4:2:2 YCrCb (SD, ED, and HD) 4:4:4 RGB (SD)

Multiformat video output support

Composite (CVBS) and S-Video (Y-C) Component YPrPb (SD, ED, and HD) Component RGB (SD, ED, and HD)

Lead frame chip scale package (LFCSP) options

32-lead, 5 mm × 5 mm LFCSP 40-lead, 6 mm × 6 mm LFCSP

Wafer level chip scale package (WLCSP) option

30-ball, 5 × 6 WLCSP with single DAC output

Advanced power management

Patented content-dependent low power DAC operation Automatic cable detection and DAC power-down Individual DAC on/off control Sleep mode with minimal power consumption

74.25 MHz 8-/10-/16-bit high definition input support Compliant with SMPTE 274M (1080i), 296M (720p),

and 240M (1035i) EIA/CEA-861B compliance support NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz) Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant Copy generation management system (CGMS) Closed captioning and wide screen signaling (WSS) Integrated subcarrier locking to external video source Complete on-chip video timing generator On-chip test pattern generation Programmable features

Luma and chroma filter responses Vertical blanking interval (VBI) Subcarrier frequency (f Luma delay

High definition (HD) programmable features

(720p/1080i/1035i) 4× oversampling (297 MHz) Internal test pattern generator

Color and black bar, hatch, flat field/frame

Fully programmable YCrCb to RGB matrix

Rev. I Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

) and phase

SC

10-Bit SD/HD Video Encoder

Gamma correction Programmable adaptive filter control Programmable sharpness filter control CGMS (720p/1080i) and CGMS Type B (720p/1080i) Dual data rate (DDR) input support

Enhanced definition (ED) programmable features

(525p/625p) 8× oversampling (216 MHz output) Internal test pattern generator

Black bar, hatch, flat field/frame Individual Y and PrPb output delay Gamma correction Programmable adaptive filter control Fully programmable YCrCb to RGB matrix Undershoot limiter Macrovision Rev 1.2 (525p/625p) (ADV7390/ADV7392 only) CGMS (525p/625p) and CGMS Type B (525p) Dual data rate (DDR) input support

Standard definition (SD) programmable features

16× oversampling (216 MHz) Internal test pattern generator

Color and black bar Controlled edge rates for start and end of active video Individual Y and PrPb output delay Undershoot limiter Gamma correction Digital noise reduction (DNR) Multiple chroma and luma filters Luma-SSAF filter with programmable gain/attenuation PrPb SSAF Separate pedestal control on component and

composite/S-Video output VCR FF/RW sync mode Macrovision Rev 7.1.L1 (ADV7390/ADV7392 only) Copy generation management system (CGMS) Wide screen signaling (WSS) Closed captioning

Serial MPU interface with I

2.7 V or 3.3 V analog operation

1.8 V digital operation

1.8 V or 3.3 V I/O operation Temperature range: −40°C to +85°C W Grade automotive range: −40°C to +105°C Qualified for automotive applications

Technical Support www.analog.com

2

C compatibility

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

REVISION HISTORY

2/15—Rev. H to Rev. I

Changed ADV739x to ADV7390/ADV7391/ADV7392/

ADV7393 ............................................................................. Universal

Changes to Figure 19 ...................................................................... 19

Changes to Table 15 ........................................................................ 20

Changes to Figure 144 ..................................................................104

Updated Outline Dimensions ......................................................106

Changes to Ordering Guide .........................................................107

9/14—Rev. G to Rev. H

Changed Storage Temperature Range from −60°C to +100°C to

−60°C to +150°C; Table 13 ............................................................. 18

Updated Figure 145, Outline Dimensions .................................105

Changes to Ordering Guide .........................................................107

2/13—Rev. F to Rev. G

Change to Features Section .............................................................. 1

Changes to Table 14 ........................................................................ 18

Changes to Figure 62 ...................................................................... 48

Changes to Ordering Guide .........................................................107

11/12—Rev. E to Rev. F

Updated Outline Dimensions ......................................................105

Changes to Ordering Guide .........................................................107

2/12—Rev. D to Rev. E

Changes to Table 1 ............................................................................ 5

Changes to Digital Input/Output Specifications—

1.8 V Section ...................................................................................... 8

Changes to Table 15 ........................................................................ 21

Changes to Table 20 ........................................................................ 31

Changes to Table 23 ........................................................................ 34

Changes to Table 28 ........................................................................ 39

Changes to 16-Bit 4:4:4 RGB Mode Section ................................ 47

Added External Sync Polarity Section .......................................... 51

SD/ED/HD RGB Output Levels ................................................ 88

SD Output Plots .......................................................................... 89

Video Standards .............................................................................. 90

Configuration Scripts ..................................................................... 92

Standard Definition .................................................................... 92

Enhanced Definition .................................................................. 99

High Definition ......................................................................... 101

ADV7390/ADV7391/ADV7392/ADV7393 Evaluation Board .... 104

Outline Dimensions ...................................................................... 105

Ordering Guide ......................................................................... 107

Automotive Products ................................................................ 107

Deleted ED/HD Nonstandard Timing Mode Section, Figure 63,

and Table 41, Renumbered Sequentially ...................................... 51

Changed SD Subcarrier Frequency Lock, Subcarrier Phase Reset, and Timing Reset Section to SD Subcarrier Frequency

Lock Section ..................................................................................... 52

Deleted Subaddress 0x84, Bits[2:1] Section, Timing Reset (TR) Mode Section, Subcarrier Phase Reset (SCR) Mode Section,

Figure 64, and Figure 65 ................................................................. 52

Changes to Ordering Guide ......................................................... 121

11/11—Rev. C to Rev. D

Changes to Features Section ............................................................ 1

Updated Outline Dimensions and changes to Automotive

Products Section ............................................................................ 107

9/11—Rev. B to Rev. C

Changes to MPU Port Description Section ................................. 26

Changes to Ordering Guide ......................................................... 107

7/10—Rev. A to Rev. B

Changes to Features Section ............................................................ 1

Change to Applications Section ...................................................... 5

Changes to General Description ..................................................... 5

Added Table 2, Renumbered Subsequent Tables .......................... 5

Added Figure 2, Renumbered Subsequent Figures ...................... 6

Changes to Full-Drive Output Current Parameter, Table 5 ........ 7

Changes to Table 14 ........................................................................ 18

Added Figure 20 .............................................................................. 19

Changes to Table 15 ........................................................................ 19

Changes to ADV7390/ADV7391 Input Configuration

Section .............................................................................................. 45

Added Additional Layout Considerations for the WLCSP

Package Section ............................................................................... 71

Added Figure 97 .............................................................................. 73

Changes to Configuration Scripts Section ................................... 92

Changes to Subaddress 0x00, Table 66 ......................................... 93

Rev. I | Page 3 of 107

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

Changes to Subaddress 0x00, Table 66 ........................................ 93

Changes to Subaddress 0x00, Table 80 ........................................ 95

Changes to Subaddress 0x00, Table 8 3 ........................................ 95

Changes to Subaddress 0x00, Table 9 7 ........................................ 98

Updated Outline Dimensions, Added Figure 150 .................... 106

Changes to Ordering Guide ........................................................ 106

3/09—Rev. 0 to Rev. A

Changes to Features Section............................................................ 1

Deleted Detailed Features Section, Changes to Table 1 ............... 4

Changes to Figure 1, Added Figure 2 ............................................. 5

Changes to Table 2, Input Clock Specifications Section, and

Analog Output Specifications Section ........................................... 6

Changes to Digital Input/Output Specifications—3.3 V Section

and Table 5 ......................................................................................... 7

Added Digital Input/Output Specifications—1.8 V Section and

Table 6 ................................................................................................ 7

Changes to MPU Port Timing Specifications Section,

Default Conditions ........................................................................... 7

Changes to Digital Timing Specifications—3.3 V Section and

Table 8 ................................................................................................ 8

Added Digital Timing Specifications—1.8 V Section and

Table 9 ................................................................................................ 9

Added Video Performance Specifications Section, Default

Conditions ....................................................................................... 10

Added Power Specifications Section, Default Conditions ........ 10

Changes to Table 11 ........................................................................ 10

Changes to Figure 16 ...................................................................... 16

Changes to Table 12 ........................................................................ 17

Changes to Table 14, Pin 19 and Pin 1 Descriptions ................. 18

Changes to MPU Port Description Section ................................ 25

Changes to I

2

C Operation Section ............................................... 25

Added Table 15 ............................................................................... 25

Changes to Table 17 ........................................................................ 28

Changes to Table 19, 0x30 Bit Description ................................. 30

Changes to Table 27 ....................................................................... 37

Changes to Table 29, 0x8B Bit Description ................................. 39

Changes to Table 30 ....................................................................... 40

Changes to Table 3 1 ....................................................................... 41

Added Table 32 ............................................................................... 42

Renamed Features Section to Design Features Section ............. 48

Changes to ED/HD Nonstandard Timing Mode Section ......... 48

Added the HD Interlace External

HSYNC

and

VSYNC

Considerations Section .................................................................. 49

Changes to SD Subcarrier Frequency Lock, Subcarrier Reset,

and Timing Reset Section.............................................................. 49

Changes to Subaddress 0x8C to Subaddress 0x8F Section ....... 51

Changes to Programming the F

Section ................................... 51

SC

Changes to Subaddress 0x82, Bit 4 Section ................................. 51

Added SD Manual CSC Matrix Adjust Feature Section ............ 54

Added Table 47 ............................................................................... 55

Changes to Subaddress 0x9C to Subaddress 0x9F Section ....... 56

Changes to Subaddress 0xBA Section.......................................... 56

Added Sleep Mode Section ........................................................... 65

Changes to Pixel and Control Port Readback Section .............. 66

Changes to Reset Mechanisms Section ....................................... 66

Added SD Teletext Insertion Section ........................................... 66

Added Figure 87 ............................................................................. 67

Added Figure 88 ............................................................................. 68

Changes to DAC Configuration Section ..................................... 68

Added Unused Pins Section .......................................................... 68

Changes to Power Supply Sequencing Section ........................... 70

Changes to Internal Test Pattern Generation Section ............... 77

Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option

(Subaddress 0x8A = XXXXX000) Section .................................. 78

10/06—Revision 0: Initial Version

Rev. I | Page 4 of 107

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393

720 × 480

I

29.97

27

ITU-R 720 × 576

P

50

27

ITU-R BT.1358

1280 × 720

P

60, 50, 30,

74.25

SMPTE 296M 1920 × 1080

I

29.97

74.1758

SMPTE 274M

640 × 480

I

29.97

24.54

NTSC Square

APPLICATIONS

Mobile handsets Digital still cameras Portable media and DVD players Portable game consoles Digital camcorders Set-top box (STB) Automotive infotainment (ADV7392 and ADV7393 only)

GENERAL DESCRIPTION

The ADV7390/ADV7391/ADV7392/ADV7393 are a family of high speed, digital-to-analog video encoders on single monolithic chips. Three 2.7 V/3.3 V, 10-bit video DACs (a single DAC for the WLCSP package) provide support for composite (CVBS), S-Video (Y-C), or component (YPrPb/RGB) analog outputs in either standard definition (SD) or high definition (HD) video formats. The single DAC WLCSP package supports CVBS (NTSC and PAL) output only in SD resolution (see Ta b l e 2).

Optimized for low power operation, occupying a minimal footprint, and requiring few external components, these encoders are ideally suited to portable and power-sensitive applications requiring TV-out functionality. Cable detection and DAC autopower-down features ensure that power consumption is kept to a minimum.

The ADV7390/ADV7391 have an 8-bit video input port that supports SD video formats over an SDR interface and HD video formats over a DDR interface. The ADV7392/ADV7393 have a 16-bit video input port that can be configured in a variety of ways. SD RGB input is supported.

All members of the family support embedded EAV/SAV timing codes, external video synchronization signals, and the I communication protocol. Tabl e 1 and Table 2 list the video standards directly supported by the ADV7390/ADV7391/

ADV7392/ADV7393 fa m i ly.

2

C® and

Table 1. Standards Directly Supported by the LFCSP Packages

Active Resolution I/P

720 × 240 P 59.94 27 720 × 288 P 50 27

720 × 576 I 25 27 ITU-R

640 × 480 I 29.97 24.54 NTSC Square

768 × 576 I 25 29.5 PAL Square

720 × 483 P 59.94 27 SMPTE 293M 720 × 483 P 59.94 27 BTA T-1004 720 × 483 P 59.94 27 ITU-R BT.1358

720 × 483 P 59.94 27 ITU-R BT.1362 720 × 576 P 50 27 ITU-R BT.1362 1920 × 1035 I 30 74.25 SMPTE 240M 1920 × 1035 I 29.97 74.1758 SMPTE 240M

1280 × 720 P 23.97,

1920 × 1080 I 30, 25 74.25 SMPTE 274M

1920 × 1080 P 30, 25, 24 74.25 SMPTE 274M 1920 × 1080 P 23.98, 29.97 74.1758 SMPTE 274M 1920 × 1080 P 24 74.25 ITU-R BT.709-5

1

I = interlaced, P = progressive.

Frame

1

Rate (Hz)

25, 24

59.94, 29.97

Clock Input (MHz) Standard

BT.601/656

Pixel

74.1758 SMPTE 296M

Table 2. Standards Directly Supported by the WLCSP Package

I/P

Frame

1

Rate (Hz)

Active Resolution

720 × 480 I 29.97 27 ITU-R

720 × 576 I 25 27 ITU-R

Clock Input (MHz)

Standard

BT.601/656

Pixel

768 × 576 I 25 29.5 PAL Square

Pixel

1

I = interlaced, P = progressive.

Rev. I | Page 5 of 107

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

FUNCTIONAL BLOCK DIAGRAMS

DGND (2)

(2)

V

DD

SCL SDA ALSB SFL

AGND

V

AA

GND_IO

V

DD_IO

8-BIT SD

8-BIT ED/HD

OR

VBI DATA SERVICE

INSERTION

SDR/DDR

SD/ED/HD INPUT

4:2:2 TO 4:4:4

DEINTERLEAVE

ASYNC

BYPASS

YCrCb

HDTV TEST

PATTERN

GENERATOR

POWER

MANAGEMENT

CONTROL

RESET HSYNC VSYNC

VIDEO TI MING GENERATO R

MPU PORT

ADD

SYNC

ADD

BURST

PROGRAMMABLE

ED/HD FILTERS

SHARPNESS AND

ADAPTIVE FILTER

CONTROL

PROGRAM MABLE

LUMINANCE

FILTER

PROGRAM MABLE

CHROMI NANCE

FILTER

SUBCARRIER FREQ UENCY

LOCK (SFL)

YCrCb

TO

RGB

SIN/COS DDS

BLOCK

YCbCr

TO

RGB MATRI X

16×/4× OVERSAMPLI NG PLL

CLKIN PV

ADV7390/ADV7391

16×

FILTER

16×

FILTER

MULTIPLEXER

4×

FILTER

PGND EXT_LF COMP

DD

11-BIT DAC 1

11-BIT DAC 2

11-BIT DAC 3

REFERENCE AND CABLE

DETECT

DAC 1

DAC 2

DAC 3

R

SET

06234-001

Figure 1. ADV7390/ADV7391 (32-Lead LFCSP)

(2)

GND_IO

V

DD_IO

8-BIT SD

DGND (2)

VBI DATA SERVI CE

INSERTION

SDR/DDR

SD INPUT

4:2:2 TO 4:4:4

DEINTERLEAVE

V

DD

SCL SDA ALSB

MPU PORT

ADD

SYNC

ADD

BURST

PROGRAM MABLE

LUMINANCE

FILTER

PROGRAM MABLE

CHROMI NANCE

FILTER

SFL

SUBCARRIER FREQ UENCY

LOCK (SFL )

SIN/CO S DDS

BLOCK

16×

FILTER

16×

FILTER

ADV7390BCBZ

MULTIPLEXER

AGND

11-BIT DAC 1

V

AA

DAC 1

POWER

MANAGEMENT

CONTROL

RESET HSYNC VSYNC

VIDEO TIMING GENERATOR

16× OVERSAMPLI NG PLL

CLKIN PV

PGND EXT_LF COMP

DD

REFERENCE AND CABLE

DETECT

R

SET

06234-146

Figure 2. ADV7390BCBZ-A (30-Ball WLCSP)

AGND

12-BIT DAC 1

12-BIT DAC 2

12-BIT DAC 3

REFERENCE

AND CABLE

DETECT

V

AA

DAC 1

DAC 2

DAC 3

R

SET

06234-145

GND_IO

V

DD_IO

8-/10-/16-B IT SD

8-/10-/16-B IT ED/H D

OR

V

(2)

DGND (2)

VBI DATA SERVICE

INSERTION

SDR/DDR

SD/ED/HD INPUT

4:2:2 TO 4:4:4

DEINTERLEAVE

POWER

MANAGEM ENT

CONTROL

RESET HSYNC VSYNC

DD

RGB

TO

YCrCb

MATRIX

ASYNC

BYPASS

YCrCb

HDTV TEST

PATTERN

GENERATOR

VIDEO T IMI NG GENERA TOR

SCL SDA ALSB SFL

MPU PORT

ADD

SYNC

ADD

BURST

PROGRAMMABLE

ED/HD FILTERS

SHARPNESS AND

ADAPTIVE FILTER

CONTROL

Figure 3. ADV7392/ADV7393 (40-Lead LFCSP)

PROGRAMMABLE

LUMINANCE

FILTER

PROGRAMMABLE

CHROMI NANCE

FILTER

SUBCARRIER FREQ UENCY

LOCK (SFL)

YCrCb

TO

RGB

SIN/CO S DDS

BLOCK

YCbCr

TO

RGB MATRI X

16x/4x OVERSAMPLING PLL

CLKIN PV

PGND EXT_LF COM P

DD

ADV7392/ADV7393

16×

FILTER

16×

FILTER

MULTIPLEXER

4×

FILTER

Rev. I | Page 6 of 107

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393

DAC-to-DAC Matching

DAC 1, DAC 2, DAC 3

2.0 %

SPECIFICATIONS

POWER SUPPLY SPECIFICATIONS

All specifications T

Table 3.

Parameter Min Typ Max Unit

SUPPLY VOLTAGES

VDD 1.71 1.8 1.89 V V

1.71 3.3 3.63 V

DD_IO

PVDD 1.71 1.8 1.89 V VAA 2.6 3.3 3.465 V

POWER SUPPLY REJECTION RATIO 0.002 %/%

INPUT CLOCK SPECIFICATIONS

VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, V All specifications T

Table 4.

Parameter Conditions1 Min Typ Max Unit

f

SD/ED 27 MHz

CLKIN

ED (at 54 MHz) 54 MHz HD 74.25 MHz CLKIN High Time, t9 40 % of one clock cycle CLKIN Low Time, t10 40 % of one clock cycle CLKIN Peak-to-Peak Jitter Tolerance 2 ±ns

1

SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.

MIN

to T

(−40°C to +85°C), unless otherwise noted.

MAX

(−40°C to +85°C), unless otherwise noted.

MAX

= 1.71 V to 3.63 V.

DD_IO

ANALOG OUTPUT SPECIFICATIONS

VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, V All specifications T

MIN

to T

(−40°C to +85°C), unless otherwise noted.

MAX

Table 5.

Parameter Conditions Min Typ Max Unit

Full-Drive Output Current R

= 510 Ω, RL = 37.5 Ω 33 34.6 37 mA

SET

All DACs enabled R

= 510 Ω, RL = 37.5 Ω 31.5 33.5 37 mA

SET

DAC 1 enabled only1 Low-Drive Output Current R

= 4.12 kΩ, RL = 300 Ω 4.3 mA

SET

Output Compliance, VOC 0 1.4 V Output Capacitance, C

10 pF

OUT

Analog Output Delay2 6 ns DAC Analog Output Skew DAC 1, DAC 2, DAC 3 1 ns

1

The recommended method of bringing this value back to the ideal value is by adjusting Register 0x0B to the recommended value of 0x12.

2

Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.

= 1.71 V to 3.63 V.

DD_IO

Rev. I | Page 7 of 107

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

Parameter

Conditions

Min

Typ

Max

Unit

DIGITAL INPUT/OUTPUT SPECIFICATIONS—3.3 V

VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, V All specifications T

MIN

to T

(−40°C to +85°C), unless otherwise noted.

MAX

Table 6.

Parameter Conditions Min Typ Max Unit

Input High Voltage, VIH 2.0 V Input Low Voltage, VIL 0.8 V Input Leakage Current, IIN VIN = V

±10 µA

DD_IO

Input Capacitance, CIN 4 pF Output High Voltage, VOH I Output Low Voltage, VOL I

= 400 µA 2.4 V

SOURCE

= 3.2 mA 0.4 V

SINK

Three-State Leakage Current VIN = 0.4 V, 2.4 V ±1 µA Three-State Output Capacitance 4 pF

DIGITAL INPUT/OUTPUT SPECIFICATIONS—1.8 V

When V V

= 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, V

DD

All specifications T

Table 7.

Parameter Conditions Min Typ Max Unit

Input High Voltage, VIH 0.7 V Input Low Voltage, VIL 0.3 V Input Capacitance, CIN 4 pF Output High Voltage, VOH I Output Low Voltage, VOL I Three-State Output Capacitance 4 pF

is set to 1.8 V, all the digital video inputs and control inputs, such as I2C, HS, and VS, should use 1.8 V levels.

DD_IO

MIN

to T

(−40°C to +85°C), unless otherwise noted.

MAX

= 400 µA V

SOURCE

= 3.2 mA 0.4 V

SINK

= 2.97 V to 3.63 V.

DD_IO

= 1.71 V to 1.89 V.

DD_IO

V

DD_IO

– 0.4 V

DD_IO

V

MPU PORT TIMING SPECIFICATIONS

VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, V All specifications T

MIN

to T

(−40°C to +85°C), unless otherwise noted.

MAX

Table 8.

MPU PORT, I2C MODE1 See Figure 17

SCL Frequency 0 400 kHz SCL High Pulse Width, t1 0.6 µs SCL Low Pulse Width, t2 1.3 µs Hold Time (Start Condition), t3 0.6 µs Setup Time (Start Condition), t4 0.6 µs Data Setup Time, t5 100 ns SDA, SCL Rise Time, t6 300 ns SDA, SCL Fall Time, t7 300 ns Setup Time (Stop Condition), t8 0.6 µs

1

Guaranteed by characterization.

= 1.71 V to 3.63 V.

DD_IO

Rev. I | Page 8 of 107

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393

ED/HD-SDR or ED/HD-DDR

2.3

ns

Component Outputs (2×)

SD oversampling disabled

78 Clock cycles

DIGITAL TIMING SPECIFICATIONS—3.3 V

VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, V All specifications T

MIN

to T

(−40°C to +85°C), unless otherwise noted.

MAX

Table 9.

Parameter Conditions1 Min Typ Max Unit

VIDEO DATA AND VIDEO CONTROL PORT

Data Input Setup Time, t

4

SD 2.1 ns

11

2, 3

ED/HD-SDR 2.3 ns ED/HD-DDR 2.3 ns ED (at 54 MHz) 1.7 ns Data Input Hold Time, t

4

SD 1.0 ns

12

ED/HD-SDR 1.1 ns ED/HD-DDR 1.1 ns ED (at 54 MHz) 1.0 ns Control Input Setup Time, t

4

SD 2.1 ns

11

= 2.97 V to 3.63 V.

DD_IO

ED (at 54 MHz) 1.7 ns Control Input Hold Time, t

4

SD 1.0 ns

12

ED/HD-SDR or ED/HD-DDR 1.1 ns ED (at 54 MHz) 1.0 ns Control Output Access Time, t

4

SD 12 ns

13

ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 10 ns Control Output Hold Time, t

4

SD 4.0 ns

14

ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 3.5 ns

PIPELINE DELAY5

SD1

CVBS/Y-C Outputs (2×) SD oversampling disabled 68 Clock cycles CVBS/Y-C Outputs (8×) SD oversampling enabled 79 Clock cycles CVBS/Y-C Outputs (16×) SD oversampling enabled 67 Clock cycles

Component Outputs (8×) SD oversampling enabled 69 Clock cycles Component Outputs (16×) SD oversampling enabled 84 Clock cycles

ED1

Component Outputs (1×) ED oversampling disabled 41 Clock cycles Component Outputs (4×) ED oversampling enabled 49 Clock cycles Component Outputs (8×) ED oversampling enabled 46 Clock cycles

HD1

Component Outputs (1×) HD oversampling disabled 40 Clock cycles Component Outputs (2×) HD oversampling enabled 42 Clock cycles Component Outputs (4×) HD oversampling enabled 44 Clock cycles

CONTROL

RESET

Low Time 100 ns

RESET

1

SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.

2

Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.

3

Video control:

4

Guaranteed by characterization.

5

Guaranteed by design.

HSYNC

and

VSYNC

.

Rev. I | Page 9 of 107

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

ED/HD-SDR or ED/HD-DDR

1.2

ns

Component Outputs (2×)

SD oversampling disabled

78 Clock cycles

DIGITAL TIMING SPECIFICATIONS—1.8 V

VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, V All specifications T

MIN

to T

(−40°C to +85°C), unless otherwise noted.

MAX

Table 10.

Parameter Conditions1 Min Typ Max Unit

VIDEO DATA AND VIDEO CONTROL PORT

Data Input Setup Time, t

4

SD 1.4 ns

11

2, 3

ED/HD-SDR 1.9 ns ED/HD-DDR 1.9 ns ED (at 54 MHz) 1.6 ns Data Input Hold Time, t

4

SD 1.4 ns

12

ED/HD-SDR 1.5 ns ED/HD-DDR 1.5 ns ED (at 54 MHz) 1.3 ns Control Input Setup Time, t

4

SD 1.4 ns

11

= 1.71 V to 1.89 V.

DD_IO

ED (at 54 MHz) 1.0 ns Control Input Hold Time, t

4

SD 1.4 ns

12

ED/HD-SDR or ED/HD-DDR 1.0 ns ED (at 54 MHz) 1.0 ns Control Output Access Time, t

4

SD 13 ns

13

ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 12 ns Control Output Hold Time, t

4

SD 4.0 ns

14

ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 5.0 ns

PIPELINE DELAY5

SD1

CVBS/Y-C Outputs (2×) SD oversampling disabled 68 Clock cycles CVBS/Y-C Outputs (8×) SD oversampling enabled 79 Clock cycles CVBS/Y-C Outputs (16×) SD oversampling enabled 67 Clock cycles

Component Outputs (8×) SD oversampling enabled 69 Clock cycles Component Outputs (16×) SD oversampling enabled 84 Clock cycles

ED1

Component Outputs (1×) ED oversampling disabled 41 Clock cycles Component Outputs (4×) ED oversampling enabled 49 Clock cycles Component Outputs (8×) ED oversampling enabled 46 Clock cycles

HD1

Component Outputs (1×) HD oversampling disabled 40 Clock cycles Component Outputs (2×) HD oversampling enabled 42 Clock cycles Component Outputs (4×) HD oversampling enabled 44 Clock cycles

CONTROL

RESET

Low Time 100 ns

RESET

1

SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.

2

Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.

3

Video control:

4

Guaranteed by characterization.

5

Guaranteed by design.

HSYNC

and

VSYNC

.

Rev. I | Page 10 of 107

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393

Signal-to-Noise Ratio (SNR)3

Luma ramp

58 dB

IDD

5 µA

VIDEO PERFORMANCE SPECIFICATIONS

VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, V

Table 11.

Parameter Conditions Min Typ Max Unit

STATIC PERFORMANCE

Resolution 10 Bits Integral Nonlinearity (INL)1 R Differential Nonlinearity (DNL)

1, 2

R

STANDARD DEFINTION (SD) MODE

Luminance Nonlinearity 0.5 ±% Differential Gain NTSC 0.5 % Differential Phase NTSC 0.6 Degrees

Flat field full bandwidth 75 dB

ENHANCED DEFINITION (ED) MODE

Luma Bandwidth 12.5 MHz Chroma Bandwidth 5.8 MHz

HIGH DEFINITION (HD) MODE

Luma Bandwidth 30.0 MHz Chroma Bandwidth 13.75 MHz

1

Measured on DAC 1, DAC 2, and DAC 3.

2

Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal

step value. For −ve DNL, the actual step value lies below the ideal step value.

3

Measured on the ADV7392/ADV7393 operating in 10-bit input mode.

= 3.3 V, TA = +25°C.

DD_IO

= 510 Ω, RL = 37.5 Ω 0.5 LSBs

SET

= 510 Ω, RL = 37.5 Ω 0.5 LSBs

SET

POWER SPECIFICATIONS

VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, V

Table 12.

Parameter Conditions Min Typ Max Unit

NORMAL POWER MODE

3

I

SD (16× oversampling enabled), CVBS (only one DAC turned on) 33 mA

DD

1, 2

SD (16× oversampling enabled), YPrPb (three DACs turned on) 68 mA ED (8× oversampling enabled)4 59 mA HD (4× oversampling enabled)4 81 101 mA I

1 10 mA

DD_IO

5

I

One DAC enabled 50 mA

AA

All DACs enabled 122 151 mA I

4 10 mA

PLL

SLEEP MODE

IAA 0.3 µA I

0.2 µA

DD_IO

I

0.1 µA

PLL

1

R

= 510 Ω (all DACs operating in full-drive mode).

SET

2

75% color bar test pattern applied to pixel data pins.

3

IDD is the continuous current required to drive the digital core.

4

Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.

5

IAA is the total current required to supply all DACs.

= 3.3 V, TA = +25°C.

DD_IO

Rev. I | Page 11 of 107

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

t

9

CLKIN

t

10

CONTRO

L

OUTPUTS

HSYNC VSYNC

Cr2

Cb2Cr0Cb0

IN MASTER/SLA

VE MODE

IN SL

AVE MODE

Y0

Y1 Y2

PIXE

L PORT

CONTROL

INPUTS

t

12

t

1

t

13

t

14

06234-002

IN MASTER/SLAVE MODE

IN SLAVE MODE

CLKIN

CONTROL

OUTPUTS

t

9t10

Cr2

Cb2

Cr0Cb0

Y0

Y1

Y2

Y3

t

12

t

14

t

11

t

13

HSYNC VSYNC

CONTROL

INPUTS

PIXEL PORT

06234-003

• t

TIMING DIAGRAMS

The following abbreviations are used in Figure 4 to Figure 11:

• t

= clock high time

9

• t

= clock low time

10

• t

= data setup time

11

• t

= data hold time

12

= control output access time

13

• t

= control output hold time

14

In addition, see Table 35 for the ADV7390/ADV7391 pixel port input configuration and Tabl e 36 for the ADV7392/ADV7393 pixel port input configuration.

Figure 4. SD Input, 8-/10-Bit 4:2:2 YCrCb, Input Mode 000

Figure 5. SD Input, 16-Bit 4:2:2 YCrCb, Input Mode 000

Rev. I | Page 12 of 107

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393

CONTROL

OUTPUTS

t

9t10

t

11

G0 G1 G2

B0 B1 B2

R0 R1 R2

t

12

t

14

t

13

PIXEL PORT

CLKIN

HSYNC VSYNC

CONTROL

INPUTS

06234-004

CONTROL

OUTPUTS

PIXEL PORT

Y0 Y1 Y2

Y3 Y4 Y5

Cr4Cb4C

r2C

b2Cr0Cb0

CLKIN

t9t

10

t

12

t

11

t

14

t

13

HSYNC VSYNC

CONTROL

INPUTS

06234-005

CLKIN*

CONTROL

OUTPUTS

Cr2Y2

Cb2

Y1Cr0

Y0Cb0

t

9

t

10

t

12

t

11

t

12

t

11

t

14

t

13

PIXEL PORT

HSYNC

VSYNC

CONTRO

L

INPUTS

*LUMA/CHROM A CLOCK RELATIONSHIP CAN BE INVERTED USI NG SUBADDRESS 0x01, BITS 1 AND 2.

06234-006

Figure 6. SD Input, 16-Bit 4:4:4 RGB, Input Mode 000

Figure 7. ED/HD-SDR Input, 16-Bit 4:2:2 YCrCb, Input Mode 001

Figure 8. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (

Rev. I | Page 13 of 107

HSYNC/VSYNC

), Input Mode 010

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

CONTROL

OUTPUTS

PIXEL PORT

*LUMA/CHROM A CLOCK RELATIONSHIP CAN BE INVERTED USI NG SUBADDRESS 0x01, BITS 1 AND 2.

Y1Cr0Y0Cb0XY00003FF

CLKIN*

t

9

t

10

t

12

t

11

t

12

t

11

t

14

t

13

06234-007

CLKIN

CONTROL

OUTPUTS

Y1Cr0Y0Cb0 Cr2

Y2

Cb2

t9t

10

t

12

t

11

t

13

t

14

PIXEL PORT

HSYNC

VSYNC

CONTROL

INPUTS

06234-008

CLKIN

CONTROL

OUTPUTS

3FF

00 00 XY Cb0

Y0 Cr0 Y1

PIXEL PORT

t

11

t

12

t

10

t

9

t

14

t

13

06234-009

Figure 9. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010

Figure 10. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (

HSYNC/VSYNC

), Input Mode 111

Figure 11. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 111

Rev. I | Page 14 of 107

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393

Y0 Y1

Y2

Y3

a

Cr2

Cb2Cr0Cb0

b

Y OUTPUT

HSYNC

VSYNC

a = AS PER RELEV ANT STANDARD. b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME

EQUAL TO THE PIPELINE DELAY.

PIXEL PORT

PIXEL PORT*

06234-010

Cb0 Y0

Cr0 Y1

a

a(MIN) = 244 CL OCK CYCLES FOR 525p. a(MIN) = 264 CL OCK CYCLES FOR 625p.

b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY.

HSYNC

VSYNC

b

Y OUTPUT

PIXEL PORT

06234-011

Figure 12. ED-SDR, 16-Bit 4:2:2 YCrCb (

HSYNC/VSYNC

) Input Timing Diagram

Figure 13. ED-DDR, 8-/10-Bit 4:2:2 YCrCb (

HSYNC/VSYNC

Rev. I | Page 15 of 107

) Input Timing Diagram

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

Y0 Y1

Y2

Y3

a

Cr2Cb2

Cr0

Cb0

b

Y OUTPUT

HSYNC

VSYNC

a = AS PER RELEV ANT STANDARD. b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT

AFTER A TIME EQUAL TO THE PIPELINE DELAY.

PIXEL PORT

06234-012

PIXEL PORT

Cb0 Y0

Cr0 Y1

a

HSYNC

VSYNC

b

Y OUTPUT

a = AS PER RELEV ANT STANDARD. b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING

SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT

AFTER A TIME EQUAL TO THE PIPELINE DELAY.

06234-013

Figure 14. HD-SDR, 16-Bit 4:2:2 YCrCb (

HSYNC/VSYNC

) Input Timing Diagram

Figure 15. HD-DDR, 8-/10-Bit 4:2:2 YCrCb (

HSYNC/VSYNC

) Input Timing Diagram

Rev. I | Page 16 of 107

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393

Cb Y

Cr

Y

PAL = 264 CLOCK CY CLES NTSC = 244 CLOCK CY CLES

PIXEL PORT

VSYNC

HSYNC

06234-014

t

3

t

3

t

4

t

7

t

8

t

5

SDA

SCL

t

1

t

2

t

6

06234-015

Figure 16. SD Input Timing Diagram (Timing Mode 1)

Figure 17. MPU Port Timing Diagram (I

2

C Mode)

Rev. I | Page 17 of 107

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

VDD to DGND

−0.3 V to +2.3 V

32-Lead LFCSP

27

32

1.2

°C/W

40-Lead LFCSP

26

32 1 °C/W

ABSOLUTE MAXIMUM RATINGS

Table 13.

Parameter1 Rating

VAA to AGND −0.3 V to +3.9 V

PVDD to PGND −0.3 V to +2.3 V V

to GND_IO −0.3 V to +3.9 V

DD_IO

AGND to DGND −0.3 V to +0.3 V AGND to PGND −0.3 V to +0.3 V AGND to GND_IO −0.3 V to +0.3 V DGND to PGND −0.3 V to +0.3 V DGND to GND_IO −0.3 V to +0.3 V PGND to GND_IO −0.3 V to +0.3 V Digital Input Voltage to GND_IO −0.3 V to V

DD_IO

+ 0.3 V Analog Outputs to AGND −0.3 V to VAA Max CLKIN Input Frequency 80 MHz Storage Temperature Range (tS) −60°C to +150°C Junction Temperature (tJ) 150°C Lead Temperature (Soldering, 10 sec) 260°C

1

Analog output short circuit to any power supply or common can be of an

indefinite duration.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

JA

2

θ

1

JC-TOP

3

θ

JC-BOTTOM

4

Unit

Table 14. Thermal Resistance

Package Type θ

30-Ball WLCSP 35 1 N/A °C/W

1

Values are based on a JEDEC 4-layer test board.

2

With the exposed metal paddle on the underside of the LFCSP soldered to

the PCB ground.

3

This is the thermal resistance of the junction to the top of the package.

4

This is the thermal resistance of the junction to the bottom of the package.

The ADV7390/ADV7391/ADV7392/ADV7393 are RoHScompliant, Pb-free products. The lead finish is 100% pure Sn electroplate. The device is suitable for Pb-free applications up to 255°C (±5°C) IR reflow (JEDEC STD-20).

The ADV7390/ADV7391/ADV7392/ADV7393 are backward compatible with conventional SnPb soldering processes. The electroplated Sn coating can be soldered with SnPb solder pastes at conventional reflow temperatures of 220°C to 235°C.

ESD CAUTION

Rev. I | Page 18 of 107

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393

O

R

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

D

DD

HSYNC

V

SFL

VSYNC

DGN

P0

GND_IO

P1

31

30

32

V

1

DD_IO

V

DD

NOTES

1. THE EXPOSED PAD SHOULD BE CONNECTED TO ANALO G GROUND (AG ND).

2P2 3P3 4P4 5 6DGND 7P5 8P6

PIN 1 INDICATOR

ADV7390/

ADV7391

TOP VIEW

(Not to Scale)

9

11

10

P7

SDA

ALSB

Figure 18. ADV7390/ADV7391 Pin Configuration

P1

P2

P3

GND_I

40

39

38

37

V

1

DD_IO

2

P4

3

V

DGND

P10

P5

4

P6

5

P7

6

DD

7 8

P8

9

P9

10

ADV7392/

ADV7393

TOP VIEW

(Not to Scale)

25

26

27

28

29

R

24

SET

23 COMP 22 DAC 1 21 DAC 2 20 DAC 3 19 V

AA

18 AGND 17 PV

DD

12

13

14

15

16

SCL

PGND

CLKIN

XT_LF

RESET

E

06234-017

DD

P0

DGND

SFL

VSYNC

V

HSYNC

31

32

36

35

34

33

R

30

SET

29

COMP

28

DAC 1 DAC 2

27

DAC 3

26

V

25

AA

AGND

24

PV

23

DD

EXT_LF

22

PGND

21

BALL A1 CORNE

234

1

R

A

SET

DAC1

B

V

C

AA

D

AGND

E

PV

DD

PGND SDA SCL CLKIN P7

F

V

HSYNC

VSYNC

COMP DGND P3 P4

GND_IO

EXT_LF

DD

SFL P1 P2

RESET

ALSB P5 P6

TOP VIEW

(BALL SIDE DOWN)

Not to Scal e

VDDDGND

5

V

P0

DD_IO

Figure 20. ADV7390BCBZ-A Pin Configuration

06234-147

11

13

12

14

15

P11

P12

SCL

SDA

ALSB

NOTES

1. THE EXPOSED PAD SHOULD BE CONNECTED TO ANALOG GROUND (AG ND).

20

19

18

16

17

ET

P14

P13

P15

LKIN C

RES

6234-018

Figure 19. ADV7392/ADV7393 Pin Configuration

Table 15. Pin Function Descriptions

Pin No.1

ADV7390/ ADV7391

9 to 7, 4 to 2, 31, 30

N/A

ADV7392/ ADV7393

N/A

18 to 15, 11 to 8, 5 to 2, 39 to

ADV7390

WLCSP

F5, E5, E4, C5,

Mnemonic

P7 to P0 I

C4, B5, B4, A4 N/A P15 to P0 I

Input/ Output Description

8-Bit Pixel Port (P7 to P0). P0 is the LSB. See Table 35 for input modes (ADV7390/ADV7391).

16-Bit Pixel Port (P15 to P0). P0 is the LSB. See Table 36 for input modes (ADV7392/ADV7393).

37, 34

13 19 F4 CLKIN I

Pixel Clock Input for HD (74.25 MHz), ED or SD (27 MHz).

27 33 A2

HSYNC

I/O

Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD horizontal synchronization signal. See the External Horizontal and Vertical Synchronization Control section.

26 32 B2

VSYNC

I/O

Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control section.

25 31 B3 SFL I/O Subcarrier Frequency Lock (SFL) Input.

2

(27 MHz or 54 MHz),

Rev. I | Page 19 of 107

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

22, 21, 20

28, 27, 26

N/A

DAC 1, DAC 2,

O

DAC Outputs. Full-drive and low-drive capable DACs.

Pin No.1

ADV7390/ ADV7391

24 30 A1 R

ADV7392/ ADV7393

ADV7390

WLCSP

Mnemonic

I Controls the amplitudes of the DAC 1, DAC 2, and DAC 3

SET

23 29 C2 COMP O Compensation Pin. Connect a 2.2 nF capacitor from COMP

N/A N/A B1 DAC 1 O DAC Output. Full-drive and low-drive capable DAC

DAC 3 12 14 F3 SCL I I2C Clock Input. 11 13 F2 SDA I/O I2C Data Input/Output. 10 12 E3 ALSB I ALSB sets up the LSB3 of the MPU I2C address. 14 20 D3

I Resets the on-chip timing generator and sets the

RESET

19 25 C1 VAA P Analog Power Supply (2.7 V or 3.3 V). 5, 28 6, 35 A3, D4 VDD P Digital Power Supply (1.8 V). For dual-supply

1 1 A5 V

P Input/Output Digital Power Supply (1.8 V or 3.3 V).

DD_IO

17 23 E1 PVDD P PLL Power Supply (1.8 V). For dual-supply configurations,

16 22 E2 EXT_LF I External Loop Filter for the Internal PLL. 15 21 F1 PGND G PLL Ground Pin. 18 24 D1 AGND G Analog Ground Pin. 6, 29 7, 36 C3, D5 DGND G Digital Ground Pin. 32 40 D2 GND_IO G Input/Output Supply Ground Pin. EPAD G Exposed Pad. Connect to analog ground (AGND).

1

N/A means not applicable.

2

ED = enhanced definition = 525p and 625p.

3

LSB = least significant bit. In the ADV7390/ADV7392, setting the LSB to 0 sets the I2C address to 0xD4. Setting it to 1 sets the I2C address to 0xD6. In the

ADV7391/ADV7393, setting the LSB to 0 sets the I

2

C address to 0x54. Setting it to 1 sets the I2C address to 0x56.

Input/ Output Description

outputs. For full-drive operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from R AGND. For low-drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be connected from R AGND.

.

to V

AA

ADV7390/ADV7391/ADV7392/ADV7393 into its default

mode.

configurations, VDD can be connected to other 1.8 V supplies through a ferrite bead or suitable filtering.

PVDD can be connected to other 1.8 V supplies through a ferrite bead or suitable filtering.

SET

to

Rev. I | Page 20 of 107

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393

TYPICAL PERFORMANCE CHARACTERISTICS

ED Pr/Pb RESPONSE. LINEAR INT ERP FROM 4:2:2 TO 4:4:4

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

20020 40 60 80 100 120 140 160 1800

Figure 21. ED 8× Oversampling, PrPb Filter (Linear) Response

EDPr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

20020 40 60 80 100 120 140 16 0 1800

Figure 22. ED 8× Oversampling, PrPb Filter (SSAF™) Response

Y RESPONSE IN ED 8× OVERSAMPL ING MODE

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

20020 40 60 80 100 120 14 0 160 1800

Figure 23. ED 8× Oversampling, Y Filter Response

1.0

0.5

–0.5

–1.0

GAIN (dB)

–1.5

–2.0

–2.5

–3.0

06234-019

Figure 24. ED 8× Oversampling, Y Filter Response (Focus on Pass Band)

10

0

–10

–20

–30

–40

–50

GAIN (dB)

–60

–70

–80

–90

–100

06234-020

Figure 25. HD 4× Oversampling, PrPb (SSAF) Filter Response

–10

–20

–30

–40

–50

GAIN (dB)

–60

–70

–80

–90

–100

06234-021

Figure 26. HD 4× Oversampling, PrPb (SSAF) Filter Response

Y RESPONSE IN ED 8× OVERSAMPLING MODE

0

FREQUENCY (MHz)

HD Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

FREQUENCY (MHz)

(4:2:2 Input)

HD Pr/Pb RES PONSE. 4: 4:4 INPUT MODE

0

10 20 30 40 50 60 70 80 90 100 110 120 130 140

FREQUENCY (M Hz)

(4:4:4 Input)

122468100

06234-022

148.018.5 37.0 55. 5 74.0 92.5 111.0 129.50

06234-023

06234-024

Rev. I | Page 21 of 107

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

10

–10

–20

–30

–40

–50

GAIN (dB)

–60

–70

–80

–90

–100

3.0

1.5

–1.5

–3.0

–4.5

GAIN (dB)

–6.0

–7.5

–9.0

–10.5

–12.0

27.750 46.250

Figure 28. HD 4× Oversampling, Y Filter Response (Focus on Pass Band)

Y RESPONSE I N HD 4× OVERSAMPL ING MODE

0

FREQUENCY ( MHz)

Figure 27. HD 4× Oversampling, Y Filter Response

Y PASS BAND IN HD 4x OVERSAMPLING MODE

0

30.063 32.375 34.688 37.000 39.312 41. 625 43.937

FREQUENCY (MHz)

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

148.018.5 37.0 55. 5 74.0 92.5 111.0 129.50

06234-025

–70

FREQUENCY (MHz)

121086420

6234-028

Figure 30. SD PAL, Luma Low-Pass Filter Response

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

06234-026

FREQUENCY (MHz)

121086420

06234-029

Figure 31. SD NTSC, Luma Notch Filter Response

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

FREQUENCY (MHz)

Figure 29. SD NTSC, Luma Low-Pass Filter Response

121086420

6234-027

Rev. I | Page 22 of 107

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

FREQUENCY (MHz)

121086420

06234-030

Figure 32. SD PAL, Luma Notch Filter Response

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393

Y RESPONSE IN SD OVERSAMPLING MODE

0

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

0 20 40 60 80 100 120 140 160 180 200

FREQUENCY (MHz)

Figure 33. SD 16× Oversampling, Y Filter Response

06234-031

5

4

3

2

MAGNITUDE ( dB)

1

0

–1

0

234

1

FREQUENCY (MHz)

Figure 36. SD Luma SSAF Filter, Programmable Gain

5

6

7

06234-034

0

–10

–20

–30

–40

MAGNITUDE ( dB)

–50

–60

–70

FREQUENCY (MHz)

Figure 34. SD Luma SSAF Filter Response up to 12 MHz

4

2

0

–2

–4

–6

MAGNITUDE ( dB)

–8

–10

–12

1

23

FREQUE NCY (MHz )

4

5

Figure 35. SD Luma SSAF Filter, Programmable Responses

1

0

–1

–2

MAGNITUDE (dB)

–3

–4

–5

121086420

06234-032

0

234

1

FREQUENCY (MHz)

5

6

7

6234-035

Figure 37. SD Luma SSAF Filter, Programmable Attenuation

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

60

7

06234-033

–70

4

620

FREQUENCY (MHz)

8

12

10

06234-036

Figure 38. SD Luma CIF Low-Pass Filter Response

Rev. I | Page 23 of 107

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

0

–10

–20

–30

–40

MAGNITUDE ( dB)

–50

–60

–70

4

620

FREQUENCY (M Hz)

Figure 39. SD Luma QCIF Low-Pass Filter Response

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

0

–10

–20

–30

–40

MAGNITUDE ( dB)

–50

–60

8

10

12

06234-037

–70

4

620

FREQUENCY (MHz)

8

10

12

06234-040

Figure 42. SD Chroma 1.3 MHz Low-Pass Filter Response

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

4

620

FREQUENCY (M Hz)

8

Figure 40. SD Chroma 3.0 MHz Low-Pass Filter Response

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

4

620

FREQUENCY (M Hz)

8

Figure 41. SD Chroma 2.0 MHz Low-Pass Filter Response

–60

12

10

06234-038

–70

4

620

FREQUENCY (M Hz)

10

8

12

6234-041

Figure 43. SD Chroma 1.0 MHz Low-Pass Filter Response

0

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

12

10

06234-039

–70

4

620

FREQUENCY (MHz)

10

8

12

06234-042

Figure 44. SD Chroma 0.65 MHz Low-Pass Filter Response

Rev. I | Page 24 of 107

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393

FREQUENC

Y

(MHz)

0

12

MAGNITUDE (dB)

–10

–30

–50

–60

–70

–20

–40

10

8

4

6

20

06234-043

FREQUENCY (MHz)

0

12

MAGNITUDE (dB)

–10

–30

–50

–60

–70

–20

–40

10

8

4

620

06234-044

Figure 45. SD Chroma CIF Low-Pass Filter Response

Figure 46. SD Chroma QCIF Low-Pass Filter Response

Rev. I | Page 25 of 107

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

1

Read

0xD7

1 1 0 1

0 1 A1 X

READ/WRITE

CONTROL 0 WRITE

1 READ

06234-045

ADDRESS CONTROL

SET UP BY

ALSB

0 1

0

1

0

1

A1

X

READ/WRITE

CONTROL 0 WRITE

1 READ

06234-046

ADDRESS CONTROL

SET UP BY

ALSB

MPU PORT DESCRIPTION

Devices such as a microprocessor can communicate with the

ADV7390/ADV7391/ADV7392/ADV7393 through a 2-wire

2

serial (I port is configured for I

C-compatible) bus. After power-up or reset, the MPU

2

C operation.

I2C OPERATION

The ADV7390/ADV7391/ADV7392/ADV7393 support a 2wire serial (I multiple peripherals. This port operates in an open-drain configuration. Two wires, serial data (SDA) and serial clock (SCL), carry information between any device connected to the bus and the ADV7390/ADV7391/ADV7392/ADV7393. The slave address depends on the device (ADV7390, ADV7391,

ADV7392, or ADV7393), the operation (read or write), and the

state of the ALSB pin (0 or 1). See Table 16, Figure 47, and Figure 48. The LSB sets either a read or a write operation. Logic 1 corresponds to a read operation, and Logic 0 corresponds to a write operation. A1 is controlled by setting the ALSB pin of the

ADV7390/ADV7391/ADV7392/ADV7393 to Logic 0 or Logic 1.

Table 16. ADV7390/ADV7391/ADV7392/ADV7393 I Slave Addresses

Device ALSB Operation Slave Address

ADV7390

and

ADV7392

ADV7391

and

ADV7393

2

C-compatible) microprocessor bus driving

0 Write 0xD4 0 Read 0xD5 1 Write 0xD6

0 Write 0x54 0 Read 0x55 1 Write 0x56 1 Read 0x57

2

Figure 47. ADV7390/ADV7392 I

C Slave Address

2

C

The various devices on the bus use the following protocol. The master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream follows. All peripherals respond to the start condition and shift the next eight bits (7-bit address plus the R/

W

bit).

The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition occurs when the device monitors the SDA and SCL lines waiting for the start condition and the correct transmitted address. The R/

W

bit determines the direction of the data.

Logic 0 on the LSB of the first byte means that the master writes information to the peripheral. Logic 1 on the LSB of the first byte means that the master reads information from the peripheral.

The ADV7390/ADV7391/ADV7392/ADV7393 act as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/

W

bit. It interprets the first byte as the device address and the second byte as the starting subaddress. There is a subaddress autoincrement facility. This allows data to be written to or read from registers in ascending subaddress sequence starting at any valid subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all the registers.

Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCL high period, the user should issue only a start condition, a stop condition, or a stop condition followed by a start condition. If an invalid subaddress is issued by the user, the ADV7390/

ADV7391/ADV7392/ADV7393 do not issue an acknowledge

but returns to the idle condition. If the user uses the autoincrement method of addressing the encoder and exceeds the highest subaddress, the following actions are taken:

• In read mode, the highest subaddress register contents are

output until the master device issues a no acknowledge. This indicates the end of a read. A no acknowledge condition occurs when the SDA line is not pulled low on the ninth pulse.

• In write mode, the data for the invalid byte is not loaded

into any subaddress register, a no acknowledge is issued by the ADV7390/ADV7391/ADV7392/ADV7393, and the part returns to the idle condition.

Figure 48. ADV7391/ADV7393 I

2

C Slave Address

Rev. I | Page 26 of 107

Figure 49 shows an example of data transfer for a write sequence and the start and stop conditions. Figure 50 shows bus write and read sequences.

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393

SDA

SCL

1–7 8

START ADDR R/W ACK SUBADDRESS ACK DATA ACK STOP

9S1–7

Figure 49. I

9

8

2

C Data Transfer

1–7

8

P

9

06234-047

WRITE

SEQUENCE

READ

SEQUENCE

S SLAVE ADDR A(S ) SUBADDR A(S) DATA DATA A(S) P

LSB = 0

S SLAVE ADDR A(S) SUBADDR A(S) S SLAVE ADDR A(S) DATA DATAA(M) A(M) P

S = START BIT P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDG E BY MASTER

Figure 50. I

2

C Read and Write Sequence

A(S)

LSB = 1

A (S) = NO-ACKNOWLEDGE BY SLAVE A (M) = NO-ACKNOWLEDGE BY MASTER

06234-048

Rev. I | Page 27 of 107

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

mode off

1 1 0 Reserved.

REGISTER MAP ACCESS

A microprocessor can read from or write to all registers of the

ADV7390/ADV7391/ADV7392/ADV7393 via the MPU port,

except for registers that are specified as read-only or write-only registers.

The subaddress register determines the register accessed by the next read or write operation. All communication through the MPU port starts with an access to the subaddress register. A read/write operation is then performed from/to the target address, incrementing to the next address until the transaction is complete.

Table 17. Register 0x00

SR7 to Bit Number Register Reset SR0 Register Bit Description 7 6 5 4 3 2 1 0 Setting Value

0x00 Power

mode

Sleep mode. With this control enabled, the current consumption is reduced to µA level. All DACs and the internal PLL circuit are disabled. Registers can be read from and written to in sleep mode.

PLL and oversampling control. This control allows the internal PLL circuit to be powered down and the oversampling to be switched off.

DAC 3: power on/off. 0 DAC 3 off

DAC 2: power on/off. 0 DAC 2 off

DAC 1: power on/off. 0 DAC 1 off

Reserved. 0 0 0

REGISTER PROGRAMMING

Table 17 to Table 34 describe the functionality of each register. All registers can be read from as well as written to, unless otherwise stated.

SUBADDRESS REGISTER (SR7 TO SR0)

The subaddress register is an 8-bit write-only register. After the MPU port is accessed and a read/write operation is selected, the subaddress is set up. The subaddress register determines which register performs the next operation.

0 Sleep

1 Sleep

mode on 0 PLL on 1 PLL off

1 DAC 3 on

1 DAC 2 on

1 DAC 1 on

0x12

Table 18. Register 0x01 to Register 0x09

SR7 to Bit Number1 Reset SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value

0x01 Mode

select

Reserved. 0 0x00 DDR clock edge alignment

(used only for ED DDR modes)

Reserved 0 Input mode

(see Subaddress 0x30, Bits[7:3] for ED/HD standard selection)

Reserved 0

2

and HD

0 0 Chroma clocked in on rising clock edge and

0 1 Reserved. 1 0 Reserved. 1 1 Luma clocked in on rising clock edge and

0 0 0 SD input. 0 0 1 ED/HD-SDR input.3 0 1 0 ED/HD-DDR input. 0 1 1 Reserved. 1 0 0 Reserved. 1 0 1 Reserved.

1 1 1 ED (at 54 MHz) input.

luma clocked in on falling clock edge.

chroma clocked in on falling clock edge.

Rev. I | Page 28 of 107

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393

0 Default.

1 Enable manual CSC matrix adjust.

1

SR7 to Bit Number1 Reset SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value

0x02 Mode

Register 0

0x03 ED/HD

CSC Matrix 0

0x04 ED/HD

CSC Matrix 1

0x05 ED/HD

CSC Matrix 2

0x06 ED/HD

CSC Matrix 3

0x07 ED/HD

CSC Matrix 4

0x08 ED/HD

CSC Matrix 5

0x09 ED/HD

CSC Matrix 6

1

x = Logic 0 or Logic 1.

2

ED = enhanced definition = 525p and 625p.

3

Available on the ADV7392/ADV7393 (40-pin devices) only.

4

Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).

Reserved 0 Zero must be written to this bit. 0x20 HD interlace external

and

HSYNC

VSYNC

1

If using HD

HSYNC/VSYNC

interlace mode, setting this bit to 1 is recommended (see the HD Interlace External

HSYNC

and

VSYNC

Considerations section for more information).

Test pattern black bar4 0 Disabled.

1 Enabled.

Manual CSC matrix adjust 0 Disable manual CSC matrix adjust.

Sync on RGB 0 No sync.

1 Sync on all RGB outputs.

RGB/YPrPb output select 0 RGB component outputs.

1 YPrPb component outputs.

SD sync output enable 0 No sync output.

1

Output SD syncs on

HSYNC

and

VSYNC

pins.

ED/HD sync output enable 0 No sync output.

Output ED/HD syncs on VSYNC

pins.

HSYNC

and

x x LSBs for GY. 0x03

x x LSBs for RV. 0xF0

x x LSBs for BU. x x LSBs for GV. x x LSBs for GU.

x x x x x x x x Bits[9:2] for GY. 0x4E

x x x x x x x x Bits[9:2] for GU. 0x0E

x x x x x x x x Bits[9:2] for GV. 0x24

x x x x x x x x Bits[9:2] for BU. 0x92

x x x x x x x x Bits[9:2] for RV. 0x7C

Rev. I | Page 29 of 107

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

disabled.

1 DAC 1 low power enabled.

DAC 2 cable detect

0 Cable detected on

Unconnected DAC autopower-down

0 DAC autopower-down

0x17

Software reset

Reserved

0

0x00

clearing bit.

Table 19. Register 0x0B to Register 0x17

SR7 to Bit Number1 Reset

SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value

0x0B DAC 1, DAC 2,

DAC 3 output levels

0x0D DAC power

mode

Positive gain to DAC output voltage 0 0 0 0 0 0 0 0 0%. 0x00

0 0 0 0 0 0 0 1 +0.018%. 0 0 0 0 0 0 1 0 +0.036%. … … … … … … … … … 0 0 1 1 1 1 1 1 +7.382%. 0 1 0 0 0 0 0 0 +7.5%.

Negative gain to DAC output voltage 1 1 0 0 0 0 0 0 −7.5%.

1 1 0 0 0 0 0 1 −7.382%. 1 0 0 0 0 0 1 0 −7.364%. … … … … … … … … … 1 1 1 1 1 1 1 1 −0.018%.

DAC 1 low power mode 0 DAC 1 low power

0x00

DAC 2 low power mode 0 DAC 2 low power

disabled.

1 DAC 2 low power enabled.

DAC 3 low power mode 0 DAC 3 low power

disabled.

1 DAC 3 low power enabled.

SD/ED oversample rate select 0 SD = 16×, ED = 8×.

1 SD = 8×, ED = 4×.

Reserved 0 0 0 0

0x10 Cable detection DAC 1 cable detect 0 Cable detected on

DAC 1.

Read only 1 DAC 1 unconnected.

DAC 2. Read only 1 DAC 2 unconnected. Reserved 0 0

disable.

1 DAC autopower-down

enable. Reserved 0 0 0

0x13 Pixel Port

Readback A

0x14 Pixel Port

Readback B

0x16 Control port

readback

2

P[7:0] readback (ADV7390/ADV7391) x x x x x x x x Read only. 0xXX

2

P[15:8] readback (ADV7392/ADV7393)

P[7:0] readback (ADV7392/ADV7393) x x x x x x x x Read only. 0xXX

2

Reserved x x x Read only. 0xXX VSYNC

HSYNC

readback

x

SFL readback x Reserved x x

0x00

1

x = Logic 0 or Logic 1.

2

For correct operation, Subaddress 0x01[6:4] must equal the default value of 000.

Software reset 0 Writing a 1 resets the

1

device; this is a self-

Reserved. 0 0 0 0 0 0

Rev. I | Page 30 of 107

ANALOG DEVICES ADV 7391 BCPZ Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

TABLE OF CONTENTS

REVISION HISTORY

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

SPECIFICATIONS

POWER SUPPLY SPECIFICATIONS

INPUT CLOCK SPECIFICATIONS

ANALOG OUTPUT SPECIFICATIONS

DIGITAL INPUT/OUTPUT SPECIFICATIONS—3.3 V

DIGITAL INPUT/OUTPUT SPECIFICATIONS—1.8 V

MPU PORT TIMING SPECIFICATIONS

DIGITAL TIMING SPECIFICATIONS—3.3 V

DIGITAL TIMING SPECIFICATIONS—1.8 V

VIDEO PERFORMANCE SPECIFICATIONS

POWER SPECIFICATIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

MPU PORT DESCRIPTION

I2C OPERATION

REGISTER MAP ACCESS

REGISTER PROGRAMMING

SUBADDRESS REGISTER (SR7 TO SR0)