16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD)
4:4:4 RGB (SD)
Multiformat video output support
Composite (CVBS) and S-Video (Y-C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Lead frame chip scale package (LFCSP) options
32-lead, 5 mm × 5 mm LFCSP
40-lead, 6 mm × 6 mm LFCSP
Wafer level chip scale package (WLCSP) option
30-ball, 5 × 6 WLCSP with single DAC output
Advanced power management
Patented content-dependent low power DAC operation
Automatic cable detection and DAC power-down
Individual DAC on/off control
Sleep mode with minimal power consumption
74.25 MHz 8-/10-/16-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
EIA/CEA-861B compliance support
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (f
Luma delay
High definition (HD) programmable features
(720p/1080i/1035i)
4× oversampling (297 MHz)
Internal test pattern generator
Color and black bar, hatch, flat field/frame
Fully programmable YCrCb to RGB matrix
Rev. I Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
) and phase
SC
10-Bit SD/HD Video Encoder
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS (720p/1080i) and CGMS Type B (720p/1080i)
Dual data rate (DDR) input support
Enhanced definition (ED) programmable features
(525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Black bar, hatch, flat field/frame
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p) (ADV7390/ADV7392 only)
CGMS (525p/625p) and CGMS Type B (525p)
Dual data rate (DDR) input support
Standard definition (SD) programmable features
16× oversampling (216 MHz)
Internal test pattern generator
Color and black bar
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF filter with programmable gain/attenuation
PrPb SSAF
Separate pedestal control on component and
Mobile handsets
Digital still cameras
Portable media and DVD players
Portable game consoles
Digital camcorders
Set-top box (STB)
Automotive infotainment (ADV7392 and ADV7393 only)
GENERAL DESCRIPTION
The ADV7390/ADV7391/ADV7392/ADV7393are a family of
high speed, digital-to-analog video encoders on single monolithic
chips. Three 2.7 V/3.3 V, 10-bit video DACs (a single DAC for
the WLCSP package) provide support for composite (CVBS),
S-Video (Y-C), or component (YPrPb/RGB) analog outputs in
either standard definition (SD) or high definition (HD) video
formats. The single DAC WLCSP package supports CVBS
(NTSC and PAL) output only in SD resolution (see Ta b l e 2).
Optimized for low power operation, occupying a minimal
footprint, and requiring few external components, these
encoders are ideally suited to portable and power-sensitive
applications requiring TV-out functionality. Cable detection
and DAC autopower-down features ensure that power
consumption is kept to a minimum.
The ADV7390/ADV7391 have an 8-bit video input port that
supports SD video formats over an SDR interface and HD video
formats over a DDR interface. The ADV7392/ADV7393 have
a 16-bit video input port that can be configured in a variety of
ways. SD RGB input is supported.
All members of the family support embedded EAV/SAV timing
codes, external video synchronization signals, and the I
communication protocol. Tabl e 1 and Table 2 list the video
standards directly supported by the ADV7390/ADV7391/
ADV7392/ADV7393 fa m i ly.
2
C® and
Table 1. Standards Directly Supported by the LFCSP Packages
Active
Resolution I/P
720 × 240 P 59.94 27
720 × 288 P 50 27
720 × 576 I 25 27 ITU-R
640 × 480 I 29.97 24.54 NTSC Square
768 × 576 I 25 29.5 PAL Square
720 × 483 P 59.94 27 SMPTE 293M
720 × 483 P 59.94 27 BTA T-1004
720 × 483 P 59.94 27 ITU-R BT.1358
720 × 483 P 59.94 27 ITU-R BT.1362
720 × 576 P 50 27 ITU-R BT.1362
1920 × 1035 I 30 74.25 SMPTE 240M
1920 × 1035 I 29.97 74.1758 SMPTE 240M
1280 × 720 P 23.97,
1920 × 1080 I 30, 25 74.25 SMPTE 274M
1920 × 1080 P 30, 25, 24 74.25 SMPTE 274M
1920 × 1080 P 23.98, 29.97 74.1758 SMPTE 274M
1920 × 1080 P 24 74.25 ITU-R BT.709-5
1
I = interlaced, P = progressive.
Frame
1
Rate (Hz)
25, 24
59.94, 29.97
Clock Input
(MHz) Standard
BT.601/656
BT.601/656
Pixel
Pixel
74.1758 SMPTE 296M
Table 2. Standards Directly Supported by the WLCSP Package
I/P
Frame
1
Rate (Hz)
Active
Resolution
720 × 480 I 29.97 27 ITU-R
720 × 576 I 25 27 ITU-R
Clock Input
(MHz)
Standard
BT.601/656
BT.601/656
Pixel
768 × 576 I 25 29.5 PAL Square
Pixel
1
I = interlaced, P = progressive.
Rev. I | Page 5 of 107
Page 6
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
FUNCTIONAL BLOCK DIAGRAMS
DGND (2)
(2)
V
DD
SCL SDA ALSBSFL
AGND
V
AA
GND_IO
V
DD_IO
8-BIT SD
8-BIT ED/HD
OR
VBI DATA SERVICE
INSERTION
SDR/DDR
SD/ED/HD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
ASYNC
BYPASS
YCrCb
HDTV
TEST
PATTERN
GENERATOR
POWER
MANAGEMENT
CONTROL
RESETHSYNCVSYNC
VIDEO TI MING GENERATO R
MPU PORT
ADD
SYNC
ADD
BURST
PROGRAMMABLE
ED/HD FILTERS
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
PROGRAM MABLE
LUMINANCE
FILTER
PROGRAM MABLE
CHROMI NANCE
FILTER
SUBCARRIER FREQ UENCY
LOCK (SFL)
YCrCb
TO
RGB
SIN/COS DDS
BLOCK
YCbCr
TO
RGB MATRI X
16×/4× OVERSAMPLI NG PLL
CLKIN PV
ADV7390/ADV7391
16×
FILTER
16×
FILTER
MULTIPLEXER
4×
FILTER
PGND EXT_LFCOMP
DD
11-BIT
DAC 1
11-BIT
DAC 2
11-BIT
DAC 3
REFERENCE
AND CABLE
DETECT
DAC 1
DAC 2
DAC 3
R
SET
06234-001
Figure 1. ADV7390/ADV7391 (32-Lead LFCSP)
(2)
GND_IO
V
DD_IO
8-BIT SD
DGND (2)
VBI DATA SERVI CE
INSERTION
SDR/DDR
SD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
V
DD
SCL SDA ALSB
MPU PORT
ADD
SYNC
ADD
BURST
PROGRAM MABLE
LUMINANCE
FILTER
PROGRAM MABLE
CHROMI NANCE
FILTER
SFL
SUBCARRIER FREQ UENCY
LOCK (SFL )
SIN/CO S DDS
BLOCK
16×
FILTER
16×
FILTER
ADV7390BCBZ
MULTIPLEXER
AGND
11-BIT
DAC 1
V
AA
DAC 1
POWER
MANAGEMENT
CONTROL
RESETHSYNCVSYNC
VIDEO TIMING GENERATOR
16× OVERSAMPLI NG PLL
CLKIN PV
PGND EXT_LFCOMP
DD
REFERENCE
AND CABLE
DETECT
R
SET
06234-146
Figure 2. ADV7390BCBZ-A (30-Ball WLCSP)
AGND
12-BIT
DAC 1
12-BIT
DAC 2
12-BIT
DAC 3
REFERENCE
AND CABLE
DETECT
V
AA
DAC 1
DAC 2
DAC 3
R
SET
06234-145
GND_IO
V
DD_IO
8-/10-/16-B IT SD
8-/10-/16-B IT ED/H D
OR
V
(2)
DGND (2)
VBI DATA SERVICE
INSERTION
SDR/DDR
SD/ED/HD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
POWER
MANAGEM ENT
CONTROL
RESETHSYNCVSYNC
DD
RGB
TO
YCrCb
MATRIX
ASYNC
BYPASS
YCrCb
HDTV
TEST
PATTERN
GENERATOR
VIDEO T IMI NG GENERA TOR
SCL SDA ALSBSFL
MPU PORT
ADD
SYNC
ADD
BURST
PROGRAMMABLE
ED/HD FILTERS
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
Figure 3. ADV7392/ADV7393 (40-Lead LFCSP)
PROGRAMMABLE
LUMINANCE
FILTER
PROGRAMMABLE
CHROMI NANCE
FILTER
SUBCARRIER FREQ UENCY
LOCK (SFL)
YCrCb
TO
RGB
SIN/CO S DDS
BLOCK
YCbCr
TO
RGB MATRI X
16x/4x OVERSAMPLING PLL
CLKIN PV
PGND EXT_LFCOM P
DD
ADV7392/ADV7393
16×
FILTER
16×
FILTER
MULTIPLEXER
4×
FILTER
Rev. I | Page 6 of 107
Page 7
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
DAC-to-DAC Matching
DAC 1, DAC 2, DAC 3
2.0 %
SPECIFICATIONS
POWER SUPPLY SPECIFICATIONS
All specifications T
Table 3.
Parameter Min Typ Max Unit
SUPPLY VOLTAGES
VDD 1.71 1.8 1.89 V
V
1.71 3.3 3.63 V
DD_IO
PVDD 1.71 1.8 1.89 V
VAA 2.6 3.3 3.465 V
POWER SUPPLY REJECTION RATIO 0.002 %/%
INPUT CLOCK SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, V
All specifications T
Table 4.
Parameter Conditions1 Min Typ Max Unit
f
SD/ED 27 MHz
CLKIN
ED (at 54 MHz) 54 MHz
HD 74.25 MHz
CLKIN High Time, t9 40 % of one clock cycle
CLKIN Low Time, t10 40 % of one clock cycle
CLKIN Peak-to-Peak Jitter Tolerance 2 ±ns
1
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.
MIN
MIN
to T
to T
(−40°C to +85°C), unless otherwise noted.
MAX
(−40°C to +85°C), unless otherwise noted.
MAX
= 1.71 V to 3.63 V.
DD_IO
ANALOG OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, V
All specifications T
MIN
to T
(−40°C to +85°C), unless otherwise noted.
MAX
Table 5.
Parameter Conditions Min Typ Max Unit
Full-Drive Output Current R
= 510 Ω, RL = 37.5 Ω 33 34.6 37 mA
SET
All DACs enabled R
= 510 Ω, RL = 37.5 Ω 31.5 33.5 37 mA
SET
DAC 1 enabled only1
Low-Drive Output Current R
= 4.12 kΩ, RL = 300 Ω 4.3 mA
SET
Output Compliance, VOC 0 1.4 V
Output Capacitance, C
10 pF
OUT
Analog Output Delay2 6 ns
DAC Analog Output Skew DAC 1, DAC 2, DAC 3 1 ns
1
The recommended method of bringing this value back to the ideal value is by adjusting Register 0x0B to the recommended value of 0x12.
2
Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.
= 1.71 V to 3.63 V.
DD_IO
Rev. I | Page 7 of 107
Page 8
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Parameter
Conditions
Min
Typ
Max
Unit
DIGITAL INPUT/OUTPUT SPECIFICATIONS—3.3 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, V
All specifications T
MIN
to T
(−40°C to +85°C), unless otherwise noted.
MAX
Table 6.
Parameter Conditions Min Typ Max Unit
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Input Leakage Current, IIN VIN = V
±10 µA
DD_IO
Input Capacitance, CIN 4 pF
Output High Voltage, VOH I
Output Low Voltage, VOL I
= 400 µA 2.4 V
SOURCE
= 3.2 mA 0.4 V
SINK
Three-State Leakage Current VIN = 0.4 V, 2.4 V ±1 µA
Three-State Output Capacitance 4 pF
DIGITAL INPUT/OUTPUT SPECIFICATIONS—1.8 V
When V
V
= 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, V
DD
All specifications T
Table 7.
Parameter Conditions Min Typ Max Unit
Input High Voltage, VIH 0.7 V
Input Low Voltage, VIL 0.3 V
Input Capacitance, CIN 4 pF
Output High Voltage, VOH I
Output Low Voltage, VOL I
Three-State Output Capacitance 4 pF
is set to 1.8 V, all the digital video inputs and control inputs, such as I2C, HS, and VS, should use 1.8 V levels.
DD_IO
MIN
to T
(−40°C to +85°C), unless otherwise noted.
MAX
= 400 µA V
SOURCE
= 3.2 mA 0.4 V
SINK
= 2.97 V to 3.63 V.
DD_IO
= 1.71 V to 1.89 V.
DD_IO
V
DD_IO
– 0.4 V
DD_IO
DD_IO
V
MPU PORT TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, V
All specifications T
MIN
to T
(−40°C to +85°C), unless otherwise noted.
MAX
Table 8.
MPU PORT, I2C MODE1 See Figure 17
SCL Frequency 0 400 kHz
SCL High Pulse Width, t1 0.6 µs
SCL Low Pulse Width, t2 1.3 µs
Hold Time (Start Condition), t3 0.6 µs
Setup Time (Start Condition), t4 0.6 µs
Data Setup Time, t5 100 ns
SDA, SCL Rise Time, t6 300 ns
SDA, SCL Fall Time, t7 300 ns
Setup Time (Stop Condition), t8 0.6 µs
1
Guaranteed by characterization.
= 1.71 V to 3.63 V.
DD_IO
Rev. I | Page 8 of 107
Page 9
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
ED/HD-SDR or ED/HD-DDR
2.3
ns
Component Outputs (2×)
SD oversampling disabled
78 Clock cycles
DIGITAL TIMING SPECIFICATIONS—3.3 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, V
All specifications T
MIN
to T
(−40°C to +85°C), unless otherwise noted.
MAX
Table 9.
Parameter Conditions1 Min Typ Max Unit
VIDEO DATA AND VIDEO CONTROL PORT
Data Input Setup Time, t
4
SD 2.1 ns
11
2, 3
ED/HD-SDR 2.3 ns
ED/HD-DDR 2.3 ns
ED (at 54 MHz) 1.7 ns
Data Input Hold Time, t
4
SD 1.0 ns
12
ED/HD-SDR 1.1 ns
ED/HD-DDR 1.1 ns
ED (at 54 MHz) 1.0 ns
Control Input Setup Time, t
4
SD 2.1 ns
11
= 2.97 V to 3.63 V.
DD_IO
ED (at 54 MHz) 1.7 ns
Control Input Hold Time, t
4
SD 1.0 ns
12
ED/HD-SDR or ED/HD-DDR 1.1 ns
ED (at 54 MHz) 1.0 ns
Control Output Access Time, t
4
SD 12 ns
13
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 10 ns
Control Output Hold Time, t
Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal
step value. For −ve DNL, the actual step value lies below the ideal step value.
3
Measured on the ADV7392/ADV7393 operating in 10-bit input mode.
= 3.3 V, TA = +25°C.
DD_IO
= 510 Ω, RL = 37.5 Ω 0.5 LSBs
SET
= 510 Ω, RL = 37.5 Ω 0.5 LSBs
SET
POWER SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, V
Table 12.
Parameter Conditions Min Typ Max Unit
NORMAL POWER MODE
3
I
SD (16× oversampling enabled), CVBS (only one DAC turned on) 33 mA
DD
1, 2
SD (16× oversampling enabled), YPrPb (three DACs turned on) 68 mA
ED (8× oversampling enabled)4 59 mA
HD (4× oversampling enabled)4 81 101 mA
I
1 10 mA
DD_IO
5
I
One DAC enabled 50 mA
AA
All DACs enabled 122 151 mA
I
4 10 mA
PLL
SLEEP MODE
IAA 0.3 µA
I
0.2 µA
DD_IO
I
0.1 µA
PLL
1
R
= 510 Ω (all DACs operating in full-drive mode).
SET
2
75% color bar test pattern applied to pixel data pins.
3
IDD is the continuous current required to drive the digital core.
4
Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.
5
IAA is the total current required to supply all DACs.
= 3.3 V, TA = +25°C.
DD_IO
Rev. I | Page 11 of 107
Page 12
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
t
9
CLKIN
t
10
CONTRO
L
OUTPUTS
HSYNC
VSYNC
Cr2
Cb2Cr0Cb0
IN MASTER/SLA
VE MODE
IN SL
AVE MODE
Y0
Y1Y2
PIXE
L PORT
CONTROL
INPUTS
t
12
t
1
1
t
13
t
14
06234-002
IN MASTER/SLAVE MODE
IN SLAVE MODE
CLKIN
CONTROL
OUTPUTS
t
9t10
Cr2
Cb2
Cr0Cb0
Y0
Y1
Y2
Y3
t
12
t
14
t
11
t
13
HSYNC
VSYNC
CONTROL
INPUTS
PIXEL PORT
PIXEL PORT
06234-003
•t
TIMING DIAGRAMS
The following abbreviations are used in Figure 4 to Figure 11:
•t
= clock high time
9
•t
= clock low time
10
•t
= data setup time
11
•t
= data hold time
12
= control output access time
13
•t
= control output hold time
14
In addition, see Table 35 for the ADV7390/ADV7391 pixel port
input configuration and Tabl e 36 for the ADV7392/ADV7393
pixel port input configuration.
AGND to DGND −0.3 V to +0.3 V
AGND to PGND −0.3 V to +0.3 V
AGND to GND_IO −0.3 V to +0.3 V
DGND to PGND −0.3 V to +0.3 V
DGND to GND_IO −0.3 V to +0.3 V
PGND to GND_IO −0.3 V to +0.3 V
Digital Input Voltage to GND_IO −0.3 V to V
DD_IO
+ 0.3 V
Analog Outputs to AGND −0.3 V to VAA
Max CLKIN Input Frequency 80 MHz
Storage Temperature Range (tS) −60°C to +150°C
Junction Temperature (tJ) 150°C
Lead Temperature (Soldering, 10 sec) 260°C
1
Analog output short circuit to any power supply or common can be of an
indefinite duration.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
JA
2
θ
1
JC-TOP
3
θ
JC-BOTTOM
4
Unit
Table 14. Thermal Resistance
Package Type θ
30-Ball WLCSP 35 1 N/A °C/W
1
Values are based on a JEDEC 4-layer test board.
2
With the exposed metal paddle on the underside of the LFCSP soldered to
the PCB ground.
3
This is the thermal resistance of the junction to the top of the package.
4
This is the thermal resistance of the junction to the bottom of the package.
The ADV7390/ADV7391/ADV7392/ADV7393 are RoHScompliant, Pb-free products. The lead finish is 100% pure Sn
electroplate. The device is suitable for Pb-free applications up to
255°C (±5°C) IR reflow (JEDEC STD-20).
The ADV7390/ADV7391/ADV7392/ADV7393 are backward
compatible with conventional SnPb soldering processes. The
electroplated Sn coating can be soldered with SnPb solder pastes
at conventional reflow temperatures of 220°C to 235°C.
ESD CAUTION
Rev. I | Page 18 of 107
Page 19
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
O
R
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
D
DD
HSYNC
V
SFL
VSYNC
DGN
P0
GND_IO
P1
31
30
32
V
1
DD_IO
V
DD
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO ANALO G GROUND (AG ND).
2P2
3P3
4P4
5
6DGND
7P5
8P6
PIN 1
INDICATOR
ADV7390/
ADV7391
TOP VIEW
(Not to Scale)
9
11
10
P7
SDA
ALSB
Figure 18. ADV7390/ADV7391 Pin Configuration
P1
P2
P3
GND_I
40
39
38
37
V
1
DD_IO
2
P4
3
V
DGND
P10
P5
4
P6
5
P7
6
DD
7
8
P8
9
P9
10
ADV7392/
ADV7393
TOP VIEW
(Not to Scale)
25
26
27
28
29
R
24
SET
23 COMP
22 DAC 1
21 DAC 2
20 DAC 3
19 V
AA
18 AGND
17 PV
DD
12
13
14
15
16
SCL
PGND
CLKIN
XT_LF
RESET
E
06234-017
DD
P0
DGND
SFL
VSYNC
V
HSYNC
31
32
36
35
34
33
R
30
SET
29
COMP
28
DAC 1
DAC 2
27
DAC 3
26
V
25
AA
AGND
24
PV
23
DD
EXT_LF
22
PGND
21
BALL A1 CORNE
234
1
R
A
SET
DAC1
B
V
C
AA
D
AGND
E
PV
DD
PGNDSDASCLCLKINP7
F
V
HSYNC
VSYNC
COMP DGNDP3P4
GND_IO
EXT_LF
DD
SFLP1P2
RESET
ALSBP5P6
TOP VIEW
(BALL SIDE DOWN)
Not to Scal e
VDDDGND
5
V
P0
DD_IO
Figure 20. ADV7390BCBZ-A Pin Configuration
06234-147
11
13
12
14
15
P11
P12
SCL
SDA
ALSB
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO ANALOG GROUND (AG ND).
20
19
18
16
17
ET
P14
P13
P15
LKIN
C
RES
6234-018
Figure 19. ADV7392/ADV7393 Pin Configuration
Table 15. Pin Function Descriptions
Pin No.1
ADV7390/
ADV7391
9 to 7, 4 to 2,
31, 30
N/A
ADV7392/
ADV7393
N/A
18 to 15, 11 to
8, 5 to 2, 39 to
ADV7390
WLCSP
F5, E5, E4, C5,
Mnemonic
P7 to P0 I
C4, B5, B4, A4
N/A P15 to P0 I
Input/
Output Description
8-Bit Pixel Port (P7 to P0). P0 is the LSB. See Table 35 for
input modes (ADV7390/ADV7391).
16-Bit Pixel Port (P15 to P0). P0 is the LSB. See Table 36 for
input modes (ADV7392/ADV7393).
37, 34
13 19 F4 CLKIN I
Pixel Clock Input for HD (74.25 MHz), ED
or SD (27 MHz).
27 33 A2
HSYNC
I/O
Horizontal Synchronization Signal. This pin can also be
configured to output an SD, ED, or HD horizontal
synchronization signal. See the External Horizontal and
Vertical Synchronization Control section.
26 32 B2
VSYNC
I/O
Vertical Synchronization Signal. This pin can also be
configured to output an SD, ED, or HD vertical
synchronization signal. See the External Horizontal and
Vertical Synchronization Control section.
25 31 B3 SFL I/O Subcarrier Frequency Lock (SFL) Input.
2
(27 MHz or 54 MHz),
Rev. I | Page 19 of 107
Page 20
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
22, 21, 20
28, 27, 26
N/A
DAC 1, DAC 2,
O
DAC Outputs. Full-drive and low-drive capable DACs.
Pin No.1
ADV7390/
ADV7391
24 30 A1 R
ADV7392/
ADV7393
ADV7390
WLCSP
Mnemonic
I Controls the amplitudes of the DAC 1, DAC 2, and DAC 3
SET
23 29 C2 COMP O Compensation Pin. Connect a 2.2 nF capacitor from COMP
N/A N/A B1 DAC 1 O DAC Output. Full-drive and low-drive capable DAC
DAC 3
12 14 F3 SCL I I2C Clock Input.
11 13 F2 SDA I/O I2C Data Input/Output.
10 12 E3 ALSB I ALSB sets up the LSB3 of the MPU I2C address.
14 20 D3
I Resets the on-chip timing generator and sets the
RESET
19 25 C1 VAA P Analog Power Supply (2.7 V or 3.3 V).
5, 28 6, 35 A3, D4 VDD P Digital Power Supply (1.8 V). For dual-supply
1 1 A5 V
P Input/Output Digital Power Supply (1.8 V or 3.3 V).
DD_IO
17 23 E1 PVDD P PLL Power Supply (1.8 V). For dual-supply configurations,
16 22 E2 EXT_LF I External Loop Filter for the Internal PLL.
15 21 F1 PGND G PLL Ground Pin.
18 24 D1 AGND G Analog Ground Pin.
6, 29 7, 36 C3, D5 DGND G Digital Ground Pin.
32 40 D2 GND_IO G Input/Output Supply Ground Pin.
EPAD G Exposed Pad. Connect to analog ground (AGND).
1
N/A means not applicable.
2
ED = enhanced definition = 525p and 625p.
3
LSB = least significant bit. In the ADV7390/ADV7392, setting the LSB to 0 sets the I2C address to 0xD4. Setting it to 1 sets the I2C address to 0xD6. In the
ADV7391/ADV7393, setting the LSB to 0 sets the I
2
C address to 0x54. Setting it to 1 sets the I2C address to 0x56.
Input/
Output Description
outputs. For full-drive operation (for example, into a 37.5 Ω
load), a 510 Ω resistor must be connected from R
AGND. For low-drive operation (for example, into a 300 Ω
load), a 4.12 kΩ resistor must be connected from R
AGND.
.
to V
AA
ADV7390/ADV7391/ADV7392/ADV7393 into its default
mode.
configurations, VDD can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
PVDD can be connected to other 1.8 V supplies through a
ferrite bead or suitable filtering.
SET
SET
to
to
Rev. I | Page 20 of 107
Page 21
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
TYPICAL PERFORMANCE CHARACTERISTICS
ED Pr/Pb RESPONSE. LINEAR INT ERP FROM 4:2:2 TO 4:4:4
0
–10
–20
–30
–40
GAIN (dB)
–50
–60
–70
–80
FREQUENCY (MHz)
20020 4060 80 100 120 140 160 1800
Figure 21. ED 8× Oversampling, PrPb Filter (Linear) Response
EDPr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
0
–10
–20
–30
–40
GAIN (dB)
–50
–60
–70
–80
FREQUENCY (MHz)
20020 4060 80 100 120 140 16 0 1800
Figure 22. ED 8× Oversampling, PrPb Filter (SSAF™) Response
Y RESPONSE IN ED 8× OVERSAMPL ING MODE
0
–10
–20
–30
–40
GAIN (dB)
–50
–60
–70
–80
FREQUENCY (MHz)
2002040 60 80 100 120 14 0 160 1800
Figure 23. ED 8× Oversampling, Y Filter Response
1.0
0.5
–0.5
–1.0
GAIN (dB)
–1.5
–2.0
–2.5
–3.0
06234-019
Figure 24. ED 8× Oversampling, Y Filter Response (Focus on Pass Band)
10
0
–10
–20
–30
–40
–50
GAIN (dB)
–60
–70
–80
–90
–100
06234-020
Figure 25. HD 4× Oversampling, PrPb (SSAF) Filter Response
–10
–20
–30
–40
–50
GAIN (dB)
–60
–70
–80
–90
–100
06234-021
Figure 26. HD 4× Oversampling, PrPb (SSAF) Filter Response
Y RESPONSE IN ED 8× OVERSAMPLING MODE
0
FREQUENCY (MHz)
HD Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
FREQUENCY (MHz)
(4:2:2 Input)
HD Pr/Pb RES PONSE. 4: 4:4 INPUT MODE
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140
FREQUENCY (M Hz)
(4:4:4 Input)
122468100
06234-022
148.018.537.055. 574.092.5 111.0 129.50
06234-023
06234-024
Rev. I | Page 21 of 107
Page 22
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
10
–10
–20
–30
–40
–50
GAIN (dB)
–60
–70
–80
–90
–100
3.0
1.5
–1.5
–3.0
–4.5
GAIN (dB)
–6.0
–7.5
–9.0
–10.5
–12.0
27.75046.250
Figure 28. HD 4× Oversampling, Y Filter Response (Focus on Pass Band)
Y RESPONSE I N HD 4× OVERSAMPL ING MODE
0
FREQUENCY ( MHz)
Figure 27. HD 4× Oversampling, Y Filter Response
Y PASS BAND IN HD 4x OVERSAMPLING MODE
0
30.063 32.375 34.688 37.000 39.312 41. 625 43.937
FREQUENCY (MHz)
0
–10
–20
–30
–40
MAGNITUDE (dB)
–50
–60
148.018.537.055. 574.092.5 111.0 129.50
06234-025
–70
FREQUENCY (MHz)
121086420
6234-028
Figure 30. SD PAL, Luma Low-Pass Filter Response
0
–10
–20
–30
–40
MAGNITUDE (dB)
–50
–60
–70
06234-026
FREQUENCY (MHz)
121086420
06234-029
Figure 31. SD NTSC, Luma Notch Filter Response
0
–10
–20
–30
–40
MAGNITUDE (dB)
–50
–60
–70
FREQUENCY (MHz)
Figure 29. SD NTSC, Luma Low-Pass Filter Response
121086420
6234-027
Rev. I | Page 22 of 107
0
–10
–20
–30
–40
MAGNITUDE (dB)
–50
–60
–70
FREQUENCY (MHz)
121086420
06234-030
Figure 32. SD PAL, Luma Notch Filter Response
Page 23
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Y RESPONSE IN SD OVERSAMPLING MODE
0
–10
–20
–30
–40
GAIN (dB)
–50
–60
–70
–80
020 4060 80 100 120 140 160 180 200
FREQUENCY (MHz)
Figure 33. SD 16× Oversampling, Y Filter Response
06234-031
5
4
3
2
MAGNITUDE ( dB)
1
0
–1
0
234
1
FREQUENCY (MHz)
Figure 36. SD Luma SSAF Filter, Programmable Gain
5
6
7
06234-034
0
–10
–20
–30
–40
MAGNITUDE ( dB)
–50
–60
–70
FREQUENCY (MHz)
Figure 34. SD Luma SSAF Filter Response up to 12 MHz
Devices such as a microprocessor can communicate with the
ADV7390/ADV7391/ADV7392/ADV7393 through a 2-wire
2
serial (I
port is configured for I
C-compatible) bus. After power-up or reset, the MPU
2
C operation.
I2C OPERATION
The ADV7390/ADV7391/ADV7392/ADV7393 support a 2wire serial (I
multiple peripherals. This port operates in an open-drain
configuration. Two wires, serial data (SDA) and serial clock
(SCL), carry information between any device connected to the
bus and the ADV7390/ADV7391/ADV7392/ADV7393. The
slave address depends on the device (ADV7390, ADV7391,
ADV7392, or ADV7393), the operation (read or write), and the
state of the ALSB pin (0 or 1). See Table 16, Figure 47, and
Figure 48. The LSB sets either a read or a write operation. Logic
1 corresponds to a read operation, and Logic 0 corresponds to a
write operation. A1 is controlled by setting the ALSB pin of the
ADV7390/ADV7391/ADV7392/ADV7393 to Logic 0 or Logic 1.
Table 16. ADV7390/ADV7391/ADV7392/ADV7393 I
Slave Addresses
Device ALSB Operation Slave Address
ADV7390
and
ADV7392
ADV7391
and
ADV7393
2
C-compatible) microprocessor bus driving
0 Write 0xD4
0 Read 0xD5
1 Write 0xD6
0 Write 0x54
0 Read 0x55
1 Write 0x56
1 Read 0x57
2
Figure 47. ADV7390/ADV7392 I
C Slave Address
2
C
The various devices on the bus use the following protocol. The
master initiates a data transfer by establishing a start condition,
defined by a high-to-low transition on SDA while SCL remains
high. This indicates that an address/data stream follows. All
peripherals respond to the start condition and shift the next
eight bits (7-bit address plus the R/
W
bit).
The bits are transferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition
occurs when the device monitors the SDA and SCL lines
waiting for the start condition and the correct transmitted
address. The R/
W
bit determines the direction of the data.
Logic 0 on the LSB of the first byte means that the master writes
information to the peripheral. Logic 1 on the LSB of the first byte
means that the master reads information from the peripheral.
The ADV7390/ADV7391/ADV7392/ADV7393 act as a
standard slave device on the bus. The data on the SDA pin is
eight bits long, supporting the 7-bit addresses plus the R/
W
bit.
It interprets the first byte as the device address and the second
byte as the starting subaddress. There is a subaddress autoincrement facility. This allows data to be written to or read from
registers in ascending subaddress sequence starting at any valid
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all the registers.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, they cause an
immediate jump to the idle condition. During a given SCL high
period, the user should issue only a start condition, a stop
condition, or a stop condition followed by a start condition. If
an invalid subaddress is issued by the user, the ADV7390/
ADV7391/ADV7392/ADV7393 do not issue an acknowledge
but returns to the idle condition. If the user uses the autoincrement method of addressing the encoder and exceeds the
highest subaddress, the following actions are taken:
•In read mode, the highest subaddress register contents are
output until the master device issues a no acknowledge.
This indicates the end of a read. A no acknowledge condition
occurs when the SDA line is not pulled low on the ninth pulse.
•In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by
the ADV7390/ADV7391/ADV7392/ADV7393, and the
part returns to the idle condition.
Figure 48. ADV7391/ADV7393 I
2
C Slave Address
Rev. I | Page 26 of 107
Figure 49 shows an example of data transfer for a write sequence
and the start and stop conditions. Figure 50 shows bus write
and read sequences.
Page 27
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
SDA
SCL
1–78
START ADDR R/W ACK SUBADDRESS ACKDATAACK STOP
9S1–7
Figure 49. I
9
8
2
C Data Transfer
1–7
8
P
9
06234-047
WRITE
SEQUENCE
READ
SEQUENCE
S SLAVE ADDR A(S ) SUBADDRA(S)DATADATAA(S) P
LSB = 0
S SLAVE ADDR A(S) SUBADDRA(S) S SLAVE ADDR A(S)DATADATAA(M)A(M) P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDG E BY MASTER
Figure 50. I
2
C Read and Write Sequence
A(S)
LSB = 1
A (S) = NO-ACKNOWLEDGE BY SLAVE
A (M) = NO-ACKNOWLEDGE BY MASTER
06234-048
Rev. I | Page 27 of 107
Page 28
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
mode off
1 1 0 Reserved.
REGISTER MAP ACCESS
A microprocessor can read from or write to all registers of the
ADV7390/ADV7391/ADV7392/ADV7393 via the MPU port,
except for registers that are specified as read-only or write-only
registers.
The subaddress register determines the register accessed by the
next read or write operation. All communication through the
MPU port starts with an access to the subaddress register. A
read/write operation is then performed from/to the target
address, incrementing to the next address until the transaction
is complete.
Table 17. Register 0x00
SR7 to Bit Number Register Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Setting Value
0x00 Power
mode
Sleep mode. With this control enabled, the current consumption is
reduced to µA level. All DACs and the internal PLL circuit are
disabled. Registers can be read from and written to in sleep mode.
PLL and oversampling control. This control allows the internal PLL
circuit to be powered down and the oversampling to be switched off.
DAC 3: power on/off. 0 DAC 3 off
DAC 2: power on/off. 0 DAC 2 off
DAC 1: power on/off. 0 DAC 1 off
Reserved. 0 0 0
REGISTER PROGRAMMING
Table 17 to Table 34 describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.
SUBADDRESS REGISTER (SR7 TO SR0)
The subaddress register is an 8-bit write-only register. After the
MPU port is accessed and a read/write operation is selected, the
subaddress is set up. The subaddress register determines which
register performs the next operation.
0 Sleep
1 Sleep
mode on
0 PLL on
1 PLL off
1 DAC 3 on
1 DAC 2 on
1 DAC 1 on
0x12
Table 18. Register 0x01 to Register 0x09
SR7 to Bit Number1 Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x01 Mode
select
Reserved. 0 0x00
DDR clock edge alignment
(used only for ED
DDR modes)
Reserved 0
Input mode
(see Subaddress 0x30, Bits[7:3]
for ED/HD standard selection)
Reserved 0
2
and HD
0 0 Chroma clocked in on rising clock edge and
0 1 Reserved.
1 0 Reserved.
1 1 Luma clocked in on rising clock edge and
0 Gamma Correction Curve A.
1 Gamma Correction Curve B.
0 Disabled.
1 Enabled.
1 Mode B.
0 Disabled.
enable
0x36 ED/HD Y level5 ED/HD Test Pattern Y level x x x x x x x x Y level value. 0xA0
0x37 ED/HD Cr level5 ED/HD Test Pattern Cr level x x x x x x x x Cr level value. 0x80
0x38 ED/HD Cb level5 ED/HD Test Pattern Cb level x x x x x x x x Cb level value. 0x80
1
x = Logic 0 or Logic 1.
2
Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1.
3
Applies to the ADV7390 and ADV7392 only.
4
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
5
For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).
Rev. I | Page 33 of 107
Page 34
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
INV_PBLANK_POL
0 Disabled
… … … … …
1
0
0
0
Gain B = −8
Table 23. Register 0x39 to Register 0x43
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x39 ED/HD Mode
Register 7
0X3A ED/HD Mode
Register 8
0x40 ED/HD
sharpness filter
gain
Reserved 0 0 0 0 0 0x00
ED/HD EIA/CEA-861B
synchronization compliance
Reserved 0 0
INV_PHSYNC_POL 0 Disabled 0x00
INV_PVSYNC_POL 0 Disabled
Reserved 0 0 0 0 0
ED/HD sharpness filter gain
Value A
ED/HD sharpness filter gain
Value B
0 Disabled 1 Enabled
1 Enabled
1 Enabled
1 Enabled
0 0 0 0 Gain A = 0 0x00
0 0 0 1 Gain A = +1
0 1 1 1 Gain A = +7
1 0 0 0 Gain A = −8
… … … … …
1 1 1 Gain A = −1
0 0 0 0 Gain B = 0
0 0 0 1 Gain B = +1
… … … … …
0 1 1 1 Gain B = +7
0x41 ED/HD CGMS
Data 0
0x42 ED/HD CGMS
Data 1
0x43 ED/HD CGMS
Data 2
… … … … …
1 1 1 1 Gain B = −1
ED/HD CGMS data bits 0 0 0 0 C19 C18 C17 C16 CGMS C19 to C16 0x00
ED/HD CGMS data bits C15 C14 C13 C12 C11 C10 C9 C8 CGMS C15 to C8 0x00
ED/HD CGMS data bits C7 C6 C5 C4 C3 C2 C1 C0 CGMS C7 to C0 0x00
Rev. I | Page 34 of 107
Page 35
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
0x44
ED/HD Gamma A0
ED/HD Gamma Curve A (Point 24)
x
x
x
x
x
x
x
x
A0
0x00
0x4C
ED/HD Gamma A8
ED/HD Gamma Curve A (Point 192)
x
x
x
x
x
x
x
x
A8
0x00
0x55
ED/HD Gamma B7
ED/HD Gamma Curve B (Point 160)
x
x
x
x
x
x
x
x
B7
0x00
Table 24. Register 0x44 to Register 0x57
SR7 to Bit Number1 Register Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Setting Value
0x45 ED/HD Gamma A1 ED/HD Gamma Curve A (Point 32) x x x x x x x x A1 0x00
0x46 ED/HD Gamma A2 ED/HD Gamma Curve A (Point 48) x x x x x x x x A2 0x00
0x47 ED/HD Gamma A3 ED/HD Gamma Curve A (Point 64) x x x x x x x x A3 0x00
0x48 ED/HD Gamma A4 ED/HD Gamma Curve A (Point 80) x x x x x x x x A4 0x00
0x49 ED/HD Gamma A5 ED/HD Gamma Curve A (Point 96) x x x x x x x x A5 0x00
0x4A ED/HD Gamma A6 ED/HD Gamma Curve A (Point 128) x x x x x x x x A6 0x00
0x4B ED/HD Gamma A7 ED/HD Gamma Curve A (Point 160) x x x x x x x x A7 0x00
0x4D ED/HD Gamma A9 ED/HD Gamma Curve A (Point 224) x x x x x x x x A9 0x00
0x4E ED/HD Gamma B0 ED/HD Gamma Curve B (Point 24) x x x x x x x x B0 0x00
0x4F ED/HD Gamma B1 ED/HD Gamma Curve B (Point 32) x x x x x x x x B1 0x00
0x50 ED/HD Gamma B2 ED/HD Gamma Curve B (Point 48) x x x x x x x x B2 0x00
0x51 ED/HD Gamma B3 ED/HD Gamma Curve B (Point 64) x x x x x x x x B3 0x00
0x52 ED/HD Gamma B4 ED/HD Gamma Curve B (Point 80) x x x x x x x x B4 0x00
0x53 ED/HD Gamma B5 ED/HD Gamma Curve B (Point 96) x x x x x x x x B5 0x00
0x54 ED/HD Gamma B6 ED/HD Gamma Curve B (Point 128) x x x x x x x x B6 0x00
0x56 ED/HD Gamma B8 ED/HD Gamma Curve B (Point 192) x x x x x x x x B8 0x00
0x57 ED/HD Gamma B9 ED/HD Gamma Curve B (Point 224) x x x x x x x x B9 0x00
1
x = Logic 0 or Logic 1.
Rev. I | Page 35 of 107
Page 36
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
0
0
0
1
Gain B = +1
0
1
1
1
Gain A = +7
ED/HD Adaptive Filter Gain 3,
0
0
0
0
Gain B = 0
Table 25. Register 0x58 to Register 0x5D
SR7 to Bit Number1 Register Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Setting Value
0x58 ED/HD Adaptive Filter Gain 1 ED/HD Adaptive Filter Gain 1,
Value A
ED/HD Adaptive Filter Gain 1,
Value B
0x59 ED/HD Adaptive Filter Gain 2 ED/HD Adaptive Filter Gain 2,
Value A
ED/HD Adaptive Filter Gain 2,
Value B
0x5A ED/HD Adaptive Filter Gain 3 ED/HD Adaptive Filter Gain 3,
Value A
0 0 0 0 Gain A = 0 0x00
0 0 0 1 Gain A = +1
… … … … …
0 1 1 1 Gain A = +7
1 0 0 0 Gain A = −8
… … … … …
1 1 1 1 Gain A = −1
0 0 0 0 Gain B = 0
0 0 0 1 Gain B = +1
… … … … …
0 1 1 1 Gain B = +7
1 0 0 0 Gain B = −8
… … … … …
1 1 1 1 Gain B = −1
0 0 0 0 Gain A = 0 0x00
0 0 0 1 Gain A = +1
… … … … …
0 1 1 1 Gain A = +7
1 0 0 0 Gain A = −8
… … … … …
1 1 1 1 Gain A = −1
0 0 0 0 Gain B = 0
… … … … …
0 1 1 1 Gain B = +7
1 0 0 0 Gain B = −8
… … … … …
1 1 1 1 Gain B = −1
0 0 0 0 Gain A = 0 0x00
0 0 0 1 Gain A = +1
… … … … …
0x5B ED/HD Adaptive Filter
0x5C ED/HD Adaptive Filter
0x5D ED/HD Adaptive Filter
1
x = Logic 0 or Logic 1.
Threshold A
Threshold B
Threshold C
1 0 0 0 Gain A = −8
… … … … …
1 1 1 1 Gain A = −1
Value B
ED/HD Adaptive Filter Threshold A x x x x x x x x Threshold A 0x00
ED/HD Adaptive Filter Threshold B x x x x x x x x Threshold B 0x00
ED/HD Adaptive Filter Threshold C x x x x x x x x Threshold C 0x00
Rev. I | Page 36 of 107
0 0 0 1 Gain B = +1
… … … … …
0 1 1 1 Gain B = +7
1 0 0 0 Gain B = −8
… … … … …
1 1 1 1 Gain B = −1
Page 37
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
ED/HD CGMS Type B
H5
H4
H3
H2
H1
H0
H5 to H0
0x69
ED/HD CGMS Type B
ED/HD CGMS Type B
P87
P86
P85
P84
P83
P82
P81
P80
P87 to P80
0x00
Table 26. Register 0x5E to Register 0x6E
SR7 to Bit Number Register Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Setting Value
1 Color reversal enabled.
SD luma and color scale control 0 Disabled. 0x00
1 Enabled.
SD luma scale saturation 0 Disabled.
1 Enabled.
1
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
2
Available on the ADV7392/ADV7393 (40-pin devices) only.
1 Enabled.
SD brightness 0 Disabled.
1 Enabled.
SD luma SSAF gain 0 Disabled.
SD input standard autodetection 0 Disabled.
1 Enabled.
Reserved 0 0 must be written to this bit.
SD RGB input enable2 0 SD YCrCb input.
1 SD RGB input.
Rev. I | Page 39 of 107
Page 40
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Table 29. Register 0x88 to Register 0x89
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0 0 0 clock cycles.
0 1 One clock cycle.
1 0 Two clock cycles.
1 1 Three clock cycles.
0x8C SD FSC Register 03 Subcarrier Frequency Bits[7:0] x x x x x x x x Subcarrier Frequency
0x8D
0x8E
0x8F
SD F
SD F
SD F
Register 13
SC
Register 23
SC
Register 33
SC
Subcarrier Frequency Bits[15:8] x x x x x x x x Subcarrier Frequency
Subcarrier Frequency Bits[23:16] x x x x x x x x Subcarrier Frequency
Subcarrier Frequency Bits[31:24] x x x x x x x x Subcarrier Frequency
0x90 SD FSC Phase Subcarrier Phase Bits[9:2] x x x x x x x x Subcarrier Phase Bits[9:2]. 0x00
0x91 SD Closed Captioning Extended data on even fields x x x x x x x x Extended Data Bits[7:0]. 0x00
0x92 SD Closed Captioning Extended data on even fields x x x x x x x x Extended Data Bits[15:8]. 0x00
0x93 SD Closed Captioning Data on odd fields x x x x x x x x Data Bits[7:0]. 0x00
SD subcarrier frequency registers default to NTSC subcarrier frequency values.
to 1 disables the
pedestal on the line
number indicated by
the bit settings.
Rev. I | Page 41 of 107
Page 42
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
0x99
SD CGMS/WSS 0
SD CGMS data
x x x x CGMS Data Bits[C19:C16]
0x00
0x9A
SD CGMS/WSS 1
SD CGMS/WSS data
x
x
x x x x CGMS Data Bits[C13:C8] or
0x00
0xA0
SD hue adjust
SD hue adjust value
x
x
x
x
x
x
x
x
SD Hue Adjust Bits[7:0]
0x00
0xA2
SD luma SSAF
SD luma SSAF gain/attenuation
0
0
0
0
−4 dB
0x00
0
1
1
1
+7/16 [−7/8]
Table 31. Register 0x99 to Register 0xA5
SR7 to Bit Number1 Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
SD CGMS CRC 0 Disabled
1 Enabled
SD CGMS on odd fields 0 Disabled
1 Enabled
SD CGMS on even fields 0 Disabled
1 Enabled
SD WSS 0 Disabled
1 Enabled
WSS Data Bits[W13:W8]
SD CGMS data x x CGMS Data Bits[C15:C14]
0x9B SD CGMS/WSS 2 SD CGMS/WSS data x x x x x x x x CGMS Data Bits[C7:C0] or
0x9C SD scale LSB LSBs for SD Y scale value x x SD Y Scale Bits[1:0] 0x00
LSBs for SD Cb scale value x x SD Cb Scale Bits[1:0]
LSBs for SD Cr scale value x x SD Cr Scale Bits[1:0]
LSBs for SD FSC phase x x Subcarrier Phase Bits[1:0]
0x9D SD Y scale SD Y scale value x x x x x x x x SD Y Scale Bits[9:2] 0x00
0x9E SD Cb scale SD Cb scale value x x x x x x x x SD Cb Scale Bits[9:2] 0x00
0x9F SD Cr scale SD Cr scale value x x x x x x x x SD Cr Scale Bits[9:2] 0x00
0xA1 SD brightness/WSS SD brightness value x x x x x x x SD Brightness Bits[6:0] 0x00
SD blank WSS data 0 Disabled
1 Enabled
(only applicable if Subaddress
0x87, Bit 4 = 1)
Reserved 0 0 0 0
0xA3 SD DNR 0 Coring gain border (in DNR
0xA6 SD Gamma A0 SD Gamma Curve A (Point 24) x x x x x x x x A0 0x00
0xA7 SD Gamma A1 SD Gamma Curve A (Point 32) x x x x x x x x A1 0x00
0xA8 SD Gamma A2 SD Gamma Curve A (Point 48) x x x x x x x x A2 0x00
0xA9 SD Gamma A3 SD Gamma Curve A (Point 64) x x x x x x x x A3 0x00
0xAA SD Gamma A4 SD Gamma Curve A (Point 80) x x x x x x x x A4 0x00
0xAB SD Gamma A5 SD Gamma Curve A (Point 96) x x x x x x x x A5 0x00
0xAD SD Gamma A7 SD Gamma Curve A (Point 160) x x x x x x x x A7 0x00
0xAE SD Gamma A8 SD Gamma Curve A (Point 192) x x x x x x x x A8 0x00
0xAF SD Gamma A9 SD Gamma Curve A (Point 224) x x x x x x x x A9 0x00
0xB0 SD Gamma B0 SD Gamma Curve B (Point 24) x x x x x x x x B0 0x00
0xB1 SD Gamma B1 SD Gamma Curve B (Point 32) x x x x x x x x B1 0x00
0xB2 SD Gamma B2 SD Gamma Curve B (Point 48) x x x x x x x x B2 0x00
0xB3 SD Gamma B3 SD Gamma Curve B (Point 64) x x x x x x x x B3 0x00
0xB4 SD Gamma B4 SD Gamma Curve B (Point 80) x x x x x x x x B4 0x00
0xB5 SD Gamma B5 SD Gamma Curve B (Point 96) x x x x x x x x B5 0x00
0xB7 SD Gamma B7 SD Gamma Curve B (Point 160) x x x x x x x x B7 0x00
0xB8 SD Gamma B8 SD Gamma Curve B (Point 192) x x x x x x x x B8 0x00
0xB9 SD Gamma B9 SD Gamma Curve B (Point 224) x x x x x x x x B9 0x00
0xBA SD brightness detect SD brightness value x x x x x x x x Read only 0xXX
Rev. I | Page 43 of 107
Page 44
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Reserved
0 0 0 Reserved
0xC9
Teletext control
Teletext enable
0
Disabled.
0x00
…
…
…
…
…
SR7 to Bit Number1 Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0xBB Field count Field count x x x Read only 0x0X
Encoder version code 0 0 Read only; first
encoder version
2
0 1 Read only; second
encoder version
1
x = Logic 0 or Logic 1.
2
See the HD Interlace External
HSYNC
and
VSYNC
Considerations section for information about the first encoder version.
Table 33. Register 0xC9 to Register 0xCE
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
1 1 1 1 15 clock cycles.
0xCB TTX Line Enable 0 Teletext on odd fields 22 21 20 19 18 17 16 15 Setting any of these bits
0xCC TTX Line Enable 1 Teletext on odd fields 14 13 12 11 10 9 8 7 0x00
0xCD TTX Line Enable 2 Teletext on even fields 22 21 20 19 18 17 16 15 0x00
0xCE TTX Line Enable 3 Teletext on even fields 14 13 12 11 10 9 8 7 0x00
1
The use of P0 as the teletext input pin is available on the ADV7392/ADV7393 (40-pin devices) only.
to 1 enables teletext on
the line number indicated
by the bit settings.
0x00
Rev. I | Page 44 of 107
Page 45
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
0xE9
Macrovision
MV control bits
x
x
x
x
x
x
x
x 0x00
0xF1
Macrovision
MV control bits
0 0 0 0 0 0 0
x
Bits[7:1] must be 0.
0x00
Table 34. Register 0xE0 to Register 0xF1
SR7 to Bit Number1 Reset
SR0 Register2 Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0xE0 Macrovision MV control bits x x x x x x x x 0x00
0xE1 Macrovision MV control bits x x x x x x x x 0x00
0xE2 Macrovision MV control bits x x x x x x x x 0x00
0xE3 Macrovision MV control bits x x x x x x x x 0x00
0xE4 Macrovision MV control bits x x x x x x x x 0x00
0xE5 Macrovision MV control bits x x x x x x x x 0x00
0xE6 Macrovision MV control bits x x x x x x x x 0x00
0xE7 Macrovision MV control bits x x x x x x x x 0x00
0xE8 Macrovision MV control bits x x x x x x x x 0x00
0xEA Macrovision MV control bits x x x x x x x x 0x00
0xEB Macrovision MV control bits x x x x x x x x 0x00
0xEC Macrovision MV control bits x x x x x x x x 0x00
0xED Macrovision MV control bits x x x x x x x x 0x00
0xEE Macrovision MV control bits x x x x x x x x 0x00
0xEF Macrovision MV control bits x x x x x x x x 0x00
0xF0 Macrovision MV control bits x x x x x x x x 0x00
1
x = Logic 0 or Logic 1.
2
Macrovision registers are available on the ADV7390 and the ADV7392 only.
Rev. I | Page 45 of 107
Page 46
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
MPEG2
DECODER
CLKIN
P[7:0]
27MHz
YCrCb
ADV7390/
ADV7391
VSYNC,
HSYNC
2
8
06234-049
3FF0000XYY0Y1Cr0
CLKIN
NOTES
1. SUBADDRESS 0x01 [2:1] S HOULD BE SET TO 00 IN THIS CASE.
P[7:0]
Cb0
06234-050
3FF0000
XYCb0Cr0Y1
CLKIN
P[7:0]Y0
NOTES
1. SUBADDRESS 0x01 [2:1] S HOULD BE SET TO 11 IN THI S CAS E .
06234-051
MPEG2
DECODER
CLKIN
P[7:0]
INTERLACED TO
PROGRESSIVE
YCrCb
ADV7390/
ADV7391
VSYNC,
HSYNC
8
2
YCrCb
06234-052
3FF0000XYCb0Y0Y1Cr0
CLKIN
P[7:0]
06234-053
ADV7390/ADV7391 INPUT CONFIGURATION
The ADV7390/ADV7391 support a number of different input
modes. The desired input mode is selected using Subaddress 0x01,
Bits[6:4]. The ADV7390/ADV7391 default to standard definition
(SD) mode on power-up. Table 35 provides an overview of all
possible input configurations. Each input mode is described in
detail in this section. Note that the WLCSP option is only
configured to support SD as shown in Figure 51.
SD YCrCb data can be input in an interleaved 4:2:2 format over
an 8-bit bus rate of 27 MHz. A 27 MHz clock signal must be
provided on the CLKIN pin. If required, external synchronization signals can be provided on the
HSYNC
Embedded EAV/SAV timing codes are also supported. The
ITU-R BT.601/656 input standard is supported. The interleaved
pixel data is input on Pin P7 to Pin P0, with Pin P0 being the LSB.
and
VSYNC
pins.
The CrCb pixel data is also input on Pin P7 to Pin P0 on the
opposite edge of CLKIN. Pin P0 is the LSB.
Whether the Y data is clocked in on the rising or falling edge of
CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 52
and Figure 53).
Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
Figure 51. SD Example Application
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 010
Enhanced definition (ED) or high definition (HD) YCrCb data
can be input in an interleaved 4:2:2 format over an 8-bit DDR
bus. The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
HSYNC
the
codes are also supported.
8-Bit 4:2:2 ED/HD YCrCb Mode (DDR)
In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input
on Pin P7 to Pin P0 on either the rising or falling edge of CLKIN.
Pin P0 is the LSB.
and
VSYNC
pins. Embedded EAV/SAV timing
Figure 54. ED/HD-DDR Example Application
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format over
an 8-bit bus rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
The interleaved pixel data is input on Pin P7 to Pin P0, with Pin P0
being the LSB.
Figure 55. ED (at 54 MHz) Input Sequence (EAV/SAV)
Rev. I | Page 46 of 107
Page 47
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
ADV7392/ADV7393 INPUT CONFIGURATION
The ADV7392/ADV7393 support a number of different input
modes. The desired input mode is selected using Subaddress 0x01,
Bits[6:4]. The ADV7392/ADV7393 default to standard definition
(SD) mode on power-up. Table 36 provides an overview of all
possible input configurations. Each input mode is described in
detail in this section.
STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
Standard definition YCrCb data can be input in 4:2:2 format over
an 8-, 10-, or 16-bit bus. SD RGB data can be input in 4:4:4 format
over a 16-bit bus.
A 27 MHz clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
HSYNC
the
codes are also supported in 8-bit and 10-bit modes.
In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin P15 to Pin P8, with Pin P8 being the LSB. The
ITU-R BT.601/656 input standard is supported.
In 10-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin P15 to Pin P6, with Pin P6 being the LSB. The ITUR BT.601/656 input standard is supported.
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with Pin P8 being the LSB.
The CrCb pixel data is input on Pin P7 to Pin P0, with Pin P0
being the LSB.
The pixel data is updated at half the rate of the clock, that is, at a
rate of 13.5 MHz (see Figure 5).
16-Bit 4:4:4 RGB Mode
Embedded EAV/SAV timing codes are not supported with SD RGB
mode. Also, master timing mode is not supported for SD RGB
input mode, therefore, external synchronization must be used.
Subaddress 0x87, Bit 7 = 1
In 16-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin P4 to Pin P0, the green pixel data is input on Pin P10 to
Pin P5, and the blue pixel data is input on Pin P15 to Pin P11.
The P0, P5, and P11 pins are the respective bus LSBs.
The pixel data is updated at half the rate of the clock, that is, at a
rate of 13.5 MHz (see Figure 6).
ADV7392/
MPEG2
DECODER
YCrCb
Figure 56. SD Example Application
2
27MHz
8/10
ADV7393
VSYNC,
HSYNC
CLKIN
P[15:8]/P[15:6]
SD RGB input enable (0x87[7]) = 0
SD RGB input enable (0x87[7]) = 1
ED/HD input format (0x33[2]) = 0
ED/HD input format (0x33[2]) = 1
ED/HD input format (0x33[2]) = 0
ED/HD input format (0x33[2]) = 1
06234-054
Page 48
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
3FF
0000
X
Y
Y0
Y1
Cr0
CLKIN
NOTES
1. SUBADDRESS 0x01 [2:1] S HOULD BE SET TO 00 IN THI S CAS E .
2. 10-BIT MODE IS ENABL E D US ING SUBADDRESS 0x33, BIT 2.
P[15:8]/
P]15:6]
Cb0
06234-055
3FF0000XYCb0Cr0Y1
CLKIN
P[15:8]/
P[15:P6]
Y0
NOTES
1. SUBADDRESS 0x01 [2:1] S HOULD BE SET TO 11 IN THI S CAS E .
2. 10-BIT MODE IS ENABL E D US ING SUBADDRESS 0x33, BIT 2.
06234-056
M
PEG2
DECODER
CLKIN
P[7:0]
P[15:8]
INTERLACED TO
PROGRESSIVE
YCrCb
ADV7392/
ADV7393
VSYNC
HSYNC
8
CrCb
8
Y
2
06234-057
MPEG2
DECODER
CLKIN
P[15:8]/P[15:6]
INTERLACED TO
PROGRESSIVE
YCrCb
ADV7392/
ADV7393
VSYNC
HSYNC
8/10
2
YCrCb
06234-058
3FF0000XYCb0
Y0Y1Cr0
CLKIN
P[15:8]/P[15:6]
NOTES
1. 10-BIT MODE IS ENABL E D US ING SUBADDRESS 0x33, BIT 2.
06234-059
MPEG2
DECODER
CLKIN
P[15:8]/P[15:6]
54MHz
ADV7392/
ADV7393
VSYNC,
HSYNC
YCrCb
8/10
YCrCb
INTERLACE D TO
PROGRESSIVE
06234-060
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 001 or 010
ED or HD YCrCb data can be input in a 4:2:2 format over an
8-/10-bit DDR bus or a 16-bit SDR bus.
The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
HSYNC
the
codes are also supported.
16-Bit 4:2:2 YCrCb Mode (SDR)
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with P8 being the LSB.
The CrCb pixel data is input on Pin P7 to Pin P0, with Pin P0
being the LSB.
8-/10-Bit 4:2:2 YCrCb Mode (DDR)
In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is
input on Pin P15 to Pin P8/P6 on either the rising or falling
edge of CLKIN. Pin P8/P6 is the LSB.
The CrCb pixel data is also input on Pin P15 to Pin P8/P6
on the opposite edge of CLKIN. P8/P6 is the LSB.
The 10-bit mode is enabled using Subaddress 0x33, Bit 2.
Whether the Y data is clocked in on the rising or falling edge of
CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 57
and Figure 58).
Figure 57. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
and
VSYNC
pins. Embedded EAV/SAV timing
Figure 59. ED/HD-SDR Example Application
Figure 60. ED/HD-DDR Example Application
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format on
an 8-/10-bit bus at a rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
The interleaved pixel data is input on Pin P15 to Pin P8/P6,
with Pin P8/P6 being the LSB.
The 10-bit mode is enabled using Subaddress 0x33, Bit 2.
Figure 58. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
Figure 61. ED (at 54 MHz) Input Sequence (EAV/SAV)
Figure 62 ED (at 54 MHz) Example Application
Rev. I | Page 48 of 107
Page 49
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
1 1 Y
Pr
Pb
OUTPUT CONFIGURATION
The ADV7390/ADV7391/ADV7392/ADV7393 support a number of different output configurations. Table 37 to Ta b l e 39 list all possible
output configurations.
Table 37. SD Output Configurations
RGB/YPrPb Output Select1
(Subaddress 0x02, Bit 5)
0 0 0 G B R
1 0 0 Y Pb Pr
1 1 0 CVBS Luma Chroma
1 1 1 CVBS Chroma Luma
1
If SD RGB output is selected, a color reversal is possible using Subaddress 0x86, Bit 7.
Table 38. ED/HD Output Configurations
RGB/YPrPb Output Select
(Subaddress 0x02, Bit 5)
0 0 G B R
0 1 G R B
1 0 Y Pb Pr
SD DAC Output 1
(Subaddress 0x82, Bit 1)
ED/HD Color DAC Swap
(Subaddress 0x35, Bit 3) DAC 1 DAC 2 DAC 3
ED/HD Color DAC Swap
(Subaddress 0x35, Bit 3) DAC 1 DAC 2 DAC 3
Rev. I | Page 49 of 107
Page 50
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
001/010
ED 1 X X ED (1×)
001/010
HD 0 X 0 HD (4×)
111
ED (at 54 MHz)
1 X X
ED (at 54 MHz) (1×)
DESIGN FEATURES
OUTPUT OVERSAMPLING
The ADV7390/ADV7391/ADV7392/ADV7393 include an onchip phase-locked loop (PLL) that allows for oversampling of
SD, ED, and HD video data. By default, the PLL is disabled. The
PLL can be enabled using Subaddress 0x00, Bit 1 = 0.
Table 40 shows the various oversampling rates supported in the
ADV7390/ADV7391/ADV7392/ADV7393.
External Sync Polarity
For SD and ED/HD modes, the ADV7390/ADV7391/ADV7392/
ADV7393 parts typically expect HS and VS to be low during
their respective blanking periods. However, when the CEA861
Table 40. Output Oversampling Modes and Rates
Input Mode
(0x01, Bits[6:4])
000 SD 1 X X SD (2×)
000 SD 0 1 X SD (8×)
000 SD 0 0 X SD (16×)
PLL and Oversampling
Control (0x00, Bit 1)
SD/ED Oversample Rate
Select (0x0D, Bit 3)
compliance bit is enabled (0x39, Bit 5 for ED/HD modes and
0x86, Bit 3 for SD modes), the part expects the HS or VS to be
active low or high depending on the input format selected
(0x30, Bits[7:3]).
If a different polarity other than the default is required for
ED/HD modes, 0x3A, Bits[2:0] can be used to invert PHSYNCB,
PVSYNCB or PBLANKB individually regardless of whether
CEA-861-B mode is enabled. It is not possible to invert
S_HSYNC or S_VSYNC.
1
HD Oversample Rate
Select (0x31, Bit 1)1
Oversampling Mode
and Rate
001/010 ED 0 1 X ED (4×)
001/010 ED 0 0 X ED (8×)
001/010 HD 1 X X HD (1×)
001/010 HD 0 X 1 HD (2×)
111 ED (at 54 MHz) 0 1 X ED (at 54 MHz) (4×)
111 ED (at 54 MHz) 0 0 X ED (at 54 MHz) (8×)
1
X = don’t care
Rev. I | Page 50 of 107
Page 51
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
HD INTERLACE EXTERNAL HSYNC AND VSYNC
CONSIDERATIONS
If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 01
or higher, the user should set Subaddress 0x02, Bit 1 to high.
To ensure exactly correct timing in HD interlace modes when
HSYNC
using
set to low, the first active pixel on each line is masked in HD
interlace modes and the Pr and Pb outputs are swapped when
using the YCrCb 4:2:2 input format. Setting Subaddress 0x02,
Bit 1 to low causes the encoder to behave in the same way as the
first version of silicon (that is, this setting is backward
compatible).
If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 00,
the setting of Subaddress 0x02, Bit 1 has no effect. In this
version of the encoder, the first active pixel is masked and the
Pr and Pb outputs are swapped when using YCrCb 4:2:2 input
format. To avoid these limitations, use the newer revision of
silicon or use a different type of synchronization.
These considerations apply only to the HD interlace modes
with external
mode is not affected and always has exactly correct timing).
There is no negative effect in setting Subaddress 0x02, Bit 0 to
high, and this bit can remain high for all the other video
standards.
VSYNC
and
HSYNC
synchronization signals. If this bit is
VSYNC
and
synchronization (EAV/SAV
ED/HD TIMING RESET
Subaddress 0x34, Bit 0
An ED/HD timing reset is achieved by setting the ED/HD
timing reset control bit (Subaddress 0x34, Bit 0) to 1. In this
state, the horizontal and vertical counters remain reset. When
this bit is set back to 0, the internal counters resume counting.
This timing reset applies to the ED/HD timing counters only.
SD SUBCARRIER FREQUENCY LOCK
Subcarrier Frequency Lock (SFL) Mode
In subcarrier frequency lock (SFL) mode (Subaddress 0x84,
Bits[2:1] = 11), the ADV7390/ADV7391/ADV7392/ADV7393
can be used to lock to an external video source. The SFL mode
allows the ADV7390/ADV7391/ADV7392/ADV7393 to
automatically alter the subcarrier frequency to compensate for
line length variations. When the part is connected to a device
such as an ADV7403 video decoder that outputs a digital data
stream in the SFL format, the part automatically changes to the
compensated subcarrier frequency on a line-by-line basis (see
Figure 63). This digital data stream is 67 bits wide, and the
subcarrier is contained in Bit 0 to Bit 21. Each bit is two clock
cycles long.
ADV7390/ADV7391/
ADV7392/ADV7393
CLKIN
LLC1
COMPOSI TE
VIDEO
H/L TRANSI TION
COUNT START
RTC
TIME SLOT 01
1
FOR EXAMPLE, VCR OR CABLE.
2
FSCPLL INCREMENT IS 22 BITS LONG. VALUE LOADED I NTO ADV7390/ADV7391/ADV 7392/ADV7393 FSC DDS REGISTER IS
F
PLL INCREMENTS BITS[21:0] PL US BITS[ 0:9] OF SUBCARRIER F REQUENC Y REGIS TERS.
SC
3
SEQUENCE BI T
PAL: 0 = LINE NORMAL, 1 = LI NE INVERTED
NTSC: 0 = NO CHANGE
4
RESET ADV7390/ADV7391/ADV7392/ADV7393 DDS.
5
REFER TO THE ADV7390/ADV7391 AND ADV7392/ADV7393 INPUT CO NFIGUR ATION TABLES FOR PIXEL DATA PIN ASSIGNMENT S.
1
128
ADV7403
VIDEO
DECODER
SUBCARRIER
LOW
130
14 BITS
PHASE
SFL
P19 TO
P10
142119
4 BITS
RESERVED
SFL
PIXEL PORT
F
SC
VAL ID
SAMPLE
DAC 1
DAC 2
DAC 3
5
PLL INCREMENT
INVALID
SAMPLE
2
SEQUENCE
BIT
0
8/LINE
LOCKED
CLOCK
RESET BIT
3
RESERVED
6768
5 BITS
RESERVED
4
06234-064
Figure 63. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)
Rev. I | Page 51 of 107
Page 52
32
2
MHz27
×
=
linevideooneincyclesclockof
Number
linevideo
oneinperiodssubcarrierofNumber
RegisterFrequencySubcarrier
569408543
2
1716
5.227
32
=×
=ValueRegisterSubcarrier
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
SD VCR FF/RW SYNC
Subaddress 0x82, Bit 5
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for nonstandard input video, that is, in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields is reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields is
reached. Conventionally, this means that the output video has
corrupted field signals because one signal is generated by the
incoming video and another is generated when the internal
line/field counters reach the end of a field.
When the VCR FF/RW sync control is enabled (Subaddress 0x82,
Bit 5), the line/field counters are updated according to the
incoming
the incoming
VSYNC
VSYNC
signal and when the analog output matches
signal. This control is available in all
slave-timing modes except Slave Mode 0.
VERTICAL BLANKING INTERVAL
Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4
The ADV7390/ADV7391/ADV7392/ADV7393 are able to
accept input data that contains vertical blanking interval (VBI)
data (such as CGMS, WSS, VITS) in SD, ED, and HD modes.
If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD; Subaddress
0x83, Bit 4 for SD), VBI data is not present at the output and the
entire VBI is blanked. These control bits are valid in all master
and slave timing modes.
For the SMPTE 293M (525p) standard, VBI data can be inserted
on Line 13 to Line 42 of each frame or on Line 6 to Line 43 for
the ITU-R BT.1358 (625p) standard. VBI data can be present on
Line 10 to Line 20 for NTSC and on Line 7 to Line 22 for PAL.
In SD Timing Mode 0 (slave option), if VBI is enabled, the
blanking bit in the EAV/SAV code is overwritten. It is possible
to use VBI in this timing mode as well.
If CGMS is enabled and VBI is disabled, the CGMS data is,
nevertheless, available at the output.
SD SUBCARRIER FREQUENCY CONTROL
Subaddress 0x8C to Subaddress 0x8F
The ADV7390/ADV7391/ADV7392/ADV7393 are able to
generate the color subcarrier used in CVBS and S-Video (Y-C)
outputs from the input pixel clock. Four 8-bit registers are used
to set up the subcarrier frequency. The value of these registers is
calculated using the following equation:
where the sum is rounded to the nearest integer.
Rev. I | Page 52 of 107
For example, in NTSC mode:
where:
Subcarrier Register Value = 569408543d = 0×21F07C1F
SD F
Register 0: 0x1F
SC
SD F
Register 1: 0x7C
SC
SD F
Register 2: 0xF0
SC
SD F
Register 3: 0x21
SC
Programming the FSC
The subcarrier frequency register value is divided into four FSC
registers as shown in the previous example. The four subcarrier
frequency registers must be updated sequentially, starting with
Subcarrier Frequency Register 0 and ending with Subcarrier
Frequency Register 3. The subcarrier frequency updates only
after the last subcarrier frequency register byte is received by
the ADV7390/ADV7391/ADV7392/ADV7393. The SD input
standard autodetection feature must be disabled.
Typical FSC Values
Table 41 outlines the values that should be written to the
subcarrier frequency registers for NTSC and PAL B/D/G/H/I.
The ADV7390/ADV7391/ADV7392/ADV7393 support an SD
noninterlaced mode. Using this mode, progressive inputs at
twice the frame rate of NTSC and PAL (240p/59.94 Hz and
288p/50 Hz, respectively) can be input into the ADV7390/
ADV7391/ADV7392/ADV7393. The SD noninterlaced mode
can be enabled using Subaddress 0x88, Bit 1.
A 27 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes or external horizontal and
vertical synchronization signals provided on the
VSYNC
pins can be used to synchronize the input pixel data.
All input configurations, output configurations, and features
available in NTSC and PAL modes are available in SD noninterlaced mode. For 240p/59.94 Hz input, the ADV7390/ADV7391/
ADV7392/ADV7393 should be configured for NTSC operation
and Subaddress 0x88, Bit 1 should be set to 1.
For 288p/50 Hz input, the ADV7390/ADV7391/ADV7392/
ADV7393 should be configured for PAL operation and
Subaddress 0x88, Bit 1 should be set to 1.
HSYNC
and
Page 53
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Y
C
r
Y
FF0000X
Y
8
0
10801
0
FF00FFABABA
B
801
0
8
0
10FF0
0
0
0
XYC
b
Y
C
r
C
b
Y
C
b
Y
C
r
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
272 CLOCK
1280 CLOCK
4 CLOCK
4 CLOCK
344 CLOCK
1536 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/ 60Hz )
PAL SYSTEM
(625 LINES/ 50Hz )
Y
06234-065
FIELD
PIXE
L
D
ATA
P
AL
= 308 CLOCK CYCLE S
NTSC = 236 CLOCK CY CLES
Cb
Y
CrY
HSYNC
06234-066
SD SQUARE PIXEL MODE
Subaddress 0x82, Bit 4
The ADV7390/ADV7391/ADV7392/ADV7393 support an SD
square pixel mode (Subaddress 0x82, Bit 4). For NTSC
operation, an input clock of 24.5454 MHz is required. The active
resolution is 640 × 480. For PAL operation, an input clock of
29.5 MHz is required. The active resolution is 768 × 576.
For CVBS and S-Video (Y-C) outputs, the SD subcarrier
frequency registers must be updated to reflect the input clock
frequency used in SD square pixel mode. The SD input standard
autodetection feature must be disabled in SD square pixel
mode. In square pixel mode, the timing diagrams shown in
Figure 64 and Figure 65 apply.
Subaddress 0x80, Bits[7:2]; Subaddress 0x82, Bit 0
The Y filter supports several different frequency responses,
including two low-pass responses, two notch responses, an
extended (SSAF) response with or without gain boost attenuation, a CIF response, and a QCIF response. The PrPb filter
supports several different frequency responses, including six
low-pass responses, a CIF response, and a QCIF response, as
shown in Figure 38 and Figure 39.
If SD Luma SSAF gain is enabled (Subaddress 0x87, Bit 4), there
are 13 response options in the range −4 dB to +4 dB. The desired
response can be programmed using Subaddress 0xA2. Variation
in frequency responses is shown in Figure 35 to Figure 37.
In addition to the chroma filters listed in Table 42, the
ADV7390/ADV7391/ADV7392/ADV7393 contain an SSAF
filter that is specifically designed for the color difference
component outputs, Pr and Pb. This filter has a cutoff frequency
of ~2.7 MHz and a gain of –40 dB at 3.8 MHz (see Figure 66).
This filter can be controlled with Bit 0 of Sub-address 0x82, Bit
0.
If this filter is disabled, one of the chroma filters shown in
Table 43 can be selected and used for the CVBS or luma/
chroma signal.
Pass-band ripple is the maximum fluctuation from the 0 dB response in the
pass band, measured in decibels. The pass band is defined to have 0 Hz to fc
(Hz) frequency limits for a low-pass filter and 0 Hz to f1 (Hz) and f2 (Hz) to
infinity for a notch filter, where fc, f1, and f2 are the −3 dB points.
2
3 dB bandwidth refers to the −3 dB cutoff frequency.
Figure 66. PrPb SSAF Filter
Pass-Band
Ripple (dB)
1
3 dB Bandwidth (MHz)
2
Rev. I | Page 54 of 107
Page 55
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
FREQUENC
Y (MHz)
0.5
–0.5
305
0
GAIN (dB)
1015
2025
0.4
0.1
–0.2
–0.3
–0.4
0.3
0.2
0
–0.1
06234-068
FREQUENCY (MHz)
0.5
–0.5
3050
GAIN (dB)
10152025
0.4
0.1
–0.2
–0.3
–0.4
0.3
0.2
0
–0.1
06234-069
Yellow
210
(0xD2)
146
(0x92)
16
(0x10)
Cyan
170
(0xAA)
16
(0x10)
166
(0xA6)
ED/HD Sinc Compensation Filter Response
Subaddress 0x33, Bit 3
The ADV7390/ADV7391/ADV7392/ADV7393 include a filter
designed to counter the effect of sinc roll-off in DAC 1, DAC 2,
and DAC 3 while operating in ED/HD mode. This filter is
enabled by default. It can be disabled using Subaddress 0x33, Bit 3.
The benefit of the filter is illustrated in Figure 67 and Figure 68.
Figure 67. ED/HD Sinc Compensation Filter Enabled
Table 44 shows sample color values that can be programmed
into the color registers when the output standard selection is set
to EIA770.2/EIA770.3 (Subaddress 0x30, Bits[1:0] = 00).
Table 44. Sample Color Values for EIA770.2/EIA770.3
ED/HD Output Standard Selection
Sample Color Y Value Cr Value Cb Value
White 235 (0xEB) 128 (0x80) 128 (0x80)
Black 16 (0x10) 128 (0x80) 128 (0x80)
Red 81 (0x51) 240 (0xF0) 90 (0x5A)
Green 145 (0x91) 34 (0x22) 54 (0x36)
Blue 41 (0x29) 110 (0x6E) 240 (0xF0)
Magenta 106 (0x6A) 222 (0xDE) 202 (0xCA)
COLOR SPACE CONVERSION MATRIX
Subaddress 0x03 to Subaddress 0x09
The internal color space conversion (CSC) matrix automatically
performs all color space conversions based on the input mode
programmed in the mode select register (Subaddress 0x01,
Bits[6:4]). Table 45 and Ta b l e 46 show the options available in
this matrix.
An SD color space conversion from RGB-in to YPrPb-out is
possible on the ADV7392/ADV7393. An ED/HD color space
conversion from RGB-in to YPrPb-out is not possible.
Three 8-bit registers at Subaddress 0x36 to Subaddress 0x38
are used to program the output color of the internal ED/HD
test pattern generator (Subaddress 0x31, Bit 2 = 1), whether it
be the lines of the crosshatch pattern or the uniform field test
pattern. They are not functional as color controls for external
pixel data input.
The values for the luma (Y) and color difference (Cr and Cb)
signals used to obtain white, black, and saturated primary and
complementary colors conform to the ITU-R BT.601-4
standard.
CVBS/Y-C outputs are available for all CSC combinations.
2
Available on the ADV7392/ADV7393 (40-pin devices) only.
Table 46. ED/HD Color Space Conversion Options
YPrPb/RGB Out
Input Output
(Subaddress 0x02, Bit 5)
YCrCb YPrPb 1
YCrCb RGB 0
SD Manual CSC Matrix Adjust Feature
The SD manual CSC matrix adjust feature (available for the
ADV7392 and ADV7393 only) provides custom coefficient
manipulation for RGB to YPbPr conversion (for YPbPr to RGB
conversion, this matrix adjustment is not available).
Normally, there is no need to modify the SD matrix coefficients
because the CSC matrix automatically performs the color space
conversion based on the output color space selected (see Table 46).
Note that Bit 7 in subaddress 0x87 must be set to enable RGB
input and, therefore, use the CSC manual adjustment.
Page 56
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
c3
0xC7
0x70
0x05
0x4E
The SD CSC matrix scalar uses the following equations:
Y = (a1 × R) + (a2 × G) + (a3 × B) + a4
Pr = (b1 × R) + (b2 × G) + (b3 × B) + b4
Pb = (c1 × R) + (c2 × G) + (c3 × B) + c4
The coefficients and their default values are located in the
registers shown in Table 47.
On power-up, the CSC matrix is programmed with the default
values shown in Table 48.
The ED/HD manual CSC matrix adjust feature provides custom
coefficient manipulation for color space conversions and is used
in ED and HD modes only. The ED/HD manual CSC matrix
adjust feature can be enabled using Subaddress 0x02, Bit 3.
Normally, there is no need to enable this feature because the CSC
matrix automatically performs the color space conversion based
on the input mode chosen (ED or HD) and the output color
space selected (see Table 46). For this reason, the ED/HD
manual CSC matrix adjust feature is disabled by default.
If RGB output is selected, the ED/HD CSC matrix scalar uses
the following equations:
R = GY × Y + RV × Pr
G = GY × Y − (GU × Pb) − (GV × Pr)
B = GY × Y + BU × Pb
Note that subtractions are implemented in the hardware.
If YPrPb output is selected, the following equations are used:
Y = GY × Y
Pr = RV × Pr
Pb = BU × Pb
where:
GY = Subaddress 0x05, Bits[7:0] and Subaddress 0x03, Bits[1:0].
GU = Subaddress 0x06, Bits[7:0] and Subaddress 0x04, Bits[7:6].
GV = Subaddress 0x07, Bits[7:0] and Subaddress 0x04, Bits[5:4].
BU = Subaddress 0x08, Bits[7:0] and Subaddress 0x04, Bits[3:2].
RV = Subaddress 0x09, Bits[7:0] and Subaddress 0x04, Bits[1:0].
0x06 0x0E
0x07 0x24
0x08 0x92
0x09 0x7C
When the ED/HD manual CSC matrix adjust feature is
enabled, the default coefficient values in Subaddress 0x03
to Subaddress 0x09 are correct for the HD color space only.
The color components are converted according to the following
1080i and 720p standards (SMPTE 274M, SMPTE 296M):
R = Y + 1.575Pr
G = Y − 0.468Pr − 0.187Pb
B = Y + 1.855Pb
The conversion coefficients should be multiplied by 315 before
being written to the ED/HD CSC matrix registers. This is
reflected in the default values for GY = 0x13B, GU = 0x03B,
GV = 0x093, BU = 0x248, and RV = 0x1F0.
If the ED/HD manual CSC matrix adjust feature is enabled and
another input standard (such as ED) is used, the scale values for
GY, GU, GV, BU, and RV must be adjusted according to this
input standard color space. The user should consider that the
color component conversion may use different scale values.
For example, SMPTE 293M uses the following conversion:
R = Y + 1.402Pr
G = Y − 0.714Pr − 0.344Pb
B = Y + 1.773Pb
The programmable CSC matrix is used for external ED/HD
pixel data and is not functional when internal test patterns are
enabled.
Programming the CSC Matrix
If custom manipulation of the ED/HD CSC matrix coefficients
is required for a YCrCb-to-RGB color space conversion, use the
following procedure:
1. Enable the ED/HD manual CSC matrix adjust feature
(Subaddress 0x02, Bit 3).
2. Set the output to RGB (Subaddress 0x02, Bit 5).
3. Disable sync on PrPb (Subaddress 0x35, Bit 2).
4. Enable sync on RGB (optional) (Subaddress 0x02, Bit 4).
The GY value controls the green signal output level, the BU
value controls the blue signal output level, and the RV value
controls the red signal output level.
Rev. I | Page 56 of 107
Page 57
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
SD LUMA AND COLOR SCALE CONTROL
Subaddress 0x9C to Subaddress 0x9F
When enabled, the SD luma and color scale control feature can
be used to scale the SD Y, Cb, and Cr output levels. This feature
can be enabled using Subaddress 0x87, Bit 0. This feature affects
all SD output signals, that is, CVBS, Y-C, YPrPb, and RGB.
When enabled, three 10-bit registers (SD Y scale, SD Cb scale,
and SD Cr scale) control the scaling of the SD Y, Cb, and Cr
output levels. The SD Y scale register contains the scaling factor
used to scale the Y level from 0.0 to 1.5 times its initial level.
The SD Cb scale and SD Cr scale registers contain the scaling
factors to scale the Cb and Cr levels from 0.0 to 2.0 times their
initial levels, respectively.
The values to be written to these 10-bit registers are calculated
using the following equation:
Y, Cb, or Cr Scale Value = Scale Factor × 512
For example, if Scale Factor = 1.3
Y, Cb, or Cr Scale Value = 1.3 × 512 = 665.6
Y, Cb, or Cr Scale Value = 666 (rounded to the nearest integer)
It is recommended that the SD luma scale saturation feature
(Subaddress 0x87, Bit 1) be enabled when scaling the Y output
level to avoid excessive Y output levels.
SD HUE ADJUST CONTROL
Subaddress 0xA0
When enabled, the SD hue adjust control register (Subaddress
0xA0) is used to adjust the hue on the SD composite and
chroma outputs. This feature can be enabled using Subaddress
0x87, Bit 2.
Subaddress 0xA0 contains the bits required to vary the hue of
the video data, that is, the variance in phase of the subcarrier
during active video with respect to the phase of the subcarrier
during the color burst. The
ADV7390/ADV7391/ADV7392/ADV7393 provide a range of
±22.5° in increments of 0.17578125°. For normal operation
(zero adjustment), this register is set to 0x80. Value 0xFF and
Value 0x00 represent the upper and lower limits, respectively, of
the attainable adjustment in NTSC mode. Value 0xFF and Value
0x01 represent the upper and lower limits, respectively, of the
attainable adjustment in PAL mode.
The hue adjust value is calculated using the following equation:
Hue Adjust (°) = 0.17578125° (HCR
Where HCR
= the hue adjust control register (decimal).
d
− 128)
d
For example, to adjust the hue by +4°, write 0x97 to the hue
adjust control register.
17578125.0
4
d
97x0151128
where the sum is rounded to the nearest integer.
To adjust the hue by −4°, write 0x69 to the hue adjust control
register.
17578125.0
4
d
96x0105128
where the sum is rounded to the nearest integer.
SD BRIGHTNESS DETECT
Subaddress 0xBA
The ADV7390/ADV7391/ADV7392/ADV7393 allow
monitoring of the brightness level of the incoming video data.
This feature is used to monitor the average brightness of the
incoming Y signal on a field-by-field basis. The information is
read from the I
2
C and, based on this information, the color
saturation, contrast, and brightness controls can be adjusted
(for example, to compensate for very dark pictures).
The luma data is monitored in the active video area only. The
average brightness I
every
VSYNC
2
C register is updated on the falling edge of
signal. The SD brightness detect register (Subad-
dress 0xBA) is a read-only register.
SD BRIGHTNESS CONTROL
Subaddress 0xA1, Bits[6:0]
When this feature is enabled, the SD brightness/WSS control
register (Subaddress 0xA1) is used to control brightness by
adding a programmable setup level onto the scaled Y data. This
feature can be enabled using Subaddress 0x87, Bit 3.
For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE.
For NTSC without pedestal (see Figure 69) and for PAL, the
setup can vary from −7.5 IRE to +15 IRE.
NTSC WITHOUT PEDESTAL
100 IRE
0 IRE
NO SETUP
VALUE ADDED
Figure 69. Examples of Brightness Control Values
POSITIVE SETUP
VALUE ADDED
NEGATIVE SETUP
VALUE ADDED
The SD brightness control register is an 8-bit register. The seven
LSBs of this 8-bit register are used to control the brightness
level, which can be a positive or negative value.
For example, to add a +20 IRE brightness level to an NTSC
signal with pedestal, write 0x28 to Subaddress 0xA1.
0 × (SD Brightness Value) =
0 × (IRE Value × 2.015631) =
0 × (20 × 2.015631) = 0 × (40.31262) ≈ 0x28
+7.5 IRE
–7.5 IRE
06234-070
Rev. I | Page 57 of 107
Page 58
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
CASE B
700mV
300mV
NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0x0B
CASE A
GAIN PROG RAM M E D IN DAC OUTPUT LEVEL
REGISTE RS , SUBADDRESS 0x0B
700mV
300mV
06234-071
To add a –7 IRE brightness level to a PAL signal, write 0x72 to
Subaddress 0xA1.
Values in the range of 0x3F to 0x44 may result in an invalid output signal.
SD INPUT STANDARD AUTODETECTION
Subaddress 0x87, Bit 5
The ADV7390/ADV7391/ADV7392/ADV7393 include an SD
input standard autodetect feature that can be enabled by setting
Subaddress 0x87, Bits[5:1].
When enabled, the ADV7390/ADV7391/ADV7392/ADV7393
can automatically identify an NTSC or a PAL B/D/G/H/I input
stream. The ADV7390/ADV7391/ADV7392/ADV7393
automatically update the subcarrier frequency registers with the
appropriate value for the identified standard. The ADV7390/
ADV7391/ADV7392/ADV7393 are also configured to correctly
encode the identified standard.
The SD standard bits (Subaddress 0x80, Bits[1:0]) and the
subcarrier frequency registers are not updated to reflect the
identified standard. All registers retain their default or userdefined values.
PROGRAMMABLE DAC GAIN CONTROL
Subaddress 0x0B
It is possible to adjust the DAC output signal gain up or down
from its absolute level. This is illustrated in Figure 70.
DAC 1 to DAC 3 are controlled by Register 0x0B.
In Case A of Figure 70, the video output signal is gained. The
absolute level of the sync tip and the blanking level increase
with respect to the reference video output signal. The overall
gain of the signal is increased from the reference signal.
In Case B of Figure 70, the video output signal is reduced. The
absolute level of the sync tip and the blanking level decrease
with respect to the reference video output signal. The overall
gain of the signal is reduced from the reference signal.
DOUBLE BUFFERING
Subaddress 0x33, Bit 7 for ED/HD;
Subaddress 0x88, Bit 2 for SD
Double-buffered registers are updated once per field. Double
buffering improves overall performance because modifications
to register settings are not be made during active video but take
effect prior to the start of the active video on the next field.
Using Subaddress 0x33, Bit 7, double buffering can be activated
on the following ED/HD registers: the ED/HD Gamma A and
Gamma B curves and ED/HD CGMS registers.
Using Subaddress 0x88, Bit 2, double buffering can be activated
on the following SD registers: the SD Gamma A and Gamma B
curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD
closed captioning, and SD Macrovision Bits[5:0]
(Subaddress 0xE0, Bits[5:0]).
Figure 70. Programmable DAC Gain—Positive and Negative Gain
The range of this feature is specified for ±7.5% of the nominal
output from the DACs. For example, if the output current of the
DAC is 4.33 mA, the DAC gain control feature can change this
output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%).
Rev. I | Page 58 of 107
Page 59
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
...
...
...
16)16240(
16240
16
+
−×
−
−
=γ
γ
n
n
The reset value of the control registers is 0x00; that is, nominal
DAC current is output. Table 50 is an example of how the output
current of the DACs varies for a nominal 4.33 mA output current.
Subaddress 0x44 to Subaddress 0x57 for ED/HD;
Subaddress 0xA6 to Subaddress 0xB9 for SD
Generally, gamma correction is applied to compensate for the
nonlinear relationship between signal input and output
brightness level (as perceived on a CRT). It can also be applied
wherever nonlinear processing is used.
Gamma correction uses the function
Signal
where γ is the gamma correction factor.
Gamma correction is available for SD and ED/HD video. For
both variations, there are twenty 8-bit registers. They are used
to program Gamma Correction Curve A and Gamma
Correction Curve B.
ED/HD gamma correction is enabled using Subaddress 0x35,
Bit 5. ED/HD Gamma Correction Curve A is programmed at
Subaddress 0x44 to Subaddress 0x4D, and ED/HD Gamma
Correction Curve B is programmed at Subaddress 0x4E to
Subaddress 0x57.
SD gamma correction is enabled using Subaddress 0x88, Bit 6.
SD Gamma Correction Curve A is programmed at Subaddress
0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B
is programmed at Subaddress 0xB0 to Subaddress 0xB9.
= (SignalIN)γ
OUT
Gamma correction is performed on the luma data only. The
user can choose one of two correction curves, Curve A or
Curve B. Only one of these curves can be used at a time. For
ED/HD gamma correction, curve selection is controlled using
Subaddress 0x35, Bit 4. For SD gamma correction, curve
selection is controlled using Subaddress 0x88, Bit 7.
The shape of the gamma correction curve is controlled by
defining the curve response at 10 different locations along the
curve. By altering the response at these locations, the shape of
the gamma correction curve can be modified. Between these
points, linear interpolation is used to generate intermediate
values. Considering the curve to have a total length of 256
points, the 10 programmable locations are at the following
points: 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. The
following locations are fixed and cannot be changed: 0, 16, 240,
and 255.
From the curve locations, 16 to 240, the values at the programmable locations and, therefore, the response of the gamma
correction curve, should be calculated to produce the following
result:
x
DESIRED
= (x
INPUT
)γ
where:
x
is the desired gamma corrected output.
DESIRED
x
is the linear input signal.
INPUT
γ is the gamma correction factor.
To program the gamma correction registers, calculate the
10 programmable curve values using the following formula:
where:
γn is the value to be written into the gamma correction register
for point n on the gamma correction curve.
n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224.
γ is the gamma correction factor.
For example, setting γ = 0.5 for all programmable curve data
points results in the following y
= [(8/224)
y
24
y
= [(16/224)
32
= [(32/224)
y
48
= [(48/224)
y
64
y
= [(64/224)
80
= [(80/224)
y
96
y
= [(112/224)
128
= [(144/224)
y
160
y
= [(176/224)
192
= [(208/224)
y
224
0.5
× 224] + 16 = 58
0.5
× 224] + 16 = 76
0.5
× 224] + 16 = 101
0.5
× 224] + 16 = 120
0.5
× 224] + 16 = 136
0.5
× 224] + 16 = 150
0.5
× 224] + 16 = 174
0.5
× 224] + 16 = 195
0.5
× 224] + 16 = 214
0.5
× 224] + 16 = 232
values:
n
where the sum of each equation is rounded to the nearest integer.
Rev. I | Page 59 of 107
Page 60
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
A
The gamma curves in Figure 71 and Figure 72 are examples only;
any user-defined curve in the range from 16 to 240 is acceptable.
GAMMA CORRECTIO N BLOCK OUTPUT TO A RAMP INPUT
300
250
200
150
100
CORRECTED AMPLITUDE
GAMM
50
0
0
Figure 71. Signal Input (Ramp) and Signal Output for Gamma 0.5
SIGNAL INPUT
50100150200250
SIGNAL OUTPUT
0.5
LOCATION
06234-072
GAMMA CORRECTIO N BLOCK TO A RAMP INPUT FO R
300
250
200
150
100
GAMMA CORRECTED AMPL ITUDE
50
0
0
Figure 72. Signal Input (Ramp) and Selectable Output Curves
VARIOUS GAMMA VALUES
0.3
0.5
T
U
P
1.5
N
I
L
A
N
G
I
S
50100150200250
1.8
LOCATION
06234-073
ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER
CONTROLS
Subaddress 0x40; Subaddress 0x58 to Subaddress 0x5D
There are three filter modes available on the ADV7390/ADV7391/
ADV7392/ADV7393: sharpness filter mode and two adaptive
filter modes.
ED/HD Sharpness Filter Mode
To enhance or attenuate the Y signal in the frequency ranges
shown in Figure 73, the ED/HD sharpness filter must be
enabled (Subaddress 0x31, Bit 7 = 1) and the ED/HD adaptive
filter must be disabled (Subaddress 0x35, Bit 7 = 0).
To select one of the 256 individual responses, the corresponding
gain values, ranging from −8 to +7 for each lter, must be
programmed into the ED/HD sharpness filter gain register at
Subaddress 0x40.
ED/HD Adaptive Filter Mode
In ED/HD adaptive filter mode, the following registers are used:
ED/HD Adaptive Filter Threshold A
ED/HD Adaptive Filter Threshold B
ED/HD Adaptive Filter Threshold C
ED/HD Adaptive Filter Gain 1
ED/HD Adaptive Filter Gain 2
ED/HD Adaptive Filter Gain 3
ED/HD sharpness filter gain
To activate the adaptive filter control, the ED/HD sharpness
filter and the ED/HD adaptive filter must be enabled
(Subaddress 0x31, Bit 7 = 1, and Subaddress 0x35, Bit 7 = 1,
respectively).
The derivative of the incoming signal is compared to the three
programmable threshold values: ED/HD adaptive filter
(Threshold A, Threshold B, and Threshold C ) registers
(Subaddress 0x5B, Subaddress 0x5C, and Subaddress 0x5D).
The recommended threshold range is 16 to 235, although any
value in the range of 0 to 255 can be used.
The edges can then be attenuated with the settings in the
ED/HD adaptive filter (Gain 1, Gain 2, and Gain 3) registers
(Subaddress 0x58, Subaddress 0x59 and Subaddress 0x5A), and
the ED/HD sharpness filter gain register (Subaddress 0x40).
There are two adaptive filter modes available. The mode is
selected using the ED/HD adaptive filter mode control
(Subaddress 0x35, Bit 6) as follows:
Mode A is used when the ED/HD adaptive filter mode
control is set to 0. In this case, Filter B (LPF) is used in the
adaptive filter block. In addition, only the programmed
values for Gain B in the ED/HD sharpness filter gain
register and ED/HD adaptive filter (Gain 1, Gain 2, and
Gain 3) registers are applied when needed. The Gain A
values are fixed and cannot be changed.
Mode B is used when ED/HD adaptive filter mode control is
set to 1. In this mode, a cascade of Filter A and Filter B is used.
Both settings for Gain A and Gain B in the ED/HD sharpness
filter gain register and ED/HD adaptive filter (Gain 1, Gain 2,
and Gain 3) registers become active when needed.
Rev. I | Page 60 of 107
Page 61
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
S
SHARPNESS AND ADAPTIVE FILTER CONTROL BLO CK
FREQUENCY ( MHz)
FILTER A RESPONSE (Gain Ka)
1.5
1.4
1.3
1.2
1.1
1.0
0.9
MAGNITUDE
0.8
0.7
0.6
0.5
Figure 73. ED/HD Sharpness and Adaptive Filter Control
FREQUENCY (MHz)
FILTER B RESPONSE (Gain Kb)
1.6
1.5
1.4
1.3
1.2
1.1
MAGNITUDE RESPONSE (Linear Scale)
1.0
02
FREQUENCY RESPONSE IN SHARPNESS
FILTER MODE WIT H Ka = 3 AND Kb = 7
6
4
FREQUENCY (MHz )
8
1012
06234-074
INPUT
IGNAL
STEP
1.5
1.4
1.3
1.2
1.1
1.0
0.9
MAGNITUDE
0.8
0.7
0.6
0.5
R2
R4
1
CH1 500mVM 4.00µsCH1
REF A500mV 4.00 µs1
Block
9.99978ms
ALL FIELDS
Figure 74. ED/HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values
ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER
APPLICATION EXAMPLES
Sharpness Filter Application
The ED/HD sharpness filter can be used to enhance or
attenuate the Y video output signal. The register settings in
Table 51 are used to achieve the results shown in Figure 74.
Input data is generated by an external signal source.
Table 51. ED/HD Sharpness Control Settings for Figure 74
Subaddress Register Setting Reference1
0x00 0xFC
0x01 0x10
0x02 0x20
0x30 0x00
0x31 0x81
0x40 0x00 a
0x40 0x08 b
0x40 0x04 c
0x40 0x40 d
0x40 0x80 e
0x40 0x22 f
1
See Figure 74.
Rev. I | Page 61 of 107
a
1
b
R1
c
R2
CH1 500mVM 4.00µsCH1
REF A500mV 4. 00µs1
9.99978ms
ALL FIELDS
Adaptive Filter Control Application
The register settings in Table 52 are used to obtain the results
shown in Figure 76, that is, to remove the ringing on the input
Y signal, as shown in Figure 75. Input data is generated by an
external signal source.
In DNR mode, if the absolute value of the filter output is
smaller than the threshold, it is assumed to be noise. A
programmable amount (coring gain border, coring gain data) of
this noise signal is subtracted from the original signal. In DNR
sharpness mode, if the absolute value of the filter output is less
than the programmed threshold, it is assumed to be noise as
before. However, if the level exceeds the threshold, now being
identified as a valid signal, a fraction of the signal (coring gain
border, coring gain data) is added to the original signal to boost
high frequency components and sharpen the video image.
In MPEG systems, it is common to process the video information
06234-076
Figure 75. Input Signal to ED/HD Adaptive Filter
in blocks of 8 pixels × 8 pixels for MPEG2 systems or 16 pixels
× 16 pixels for MPEG1 systems (block size control). DNR can
be applied to the resulting block transition areas known to
contain noise. Generally, the block transition area contains two
pixels. It is possible to define this area to contain four pixels
(border area).
It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the DNR
block offset.
The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.
06234-077
Figure 76. Output Signal from ED/HD Adaptive Filter (Mode A)
When the adaptive filter mode is changed to Mode B
(Subaddress 0x35, Bit 6), the output shown in Figure 77
can be obtained.
06234-078
Figure 77. Output Signal from ED/HD Adaptive Filter (Mode B)
SD DIGITAL NOISE REDUCTION
Subaddress 0xA3 to Subaddress 0xA5
Digital noise reduction (DNR) is applied to the Y data only.
A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select). The absolute
value of the filter output is compared to a programmable
threshold value (DNR threshold control). There are two DNR
modes available: DNR mode and DNR sharpness mode.
Rev. I | Page 62 of 107
DAT
INPUT
Y DATA
INPUT
DNR MODE
NOISE
SIGNAL PATH
INPUT FILTER
BLOCK
MAIN SIGNAL PATH
DNR
SHARPNESS
MODE
NOISE
SIGNAL PATH
INPUT FILTER
BLOCK
MAIN SIGNAL PATH
Figure 78. SD DNR Block Diagram
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
GAIN
CORING G AIN DATA
CORING GAI N BORDER
FILTER
OUTPUT
< THRESHOL D?
FILTER OUTPUT
> THRESHOLD
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
GAIN
CORING GAI N DATA
CORING G AIN BORDER
FILTER
OUTPUT
> THRESHOLD?
FILTER OUTPUT
< THRESHOLD
SUBTRACT
SIGNAL I N
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
–
+
DNR OUT
ADD SIGNAL
ABOVE
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
+
+
DNR OUT
06234-079
Page 63
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
OXXXXXXOOXXXXXXO
OXXXXXXOOXXXXXXO
OXXXXXXOOXXXXXXO
DNR27 T
O DNR24 = 0x01
OFFSET CAUSED
B
Y V
ARIA
TIONS IN
INPUT TIMING
APP
LY BORDER
CORING GAIN
APPL
Y DATA
CORING GAIN
06234-080
720 × 485 PIXELS
(NTSC)
8 × 8 PIXEL BLOCK
TWO-PIXEL
BORDER
DATA
8 × 8 PIXEL BLOCK
06234-081
FI
LTER C
FIL
TER B
FILTER A
FIL
TER D
FREQUENC
Y (MHz)
0
0.2
0.4
0.6
MAGNITUDE
0.8
1.0
0
1
2
3
4
5
6
06234-082
Coring Gain Border—Subaddress 0xA3, Bits[3:0]
These four bits are assigned to the gain factor applied to border
areas. In DNR mode, the range of gain values is 0 to 1 in
increments of 1/8. This factor is applied to the DNR filter
output that lies below the set threshold range. The result is then
subtracted from the original signal.
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output that lies above the threshold range. The result is added to
the original signal.
Coring Gain Data—Subaddress 0xA3, Bits[7:4]
These four bits are assigned to the gain factor applied to the luma
data inside the MPEG pixel block. In DNR mode, the range of
gain values is 0 to 1 in increments of 1/8. This factor is applied
to the DNR filter output that lies below the set threshold range.
The result is then subtracted from the original signal.
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output that lies above the threshold range. The result is added to
the original signal.
Block Size—Subaddress 0xA4, Bit 7
This bit is used to select the size of the data blocks to be
processed. Setting the block size control function to Logic 1
defines a 16 pixel × 16 pixel data block, and Logic 0 defines an
8 pixel × 8 pixel data block, where one pixel refers to two clock
cycles at 27 MHz.
DNR Input Select—Subaddress 0xA5, Bits[2:0]
These three bits are assigned to select the filter that is applied to
the incoming Y data. The signal that lies in the pass band of the
selected filter is the signal processed by DNR. Figure 81 shows
the filter responses selectable with this control.
Figure 79. SD DNR Offset Control
DNR Threshold—Subaddress 0xA4, Bits[5:0]
These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.
Border Area—Subaddress 0xA4, Bit 6
When this bit is set to Logic 1, the block transition area can be
defined to consist of four pixels. If this bit is set to Logic 0, the
border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.
Figure 80. SD DNR Border Area
DNR Mode—Subaddress 0xA5, Bit 3
This bit controls the DNR mode selected. Logic 0 selects DNR
mode; Logic 1 selects DNR sharpness mode.
DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.
In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.
When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal because this data is assumed to be valid data and
not noise. The overall effect is that the signal is boosted (similar
to using the extended SSAF filter).
Block Offset Control—Subaddress 0xA5, Bits[7:4]
Four bits are assigned to this control, which allows a shift in the
data block of 15 pixels maximum. The coring gain positions are
fixed. The block offset shifts the data in steps of one pixel such
that the border coring gain factors can be applied at the same
Rev. I | Page 63 of 107
position regardless of variations in input timing of the data.
Figure 81. SD DNR Input Select
Page 64
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
100 IRE
0 IRE
100 IRE
12.5 IRE
87.5 IRE
0 IRE
50 IRE
LUM
A
CHANNEL
WITH
AC
TIVE VIDEO EDGE
DISABLED
LUMA
CHANNE
L
WITH
AC
TIVE VIDEO EDGE
ENABLED
06234-083
VOLTS
024
F2
L135
681012
IRE:FLT
–50
0
0
50
100
0.5
06234-084
VOL
TS
02–24
681012
F2
L135
IRE:FLT
–50
0
50
100
0
0.5
06234-085
SD ACTIVE VIDEO EDGE CONTROL
Subaddress 0x82, Bit 7
The ADV7390/ADV7391/ADV7392/ADV7393 are able to
control fast rising and falling signals at the start and end of
active video to minimize ringing.
When the active video edge control feature is enabled
(Subaddress 0x82, Bit 7 = 1), the first three pixels and the last
three pixels of the active video on the luma channel are scaled
so that maximum transitions on these pixels are not possible.
At the start of active video, the first three pixels are multiplied
by 1/8, 1/2, and 7/8, respectively. Approaching the end of active
video, the last three pixels are multiplied by 7/8, 1/2, and 1/8,
respectively. All other active video pixels pass through unprocessed.
Figure 82. Example of Active Video Edge Functionality
Figure 83. Example of Video Output with Subaddress 0x82, Bit 7 = 0
Figure 84. Example of Video Output with Subaddress 0x82, Bit 7 = 1
Rev. I | Page 64 of 107
Page 65
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Signal
Pin
Condition
X X 0
1
See the SD Timing
EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For timing synchronization purposes, the ADV7390/ADV7391/ADV7392/ADV7393 are able to accept either EAV/SAV time codes
embedded in the input pixel data or external synchronization signals provided on the
possible to output synchronization signals on the
HSYNC
and
VSYNC
pins (see Table 54 to Tabl e 56).
HSYNC
Table 53. Timing Synchronization Signal Input Options
Signal Pin Condition
HSYNC
SD
SD
ED/HD
ED/HD
1
SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).
pulse is aligned with the falling edge of the embedded
SD Sync
Output Enable
(Subaddress 0x02,
Bit 6)
SD Sync
Output Enable
(Subaddress
0x02, Bit 6) Video Standard
standards
progressive
standards
VSYNC
and
Signal on
Pipelined SD
Pipelined ED/HD
Pipelined ED/HD
pins (see Table 53). It is also
HSYNC Pin
HSYNC
HSYNC
HSYNC
based on AV Code H bit
Pipelined ED/HD
HSYNC
based on horizontal
counter
HSYNC
Signal on
Pipelined SD
Pipelined ED/HD
VSYNC Pin
VSYNC
/field
VSYNC
or field signal
Pipelined field signal
based on AV Code F bit
VSYNC
Pipelined
based
on AV Code V bit
1
1
2
2
Duration
section.
As per
timing.
Same as line
blanking interval.
Same as embedded
HSYNC
in the output video.
Duration
See the SD Timing
section.
As per
field signal timing.
Field.
Vertical blanking
interval.
1
1
HSYNC
.
VSYNC
or
Rev. I | Page 65 of 107
Page 66
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
VSYNC
ED/HD Input
Sync Format
(Subaddress
0x30, Bit 2)
X 1 1 X All ED/HD standards
X 1 1 X 525p
1
In all ED/HD standards where there is a
2
X = don’t care.
ED/HD
Control
(Subaddress
0x34, Bit 2)
ED/HD Sync
Output Enable
(Subaddress
0x02, Bit 7)
VSYNC
output, the start of the
SD Sync
Output Enable
(Subaddress
0x02, Bit 6) Video Standard
except 525p
VSYNC
pulse is aligned with the falling edge of the embedded
Signal on
Pipelined ED/HD
based on the vertical
counter
Pipelined ED/HD
based on the vertical
counter
VSYNC Pin
VSYNC
VSYNC
VSYNC
Duration
Aligned with
serration lines.
Vertical blanking
interval.
in the output video.
LOW POWER MODE
Subaddress 0x0D, Bits[2:0]
For power-sensitive applications, the ADV7390/ADV7391/
ADV7392/ADV7393 support an Analog Devices, Inc.,
proprietary low power mode of operation. To u s e this low
power mode, the DACs must be operating in full-drive mode
(R
= 510 Ω, RL = 37.5 Ω). Low power mode is not available in
SET
low-drive mode (R
= 4.12 kΩ, RL = 300 Ω). Low power mode
SET
can be independently enabled or disabled on each DAC using
Subaddress 0x0D, Bits[2:0]. Low power mode is disabled by
default on all DACs.
In low-power mode, DAC current consumption is content
dependent and, on a typical video stream, it can be reduced by
as much as 40%. For applications requiring the highest possible
video performance, low power mode should be disabled.
CABLE DETECTION
Subaddress 0x10, Bits[1:0]
The ADV7390/ADV7391/ADV7392/ADV7393 include an
Analog Devices proprietary cable detection feature. The cable
detection feature is available on DAC 1 and DAC 2 when
operating in full-drive mode (R
assuming a connected cable). The feature is not available in lowdrive mode (R
= 4.12 kΩ, RL = 300 Ω). For a DAC to be
SET
monitored, the DAC must be powered up in Subaddress 0x00.
The cable detection feature can be used with all SD, ED, and
HD video standards. It is available for all output configurations,
that is, CVBS, Y-C, YPrPb, and RGB output configurations.
For CVBS/Y-C output configurations, both DAC 1 and DAC 2
are monitored; that is, the CVBS and Y-C luma outputs are
monitored. For YPrPb and RGB output configurations, only
DAC 1 is monitored; that is, the luma or green output is
monitored.
Once per frame, the ADV7390/ADV7391/ADV7392/ADV7393
monitor DAC 1 and/or DAC 2, updating Subaddress 0x10, Bit 0
and/or Bit 1, respectively. If a cable is detected on one of the
DACs, the relevant bit is set to 0. If not, the bit is set to 1.
= 510 Ω, RL = 37.5 Ω,
SET
DAC AUTOPOWER-DOWN
Subaddress 0x10, Bit 4
For power-sensitive applications, a DAC autopower-down
feature can be enabled using Subaddress 0x10, Bit 4. This
feature is available only when the cable detection feature is
enabled.
With this feature enabled, the cable detection circuitry monitors
DAC 1 and/or DAC 2 once per frame and, if they are
unconnected, automatically powers down some or all of the
DACs. Which DAC or DACs are powered down depends on the
selected output configuration. For CVBS/Y-C output configurations, if DAC 1 is unconnected, only DAC 1 powers down. If
DAC 2 is unconnected, DAC 2 and DAC 3 power down.
For YPrPb and RGB output configurations, if DAC 1 is unconnected, all three DACs are powered down. DAC 2 is not monitored
for YPrPb and RGB output configurations.
Once per frame, DAC 1 and/or DAC 2 is monitored. If a cable is
detected, the appropriate DAC or DACs remain powered up for
the duration of the frame. If no cable is detected, the appropriate
DAC or DACs power down until the next frame, when the
process is repeated.
SLEEP MODE
Subaddress 0x00, Bit 0
In sleep mode, most of the digital I/O pins of the ADV7390/
ADV7391/ADV7392/ADV7393 are disabled. For inputs, this
means that the external data is ignored, and internally the logic
normally driven by a given input is just tied low or high. This
includes CLKIN.
For digital output pins, this means that the pin goes into tristate
(high impedance) mode.
There are some exceptions to allow the user to continue to
communicate with the part via I
SCL pins are kept alive.
Most of the analogue circuitry is powered down when in sleep
mode. In addition, the cable detect feature no longer works as
the DACs are powered down.
Sleep mode is enabled using Subaddress 0x00, Bit 0.
2
C: the
RESET
, ALSB, SDA and
Rev. I | Page 66 of 107
Page 67
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
06234-143
ADDRESS AND DATA
RUN-IN CLOCK
TELETEXT VBI LINE
45 BYTES (360 BITS) – PAL
PIXEL AND CONTROL PORT READBACK
Subaddress 0x13, Subaddress 0x14, Subaddress 0x16
The ADV7390/ADV7391/ADV7392/ADV7393 support the
readback of most digital inputs via the I
2
C MPU port. This
feature is useful for board-level connectivity testing with
upstream devices.
The pixel port (P[15:0] or P[7:0]),
HSYNC, VSYNC
, and SFL
are available for readback via the MPU port. The readback
registers are located at Subaddress 0x13, Subaddress 0x14, and
Subaddress 0x16.
When using this feature, apply a clock signal to the CLKIN pin
to register the levels applied to the input pins. The SD input
mode (Subaddress 0x01, Bits[6:4] = 000) must be selected when
using this feature.
RESET MECHANISMS
Subaddress 0x17, Bit 1
A hardware reset is activated with a high-to-low transition on
RESET
the
This resets all registers to their default values. After a hardware
reset, the MPU port is configured for I
device operation, a hardware reset is necessary after power-up.
The ADV7390/ADV7391/ADV7392/ADV7393 also have a
software reset accessible via the I
is activated by writing a 1 to Subaddress 0x17, Bit 1. This resets
all registers to their default values. This bit is self-clearing; that
is, after a 1 has been written to the bit, the bit automatically
returns to 0.
A hardware reset is necessary after power-up for correct device
operation. If no hardware reset functionality is required by the
application, the
to provide the hardware reset necessary after power-up. After
power-up, the time constant of the RC network holds the
RESET
subsequent resets can be done via software.
pin in accordance with the timing specifications.
2
C operation. For correct
2
C MPU port. A software reset
RESET
pin can be connected to an RC network
pin low long enough to cause a reset to take place. All
SD TELETEXT INSERTION
Subaddress 0xC9 to Subaddress 0xCE
The ADV7390/ADV7391/ADV7392/ADV7393 support the
insertion of teletext data, using a two pin interface, when
operating in PAL mode. Teletext insertion is enabled using
Subaddress 0xC9, Bit 0.
In accordance with the PA L WST teletext standard, teletext data
should be inserted into the ADV7390/ADV7391/ADV7392/
ADV7393 at a rate of 6.9375 Mbps. On the ADV7390/ADV7391,
the teletext data is inserted on the
ADV7392/ADV7393, the teletext data can be inserted on the
VSYNC
or P0 pin (selectable through Subaddress 0xC9, Bit 2).
When teletext insertion is enabled, a teletext request signal is
output from the ADV7390/ADV7391/ADV7392/ADV7393 to
indicate when teletext data should be inserted. The teletext
request signal is output on the SFL pin. The position (relative to
the teletext data) and width of the request signal are
configurable using Subaddress 0xCA. The request signal can
operate in either a line or bit mode. The request signal mode is
controlled using Subaddress 0xC9, Bit 1.
To account for the noninteger relationship between the teletext
insertion rate (6.9375 Mbps) and the pixel clock (27 MHz),
a teletext insertion protocol is implemented in the ADV7390/
ADV7391/ADV7392/ADV7393. At a rate of 6.9375 Mbps, the
time taken for the insertion of 37 teletext bits equates to 144
pixel clock cycles (at 27 MHz). For every 37 teletext bits
inserted into the ADV7390/ADV7391/ADV7392/ADV7393,
th
the 10
, 19th, 28th, and 37th bits are carried for three pixel clock
cycles, and the remainder are carried for four pixel clock cycles
(totaling 144 pixel clock cycles). The teletext insertion protocol
repeats every 37 teletext bits or 144 pixel clock cycles until all 360
teletext bits are inserted.
VSYNC
pin. On the
Figure 85. Teletext VBI Line
Rev. I | Page 67 of 107
Page 68
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
T
t
SYNTTXOUT
CVBS/Y
t
PD
t
HSYNC
10.2µs
TX
DATA
TTX
DEL
TTX
REQ
TTX
ST
t
SYNTTXOUT
t
PD
TTX
= 10.2µs.
= PIPELINE DELAY THROUGH ADV7390/ ADV7391/ADV7392/ ADV7393.
DEL
= TTX
REQ
TO TTX
(PROGRAMMABLE RANGE = 4 BITS [ 0 TO 15 PIXEL CLO CK CYCLES]).
DATA
PD
PROGRAMMABLE PULSE EDGES
Figure 86. Teletext Functionality Diagram
06234-144
Rev. I | Page 68 of 107
Page 69
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
On
297
(4×)
8×
> 6.5
101.5
2×
> 30
118.5
560Ω
600Ω
22pF600Ω
DAC
OUTPUT
75
Ω
BNC
OUTPUT
10
µH
560Ω
3
4
1
06234-086
560Ω
6.8pF600Ω
6.8pF
600Ω
DAC
OUTPUT
75Ω
BNC
OUTPUT
4.7µH
560Ω
3
4
1
06234-087
DAC
OUTPUT
390nH
33pF33pF
75Ω
500Ω
300Ω
75Ω
BNC
OUTPUT
500Ω
3
4
1
3
4
1
06234-088
PRINTED CIRCUIT BOARD LAYOUT AND DESIGN
UNUSED PINS
HSYNC
If the
to V
through a pull-up resistor (10 kΩ or 4.7 kΩ). Any
DD_IO
other unused digital inputs should be tied to ground. Unused
digital output pins should be left floating. DAC outputs can
either be left floating or connected to GND. Disabling these
outputs is recommended.
and
VSYNC
pins are not used, they should be tied
DAC CONFIGURATIONS
The ADV7390/ADV7391/ADV7392/ADV7393 contain three
DACs. All three DACs can be configured to operate in fulldrive mode. Full-drive mode is defined as 34.7 mA full-scale
current into a 37.5 Ω load, R
. Full drive is the recommended
L
mode of operation for the DACs.
Alternatively, all three DACs can be configured to operate in lowdrive mode. Low-drive mode is defined as 4.33 mA full-scale
current into a 300 Ω load, R
The ADV7390/ADV7391/ADV7392/ADV7393 contain an R
pin. A resistor connected between the R
.
L
SET
pin and AGND is
SET
used to control the full-scale output current and, therefore, the
output voltage levels of DAC 1, DAC 2, and DAC 3. For fulldrive operation, R
have a value of 37.5 Ω. For low-drive opera-tion, R
a value of 4.12 kΩ, and R
resistor connected to the R
must have a value of 510 Ω and RL must
SET
must have
SET
must have a value of 300 Ω. The
L
pin should have a 1% tolerance.
SET
The ADV7390/ADV7391/ADV7392/ADV7393 contain a
compensation pin, COMP. A 2.2 nF compensation capacitor
should be connected from the COMP pin to V
.
AA
VIDEO OUTPUT BUFFER AND OPTIONAL
OUTPUT FILTER
An output buffer is necessary on any DAC that operates in lowdrive mode (R
produces a range of op amps suitable for this application, for
example, the AD8061. For more information about line driver
buffering circuits, see the relevant op amp data sheet.
An optional reconstruction (anti-imaging) low-pass filter (LPF)
may be required on the ADV7390/ADV7391/ADV7392/ADV7393
DAC outputs. The filter specifications vary with the application.
The use of 16× (SD), 8× (ED), or 4× (HD) oversampling can
remove the requirement for a reconstruction filter altogether.
For applications requiring an output buffer and reconstruction
filter, the ADA4430-1 and ADA4411-3 integrated video filter
buffers should be considered.
Figure 87. Example of Output Filter for SD, 16× Oversampling
Figure 88. Example of Output Filter for ED, 8× Oversampling
Figure 89. Example of Output Filter for HD, 4× Oversampling
Rev. I | Page 69 of 107
Page 70
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
0
–10
–20
–30
–40
GAIN (dB)
–50
GROUP DELAY (Seconds)
–60
–70
–80
1M10M100M
CIRCUIT FRE QUENCY RESPO NSE
MAGNITUDE (dB)
PHASE (Degrees)
FREQUENCY ( Hz)
Figure 90. Output Filter Plot for SD, 16× Oversampling
0
–10
–20
–30
GROUP DE LAY (Seconds)
–40
–50
GAIN (dB)
–60
–70
–80
–90
1M10M100M1G
CIRCUIT FRE QUENCY RESPONSE
MAGNITUDE (dB)
FREQUENCY (Hz)
Figure 91. Output Filter Plot for ED, 8× Oversampling
0
–10
–20
GAIN (dB)
–30
–40
–50
1
Figure 92. Output Filter Plot for HD, 4× Oversampling
CIRCUIT FREQ UENCY RESPONSE
MAGNITUDE (d B)
GROUP DEL AY (Secon ds)
10100
FREQUENCY (MHz)
PHASE
(Degrees)
PHASE
(Degrees)
1G
0
–30
–60
–90
–120
–150
–180
–210
–240
480
400
320
240
160
80
0
–80
–160
–240
200
120
40
–40
–120
–200
24n
21n
18n
15n
12n
9n
6n
3n
0
18n
16n
14n
12n
10n
8n
6n
4n
2n
0
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADV7390/ADV7391/ADV7392/ADV7393 are highly
integrated circuits containing both precision analog and high
speed digital circuitry. It is designed to minimize interference
effects on the integrity of the analog circuitry by the high speed
digital circuitry. It is imperative that these same design and
layout techniques be applied to the system-level design so that
optimal performance is achieved.
The layout should be optimized for lowest noise on the
ADV7390/ADV7391/ADV7392/ADV7393 power and ground
planes by shielding the digital inputs and providing good power
supply decoupling.
06234-089
06234-090
PHASE (Degrees)
06234-091
It is recommended to use a 4-layer printed circuit board with
ground and power planes separating the signal trace layer and
the solder side layer.
Component Placement
Component placement should be carefully considered to
separate noisy circuits, such as clock signals and high speed
digital circuitry, from analog circuitry.
The external loop filter components and components connected
to the COMP and R
pins should be placed as close as possible
SET
to, and on the same side of the PCB as, the ADV7390/ADV7391/
ADV7392/ADV7393. Adding vias to the PCB to get the
components closer to the ADV7390/ADV7391/ADV7392/
ADV7393 is not recommended.
It is recommended that the ADV7390/ADV7391/ADV7392/
ADV7393 be placed as close as possible to the output connector,
with the DAC output traces as short as possible.
The termination resistors on the DAC output traces should be
placed as close as possible to and on the same side of the PCB as
the ADV7390/ADV7391/ADV7392/ADV7393. The termination
resistors should overlay the PCB ground plane.
External filter and buffer components connected to the DAC
outputs should be placed as close as possible to the ADV7390/
ADV7391/ADV7392/ADV7393 to minimize the possibility of
noise pickup from neighboring circuitry and to minimize the
effect of trace capacitance on output bandwidth. This is particularly
important when operating in low-drive mode (R
R
= 300 Ω).
L
= 4.12 kΩ,
SET
Power Supplies
It is recommended that a separate regulated supply be provided
for each power domain (V
, VDD, V
AA
, and PVDD). For
DD_IO
optimal performance, linear regulators rather than switch mode
regulators should be used. If switch mode regulators must be
used, care must be taken with regard to the quality of the output
voltage in terms of ripple and noise. This is particularly true for
the V
and PVDD power domains. Each power supply should be
AA
individually connected to the system power supply at a single
point through a suitable filtering device, such as a ferrite bead.
Rev. I | Page 70 of 107
Page 71
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Power Supply Decoupling
It is recommended that each power supply pin be decoupled
with 10 nF and 0.1 µF ceramic capacitors. The V
V
, and both VDD pins should be individually decoupled to
DD_IO
, PVDD,
AA
ground. The decoupling capacitors should be placed as close as
possible to the ADV7390/ADV7391/ADV7392/ADV7393 with
the capacitor leads kept as short as possible to minimize lead
inductance.
A 1 µF tantalum capacitor is recommended across the V
AA
supply in addition to the 10 nF and 0.1 µF ceramic capacitors.
Power Supply Sequencing
The ADV7390/ADV7391/ADV7392/ADV7393 are robust to all
power supply sequencing combin-ations. Any sequence can be
used. However, all power supplies should settle to their nominal
voltages within one second.
Digital Signal Interconnect
The digital signal traces should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal traces should not overlay the V
or PVDD power plane.
AA
Due to the high clock rates used, avoid long clock traces to the
ADV7390/ADV7391/ADV7392/ADV7393 to minimize noise
pickup.
Any pull-up termination resistors for the digital inputs should
be connected to the V
power supply.
DD_IO
Analog Signal Interconnect
DAC output traces should be treated as transmission lines with
appropriate measures taken to ensure optimal performance (for
example, impedance matched traces). The DAC output traces
should be kept as short as possible. The termination resistors on
the DAC output traces should be placed as close as possible to,
and on the same side of the PCB as, the ADV7390/ADV7391/
ADV7392/ADV7393.
To avoid crosstalk between the DAC outputs, it is recommended
that as much space as possible be left between the traces
connected to the DAC output pins. Adding ground traces
between the DAC output traces is also recommended.
ADDITIONAL LAYOUT CONSIDERATIONS FOR THE
WLCSP PACKAGE
Due to the high pad density and 0.5 mm pitch of the WLCSP, it
is not recommended that connections to inner bumps be routed
on the top PCB layer only.
The traces (track and space) must fit within the limits of the
solder mask openings. Routing all traces on the top surface
layer of the board, while possible, is usually not a feasible
solution due to the limitations of the geometries imposed by
the board fabrication technology. Given a pitch of 0.5 mm with
a typical solder mask opening diameter of 0.35 mm, there is only
a 0.15 mm distance between the solder mask openings.
An alternative to routing on the top surface is to route out on
buried layers. To achieve this, the pads are connected to the
lower layers using microvias. See the AN-617 Application Note,
MicroCSP Wafer Level Chip Scale Package for additional details
about the board layout for the WLCSP package.
Rev. I | Page 71 of 107
Page 72
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
TYPICAL APPLICATIONS CIRCUITS
V
DD_IO
PV
DD
V
AA
V
DD
PIXEL PORT INPUTS
INPUTS/OUTPUTS
EXTERNAL LOOP FILTER
PV
DD
150nF
LOOP FILTER COMPONENTS
SHOULD BE LOCATED
CLOSE TO THE EXT_LF
PIN AND ON THE
SAME SIDE OF THE PCB
AS THE ADV7390/ADV7391/
ADV7392/ADV7393.
1. FOR OPT IMUM PERFO RMANCE, EXTERNAL CO MPONENTS CONNECT ED
TO THE COMP, R
CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS, THE
ADV7390/ADV7391/ ADV7392/ADV 7393.
2
2. THE I
C DEVICE ADDRESS IS CONF IGURABLE USING THE ALSB PIN:
ALSB = 0, I
0x54 (ADV7391/ADV 7393)
ALSB = 1, I
0x56 (ADV7391/ADV 7393)
3. THE RESISTO R CONNECTED TO T HE R
TOLERANCE.
4. THE RECOMMENDED MO DE OF OPERATION FOR T HE DACs IS FULL DRIVE (R
OPTIONAL LPF
SET
DAC 1
DAC 2
DAC 3
AND DAC OUTPUT PI NS SHOULD BE LOCATED
SET
2
C DEVICE ADDRESS = 0xD4 (ADV7390/ADV7392) OR
2
C DEVICE ADDRESS = 0xD6 (ADV7390/ADV7392) OR
PIN SHOULD HAVE A 1%
SET
= 510Ω, RL = 37.5Ω).
DAC1 TO DAC3 LOW DRIVE OPTI ON
R
SET
4.12kΩ
AGND
ADA4411-3
DAC 1
DAC 2
DAC 3
LPF
300Ω
AGND
ADA4411-3
LPF
300Ω
AGND
ADA4411-3
LPF
300Ω
AGND
75Ω
75Ω
75Ω
DAC 1
DAC 2
DAC 3
06234-092
Rev. I | Page 72 of 107
Page 73
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
P0
P1
P2
P3
P4
P5
P6
P7
DGNDPG
ND
D
GNDPG
ND
0.1µF
GND_IO
0.01µF
GND_IO
33µF
GND_IO
10µF
GND_IO
FERRITE BE AD
V
DD_IO
V
DD_IO
POWER
SUPPLY
DECOUPLING
0.1µF
PGND
0.01µF
PGND
33µF
PGND
10µF
PGND
FERRITE BE AD
PV
DD
PV
DD
POWER
SUPPLY
DECOUPLING
0.1µF
AGND
0.01µF
AGND
33µF
AGND
10µF
AGND
FERRITE BE AD
V
AA
V
AA
POWER
SUPPLY
DECOUPLING
0.1µF
DGND
0.01µF
DGND
33µF10µF
DGND
FERRITE BE AD
V
DD
V
DD
POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
V
DD_IO
PV
DD
V
AA
V
DD
AD
V7390BCBZ
AGN
D
AGND
DGND
DGND
GND_IO
GND_I
O
R
SET
AGND
510Ω
COMP
V
AA
2.2nF
EXT_LF
12nF
150nF
170Ω
PV
DD
SDA
SCL
RESET
PI
XEL
PORT INPUTS
I2C PORT
D
G
N
D
V
DD
EXTERNAL LOOP FILTER
LOOP FILTER COMPONENTS
SHOULD BE LOCATED
CLOSE TO THE EXT_LF
PIN AND ON THE
SAME SIDE OF THE PCB
AS THE ADV7390.
NOTES
1. FOR OP TIMUM PERFORMANCE, EX TERNAL COMP ONENTS CONNECTED
TO THE COMP, R
SET
AND DAC OUTPUT PINS SHOULD BE LOCATED
CLOSE TO, AND ON THE S AM E S IDE OF THE P CB AS , THE ADV7390.
2. THE I
2
C DEVICE ADDRESS IS CONFI GURABLE USING THE ALSB PI N:
ALSB = 0, I
2
C DEVICE ADDRESS = 0xD4
ALSB = 1, I
2
C DEVICE ADDRESS = 0xD6
3. THE RESI S TOR CONNECT E D TO THE R
SET
PIN SHOULD HAV E A 1%
TOLERANCE.
4. THE RECOM M E NDE D M ODE OF O P E RATION FO R THE DACs IS FULL DRIVE (R
The ADV7390/ADV7391/ADV7392/ADV7393 support a copy
generation management system (CGMS) that conforms to the
EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is
transmitted on Line 20 of odd fields and Line 283 of even fields.
Subaddress 0x99, Bits[6:5] control whether CGMS data is
output on odd or even fields or both.
SD CGMS data can be transmitted only when the
ADV7390/ADV7391/ADV7392/ADV7393 are configured in
NTSC mode. The CGMS data is 20 bits long. The CGMS data is
preceded by a reference pulse of the same amplitude and
duration as a CGMS bit (see Figure 95).
ED CGMS
Subaddress 0x41 to Subaddress 0x43;
Subaddress 0x5E to Subaddress 0x6E
525p Mode
The ADV7390/ADV7391/ADV7392/ADV7393 support a copy
generation management system (CGMS) in 525p mode in
accordance with EIAJ CPR-1204-1.
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 525p
CGMS data is inserted on Line 41. The 525p CGMS data
registers are at Subaddress 0x41, Subaddress 0x42, and
Subaddress 0x43.
The ADV7390/ADV7391/ADV7392/ADV7393 also support
CGMS Type B packets in 525p mode in accordance with CEA805-A.
When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
525p CGMS Type B data is inserted on Line 40. The 525p CGMS
Type B data registers are at Subaddress 0x5E to Subaddress 0x6E.
625p Mode
The ADV7390/ADV7391/ADV7392/ADV7393 support a copy
generation management system (CGMS) in 625p mode in
accordance with IEC 62375 (2004).
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p
CGMS data is inserted on Line 43. The 625p CGMS data
registers are at Subaddress 0x42 and Subaddress 0x43.
HD CGMS
Subaddress 0x41 to Subaddress 0x43;
Subaddress 0x5E to Subaddress 0x6E
The ADV7390/ADV7391/ADV7392/ADV7393 support a copy
generation management system (CGMS) in HD mode (720p
and 1080i) in accordance with EIAJ CPR-1204-2.
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 720p
CGMS data is applied to Line 24 of the luminance vertical
blanking interval.
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 1080i
CGMS data is applied to Line 19 and Line 582 of the luminance
vertical blanking interval.
The HD CGMS data registers are at Subaddress 0x41, Subadress 0x42, and Subaddress 0x43.
The ADV7390/ADV7391/ADV7392/ADV7393 also support
CGMS Type B packets in HD mode (720p and 1080i) in
accordance with CEA-805-A.
When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
720p CGMS data is applied to Line 23 of the luminance vertical
blanking interval.
When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
1080i CGMS data is applied to Line 18 and Line 581 of the
luminance vertical blanking interval.
The HD CGMS Type B data registers are at Subaddress 0x5E to
Subaddress 0x6E.
CGMS CRC FUNCTIONALITY
If SD CGMS CRC (Subaddress 0x99, Bit 4) or ED/HD CGMS
CRC (Subaddress 0x32, Bit 7) is enabled, the upper six CGMS
data bits (C19 to C14) that comprise the 6-bit CRC check
sequence are automatically calculated on the ADV7390/
ADV7391/ADV7392/ADV7393. This calculation is based on
the lower 14 bits (C13 to C0) of the data in the CGMS data
registers, and the result is output with the remaining 14 bits to
form the complete 20 bits of the CGMS data. The calculation of
the CRC sequence is based on the polynomial x
preset value of 111111.
If SD CGMS CRC or ED/HD CGMS CRC is disabled, all 20 bits
(C19 to C0) are output directly from the CGMS registers (CRC
must be calculated by the user manually).
If ED/HD CGMS Type B CRC (Subaddress 0x5E, Bit 1) is
enabled, the upper six CGMS Type B data bits (P122 to P127)
that comprise the 6-bit CRC check sequence are automatically
calculated on the ADV7390/ADV7391/ADV7392/ADV7393.
This calculation is based on the lower 128 bits (H0 to H5 and
P0 to P121) of the data in the CGMS Type B data registers. The
result is output with the remaining 128 bits to form the
complete 134 bits of the CGMS Type B data. The calculation of
the CRC sequence is based on the polynomial x
preset value of 111111.
If ED/HD CGMS Type B CRC is disabled, all 134 bits (H0 to H5
and P0 to P127) are output directly from the CGMS Type B
registers (CRC must be calculated by the user manually).
1. PLEASE REF ER TO THE CEA-805-A SPECIFI CATION FO R TIMING INFORMAT ION.
START
BIT 1 BIT 2
H0H1H2H3H4
Figure 100. Enhanced Definition (525p) CGMS Type B Waveform
+700mV
70% ±10%
0mV
–300mV
START
BIT 1 BIT 2
H0H1H2H3H4
22.84µs ± 210ns
22T
1H
P0P1P2P3P4
H5
× 2200/77) = 1. 038µs
T = 1/(f
H
f
= HORIZO NTAL SCAN FREQUENCY
H
P2P3P4
P0
P1
H5
...
P122
.
..
CRC SEQUENCE
BIT 134
P123
P124
P125
CRC SEQUENCE
P122
P123
P124
P126
P127
P125
BIT 134
P126
P127
06234-097
06234-098
NOTES
1. PLEASE REFER TO T HE CEA-805-A SPECI FICATI ON FOR T IMING I NFORMATI ON.
Figure 101. High Definition (720p and 1080i) CGMS Type B Waveform
Rev. I | Page 76 of 107
06234-099
Page 77
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
1 Film mode
Open Subtitles
0 0 No
Copyright
0 No copyright asserted or unknown
ACTIVE
VIDEO
RUN-IN
SEQUENCE
START
CODE
500mV
11.0µs
38.4µs
42.5µs
W0 W1 W2 W3 W4
W5 W6 W7 W8 W9 W10 W1
1 W12 W13
06234-100
SD WIDE SCREEN SIGNALING
Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B
The ADV7390/ADV7391/ADV7392/ADV7393 support wide
screen signaling (WSS) con-forming to the ETSI 300 294
standard. WSS data is transmitted on Line 23. WSS data can be
transmitted only when the device is configured in PAL mode.
The WSS data is 14 bits long. The function of each of these bits
is shown in Tab l e 59. The WSS data is preceded by a run-in
Table 59. Function of WSS Bits
Bit Number
Bit Description 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Setting
Aspect Ratio, Format, Position 1 0 0 0 4:3, full format, N/A
0 0 0 1 14:9, letterbox, center
0 0 1 0 14:9, letterbox, top
1 0 1 1 16:9, letterbox, center
0 1 0 0 16:9, letterbox, top
1 1 0 1 >16:9, letterbox, center
1 1 1 0 14:9, full format, center
0 1 1 1 16:0, N/A, N/A
Mode 0 Camera mode
sequence and a start code (see Figure 102). The latter portion of
Line 23 (after 42.5 µs from the falling edge of
HSYNC
) is
available for the insertion of video. WSS data transmission on
Line 23 can be enabled using Subaddress 0x99, Bit 7. It is
possible to blank the WSS portion of Line 23 with Subaddress
0xA1, Bit 7.
Color Encoding 0 Normal PAL
1 Motion Adaptive ColorPlus
Helper Signals 0 Not present
1 Present
Reserved 0 N/A
Teletext Subtitles 0 No
1 Ye s
0 1 Subtitles in active image area
1 0 Subtitles out of active image area
1 1 Reserved
Surround Sound 0 No
1 Yes
1 Copyright asserted
Copy Protection 0 Copying not restricted
1 Copying restricted
Figure 102. WSS Waveform Diagram
Rev. I | Page 77 of 107
Page 78
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
D0
TO D6
D0 TO D6
10.5 ± 0.25
µs12.91
µs
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLIT UDE = 40 IRE
50 IRE
40 IRE
10.003µs
27.382µs33.764µ
s
BYTE 1BYTE 0
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
P
A
R
I
T
Y
P
A
R
I
T
Y
06234-101
SD CLOSED CAPTIONING
Subaddress 0x91 to Subaddress 0x94
The ADV7390/ADV7391/ADV7392/ADV7393 support closed
captioning conforming to the standard television synchronizing
waveform for color trans-mission. When enabled, closed
captioning is transmitted during the blanked active line time of
Line 21 of the odd fields and Line 284 of the even fields. Closed
captioning can be enabled using Subaddress 0x83, Bits[6:5].
Closed captioning consists of a seven-cycle sinusoidal burst that
is frequency- and phase-locked to the caption data. After the
clock run-in signal, the blanking level is held for two data bits
and is followed by a Logic 1 start bit. Sixteen bits of data follow
the start bit. The data consists of two 8-bit bytes (seven data bits
and one odd parity bit per byte). The data for these bytes is
stored in SD closed captioning registers (Subaddress 0x93 to
Subaddress 0x94).
The ADV7390/ADV7391/ADV7392/ADV7393 also support the
extended closed captioning operation, which is active during
even fields and encoded on Line 284. The data for this
operation is stored in SD closed captioning registers
(Subaddress 0x91 to Subaddress 0x92).
The ADV7390/ADV7391/ADV7392/ADV7393 automatically
generate all clock run-in signals and timing that support closed
captioning on Line 21 and Line 284. All pixels inputs are ignored
on Line 21 and Line 284 if closed captioning is enabled.
The FCC Code of Federal Regulations (CFR) Title 47 Section
15.119 and EIA-608 describe the closed captioning information
for Line 21 and Line 284.
The ADV7390/ADV7391/ADV7392/ADV7393 use a single
buffering method. This means that the closed captioning buffer
is only 1-byte deep. Therefore, there is no frame delay in
outputting the closed captioning data, unlike other 2-byte deep
buffering systems. The data must be loaded one line before it is
output on Line 21 and Line 284. A typical implementation of
this method is to use
VSYNC
to interrupt a microprocessor,
which in turn loads the new data (two bytes) in every field. If no
new data is required for transmission, 0s must be inserted in
both data registers; this is called nulling. It is also important to
load control codes, all of which are double bytes, on Line 21.
Otherwise, a TV does not recognize them. If there is a message
such as “Hello World” that has an odd number of characters, it
is important to add a blank character at the end to make sure that
the end-of-caption, 2-byte control code lands in the same field.
Figure 103. SD Closed Captioning Waveform, NTSC
Rev. I | Page 78 of 107
Page 79
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
0x31
0x05
INTERNAL TEST PATTERN GENERATION
SD TEST PATTERNS
The ADV7390/ADV7391/ADV7392/ADV7393 are able to
internally generate SD color bar and black bar test patterns. For
this function, a 27 MHz clock signal must be applied to the
CLKIN pin.
The register settings in Table 60 are used to generate an SD NTSC
75% color bar test pattern. All other registers are set as normal/
default. Component YPrPb output is available on DAC 1 to
DAC 3. On power-up, the subcarrier frequency registers default
to the appropriate values for NTSC.
Table 60. SD NTSC Color Bar Test Pattern Register Writes
Subaddress Setting
0x00 0x1C
0x82 0xC9
0x84 0x40
For CVBS and S-Video (Y/C) output, 0xCB instead of 0xC9
should be written to Subaddress 0x82.
For component RGB output rather than YPrPb output, 0 should
be written to Subaddress 0x02, Bit 5.
To generate an SD NTSC black bar test pattern, the settings
shown in Tab l e 60 should be used with an additional write of
0x24 to Subaddress 0x02.
For PAL output of either test pattern, the same settings are used
except that Subaddress 0x80 is programmed to 0x11, and the
subcarrier frequency (F
in Table 61.
Note that, when programming the FSC registers, the user must
write the values in the sequence F
F
value to be written is only accepted after the FSC3 write is
SC
complete.
) registers are programmed as shown
SC
Register Writes
0, FSC1, FSC2, FSC3. The full
SC
ED/HD TEST PATTERNS
The ADV7390/ADV7391/ADV7392/ADV7393 are able to
internally generate ED/HD color bar, black bar, and hatch test
patterns. For ED test patterns, a 27 MHz clock signal must be
applied to the CLKIN pin. For HD test patterns, a 74.25 MHz
clock signal must be applied to the CLKIN pin.
The register settings in Tabl e 62 are used to generate an ED
525p hatch test pattern. All other registers are set as normal/
default. Component YPrPb output is available on DAC 1 to
DAC 3. For component RGB output rather than YPrPb output,
0 should be written to Subaddress 0x02, Bit 5.
Table 62. ED 525p Hatch Test Pattern Register Writes
Subaddress Setting
0x00 0x1C
0x01 0x10
To generate an ED 525p black bar test pattern, the settings
shown in Tab l e 62 should be used with an additional write of
0x24 to Subaddress 0x02.
To generate an ED 525p flat field test pattern, the settings
shown in Tab l e 62 should be used, except that 0x0D should be
written to Subaddress 0x31.
The Y, Cr, and Cb levels for the hatch and flat field test patterns
can be controlled using Subaddress 0x36, Subaddress 0x37, and
Subaddress 0x38, respectively.
For ED/HD standards other than 525p, the settings shown in
Table 62 (and subsequent comments) are used, except that
Subaddress 0x30, Bits[7:3] are updated as appropriate.
Rev. I | Page 79 of 107
Page 80
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Y
C
r
Y
FF0000X
Y
8
0
10801
0
FF00FFABABA
B
801
0
8
0
10FF0
0
0
0
XYC
b
Y
C
r
C
b
Y
C
b
Y
C
r
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
268 CLOCK
1440 CLOCK
4 CLOCK
4 CLOCK
280 CLOCK
1440 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/ 60Hz )
PAL SYSTEM
(625 LINES/ 50Hz )
Y
06234-102
522
523524525
8
9
10
112021
22
DISPLAY
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
H
F
260261262263264265266267268269270271272273274
283
284
285
ODD FIELD
EVEN FIELD
DISPLAY
DISPL
AY
VERTICAL BLANK
H
F
765
4
32
1
06234-103
SD TIMING
Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)
The ADV7390/ADV7391/ADV7392/ADV7393 are controlled by the SAV (start of active video) and EAV (end of active video) time codes
embedded in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is
sent immediately before and after each line during active picture and retrace. If the
tied to V
when using this mode.
DD_IO
VSYNC
and
HSYNC
pins are not used, they should be
Figure 104. SD Timing Mode 0, Slave Option
Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)
The ADV7390/ADV7391/ADV7392/ADV7393 generate H and F signals required for the SAV and EAV time codes in the CCIR-656
standard. The H bit is output on
HSYNC
and the F bit is output on
Figure 105. SD Timing Mode 0, Master Option, NTSC
VSYNC
.
Rev. I | Page 80 of 107
Page 81
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
A
DISPLAY
622623624625
H
F
DISPLAY
309310311312314315316317
H
F
EVEN FIELD
ODD FIELD
1
ODD FIELD
313
EVEN FIELD
VERTICAL BLANK
32
VERTICAL BLANK
4
318
765
319320
21
2223
334
DISPLAY
335336
DISPLAY
6234-104
Figure 106. SD Timing Mode 0, Master Option, PAL
NALOG
VIDEO
H
F
06234-105
Figure 107. SD Timing Mode 0, Master Option, Data Transitions
Mode 1—Slave Option (Subaddress 0x8A = X X X X X 0 1 0)
In this mode, the ADV7390/ADV7391/ADV7392/ADV7393 accept horizontal synchronization and odd/even field signals. When
HSYNC
VSYNC
is low, a transition of the field input indicates a new frame, that is, vertical retrace.
pins, respectively.
HSYNC
FIELD
DISPLAY
522523524525
DISPLAY
1
3
2
EVEN FIELD
4
ODD FIELD
VERTICAL BLANK
59
VERTICAL BLANK
7
6
HSYNC
8
and FIELD are input on the
1011
202122
HSYNC
DISPLAY
DISPLAY
and
HSYNC
FIELD
260261262263264265266267268269270271272273274
ODD FIELD EVEN FIELD
283
284
285
06234-106
Figure 108. SD Timing Mode 1, Slave Option, NTSC
Rev. I | Page 81 of 107
Page 82
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
DISPLAY
DISPLAY
334335336
6234-107
HSYNC
FIELD
HSYNC
FIELD
DISPLAY
622623624625
EVEN FIELD
DISPLAY
309310311312313314315316
ODD FIELD
ODD FIELD
EVEN FIELD
21
VERTICAL BLANK
3
VERTICAL BLANK
4
5
317
6
318319
7
212223
320
Figure 109. SD Timing Mode 1, Slave Option, PAL
Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)
In this mode, the ADV7390/ADV7391/ADV7392/ADV7393 can generate horizontal synchronization and odd/even field signals. When
HSYNC
is low, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV7390/ADV7391/ADV7392/ADV7393
automatically blank all normally blank lines as required by the CCIR-624 standard. Pixel data is latched on the rising clock edge following
the timing signal transitions.
HSYNC
and FIELD are output on the
HSYNC
and
VSYNC
pins, respectively.
HSYNC
FIELD
PIXEL
DATA
CbY
PAL = 132 × CLOCK/2
NTSC = 122 × CL OCK/2
CrY
06234-108
Figure 110. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)
Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)
In this mode, the ADV7390/ADV7391/ADV7392/ADV7393 accept horizontal and vertical synchronization signals. A coincident low
transition of both
HSYNC
and
VSYNC
inputs indicates the start of an odd field. A
VSYNC
low transition when
HSYNC
is high indicates
the start of an even field. The ADV7390/ADV7391/ADV7392/ADV7393 automatically blank all normally blank lines as required by the
CCIR-624 standard.
HSYNC
and
VSYNC
are input on the
HSYNC
and
VSYNC
pins, respectively.
Rev. I | Page 82 of 107
Page 83
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
HSYNC
VSYNC
HSYNC
VSYNC
DISPLAY
4
522523524525
DISPLAY
260261262263264265266267268269270271272273274
1
3
2
EVEN FIELD
ODD FIELD
VERTICAL BLANK
5
6
ODD FIELD
VERTICAL BLANK
EVEN FIELD
7
8
1011
9
202122
DISPLAY
283
284
DISPLAY
285
6234-109
Figure 111. SD Timing Mode 2, Slave Option, NTSC
DISPLAY
HSYNC
DISPLAY
622623624625
VERTICAL BLANK
4
321
765
212223
VSYNC
HSYNC
VSYNC
DISPLAY
3093103 11312313314315316
ODD FIELD
ODD FIELDEVEN FIELD
VERTICAL BLANK
EVEN FIELD
317
318319
320
DISPLAY
334335336
06234-110
Figure 112. SD Timing Mode 2, Slave Option, PAL
Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)
In this mode, the ADV7390/ADV7391/ADV7392/ADV7393 can generate horizontal and vertical synchronization signals. A coincident
low transition of both
HSYNC
and
VSYNC
inputs indicates the start of an odd field. A
VSYNC
low transition when
HSYNC
is high
indicates the start of an even field. The ADV7390/ADV7391/ADV7392/ADV7393 automatically blank all normally blank lines as required
by the CCIR-624 standard.
HSYNC
and
VSYNC
are output on the
HSYNC
and
VSYNC
pins, respectively.
HSYNC
VSYNC
PIXEL
DATA
PAL = 132 × CLOCK/2
NTSC = 122 × CL OCK/2
Figure 113. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave)
Rev. I | Page 83 of 107
Cb
Cr
Y
Y
06234-111
Page 84
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Cb
PIXEL
DATA
HSYNC
VSYNC
PAL = 132 × CLOCK/2
NTSC = 122 × CL OCK/2
PAL = 864 × CLOCK/2
NTSC = 858 × CL OCK/2
Cb
Y
Y
Cr
06234-112
260261262263264265266267268269270271272273274
283
284
285
ODD FIELD EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
522523524525
9
1011
202122
DISPLAY
DISPLAY
VERTICAL BLANK
ODD FIELDEVEN FIELD
HSYNC
FIELD
HSYNC
FIELD
8
765
4
32
1
06234-113
622623624625
5
6
212223
DISPLAY
VERTICAL BLANK
ODD FIELDEVEN FIELD
FIELD
DISPLAY
309310311312313314315316
317
318319
334335336
DISPLAY
VERTICAL BLANK
ODD FIELDEVEN FIELD
FIELD
DISPLAY
320
4
32
1
7
HSYNC
HSYNC
06234-114
Figure 114. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave)
Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7390/ADV7391/ADV7392/ADV7393 accept or generates horizontal synchronization and odd/even field signals.
HSYNC
When
ADV7390/ADV7391/ADV7392/ADV7393 automatically blank all normally blank lines as required by the CCIR-624 standard.
VSYNC
and
is high, a transition of the field input indicates a new frame, that is, vertical retrace. The
are output in master mode and input in slave mode on the
HSYNC
and
VSYNC
pins, respectively.
HSYNC
Figure 115. SD Timing Mode 3, NTSC
Figure 116. SD Timing Mode 3, PAL
Rev. I | Page 84 of 107
Page 85
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
HD TIMING
DISPLAY
FIELD 1
VSYNC
HSYNC
FIELD 2
VSYNC
HSYNC
VERTICAL BL ANKING INTERVAL
11241125
561562563564567568569570
1256 7 8
VERTICAL BL ANKING INTERVAL
Figure 117. 1080i
43
566565
and
VSYNC
Input Timing
HSYNC
21
2022560
DISPLAY
584
5835851123
06234-115
Rev. I | Page 85 of 107
Page 86
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
3
V
VIDEO OUTPUT LEVELS
SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10
Pattern: 100% Color Bars
WHITE
YELLOW
CYAN
GREEN
MAGENTARED
BLUE
700mV
BLACK
WHITE
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
700mV
BLACK
300mV
06234-116
Figure 118. Y Levels—NTSC
WHITE
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
700mV
06234-117
Figure 119. Pr Levels—NTSC
00m
700mV
Figure 121. Y Levels—PAL
WHITE
YELLOW
CYAN
GREEN
Figure 122. Pr Levels—PAL
06234-119
MAGENTA
RED
BLUE
BLACK
06234-120
WHITE
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
06234-121
700mV
WHITE
YELLOW
CYAN
GREEN
MAGENTA
Figure 120. Pb Levels—NTSC
RED
BLUE
BLACK
700mV
06234-118
Figure 123. Pb Levels—PAL
Rev. I | Page 86 of 107
Page 87
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
ED/HD YPrPb OUTPUT LEVELS
INPUT CODE
EIA-770.2, S TANDARD FOR Y
OUTPUT VOLTAGE
INPUT CODE
EIA-770.3, S TANDARD FOR Y
OUTPUT VOLTAGE
940
64
EIA-770.2, STANDARD FOR Pr/Pb
960
512
64
Figure 124. EIA-770.2 Standard Output Signals (525p/625p)
INPUT CODE
EIA-770.1, STANDARD FOR Y
940
700mV
300mV
OUTPUT VOLTAGE
700mV
OUTPUT VOLTAGE
782mV
940
700mV
64
300mV
EIA-770.3, STANDARD FOR Pr/Pb
960
512
64
06234-122
600mV
OUTPUT VOLTAGE
700mV
06234-124
Figure 126. EIA-770.3 Standard Output Signals (1080i/720p)
INPUT CODE
1023
Y–OUTPUT LEVELS FOR
FULL INPUT SELECTION
OUTPUT VOLTAGE
64
EIA-770.1, STANDARD FOR Pr/Pb
960
512
64
Figure 125. EIA-770.1 Standard Output Signals (525p/625p)
714mV
286mV
OUTPUT VOLTAGE
700mV
700mV
64
300mV
INPUT CODE
1023
6234-123
Pr/Pb–OUTPUT LEVELS FOR
FULL INPUT SELECTION
64
OUTPUT VOLTAGE
700mV
300mV
06234-125
Figure 127. Output Levels for Full Input Selection
APL = 44.5%
525 LINE NTSC
SLOW CLAMP TO 0.00V AT 6.72s
MICROSECONDS
PRECISION MODE OFF
SYNCHRO NOUS SYNC = A
Figure 132. NTSC Color Bars (75%)
IRE:FLT
VOLTS
0.6
0.4
50
0.2
0
0
0
–0.2
0
NOISE REDUCTI ON: 15.05dB
APL = 44.3%
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00V AT 6.72s
F2
L238
102030405060
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS SYNC = SO URCE
Figure 133. NTSC Luma
VOLTS IRE:FLT
0.4
50
30405060
µ FRAMES SELECTED 1, 2
µ FRAMES SELECTED 1, 2
0
–0.2
L608
10020
NOISE REDUCTION: 0. 00dB
APL = 39.1%
625 LINE NTSC NO FILTERING
06234-130
06234-131
SLOW CL AMP TO 0.00 AT 6.72µs
Figure 135. PAL Color Bars (75%)
VOLTS
0.5
0
L575
10020
APL NEEDS SYNC SOURCE.
625 LINE PAL NO F ILTERING
SLOW CLAMP TO 0.00 AT 6.72µs
VOLTS
0.5
MICROSECONDS
30405060
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS SO UND-IN-SYNC OFF
FRAMES SELECTED 1, 2, 3, 4
30405060
NO BUNCH SIGNAL
PRECISION MODE OFF
SYNCHRONOUS SOUND-IN-SYNC OFF
FRAMES SELECTED 1
Figure 136. PAL Luma
06234-133
70
6234-134
0.2
0
0
–0.2
–50
–0.4
F1
L76
0
1020
NOISE REDUCTI ON: 15.05dB
APL NEEDS SYNC SOURCE.
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72µs
30405060
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS SYNC = B
FRAMES SELECTED 1, 2
Figure 134. NTSC Chroma
06234-132
Rev. I | Page 89 of 107
0
–0.5
L575
10020
APL NEEDS SYNC S OURCE.
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72µs
MICROSECONDS
Figure 137. PAL Chroma
30405060
NO BUNCH SIG NAL
PRECISION MODE OFF
SYNCHRONOUS SOUND-IN-SYNC OFF
FRAMES SELECTED 1
06234-135
Page 90
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
F
V
H*
F
F
272T
4T
*1
4T1920T
EAV CODE
SAV CODE
DIGITAL
ACTIVE LINE
4 CLOCK4 CLOCK
21122116 21562199
0
441881922111
000
0
000
0
F
F
F
V
H*
C
bCr
C
r
Y
Y
FVH* = FVH AND PARITY BITS
SAV/EAV: LINE 1–562: F = 0
SAV/EAV: LINE 563–1125: F = 1
SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1
SAV/EAV: LINE 21–560; 584–1123: V = 0
FOR A FRAME RATE OF 30Hz: 40 SAMPLES
FOR A FRAME RATE OF 25Hz: 480 SAMPLES
INPUT PIXELS
ANALOG WAVEFORM
SAMPLE NUMBER
SMPTE 274M
DIGITAL HORIZONTAL BLANKING
ANCILLARY DATA
(OPTIONAL) OR BL ANKING CODE
0
H
DATUM
06234-136
Y
EAV CODE
ANCILLARY DATA
(OPTIONAL)
SAV CODE
DIGITAL
ACTIVE LINE
719723 7367998530
FVH* = FVH AND PARITY BITS
SAV: LINE 43–525 = 200H
SAV: LINE 1–42 = 2AC
EAV: LINE 43–525 = 274H
EAV: LINE 1–42 = 2D8
4 CLOCK
4 CLOCK
857719
0
H
DATUM
DIGITAL HORIZONTAL BLANKING
000
0
000
0
CbC
r
C
r
Y
Y
F
V
H*
SMPTE 293M
INPUT PIXELS
ANALOG WAVEFORM
SAMPLE NUMBER
F
F
F
F
F
V
H*
06234-137
VERTICAL BLANK
522 523 524 52512567891213141516424344
ACTIVE
VIDEO
ACTIVE
VIDEO
06234-138
VIDEO STANDARDS
Figure 138. EAV/SAV Input Data Timing Diagram (SMPTE 274M)
Figure 139. EAV/SAV Input Data Timing Diagram (SMPTE 293M)
Figure 140. SMPTE 293M (525p)
Rev. I | Page 90 of 107
Page 91
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
ACTIVE
VIDEO
622 623624 6251011
125 6789
4
VERTICAL BLANK
12
13
ACTIVE
VIDEO
434445
06234-139
Figure 141. ITU-R BT.1358 (625p)
DISPLAY
VERTICAL BLANKI NG INTERVAL
747748749750262725744745
123
456
7
8
06234-140
Figure 142. SMPTE 296M (720p)
DISPLAY
VERTICAL BLANKI NG INTERVAL
FIELD 1
FIELD 2
11241125
561562563564567568569570
125678
VERTICAL BLANKI NG INTERVAL
4320
566565
Figure 143. SMPTE 274M (1080i)
560
22
21
DISPLAY
584
5835851123
6234-141
Rev. I | Page 91 of 107
Page 92
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
/
625i (PAL)
8-bit SDR
EAV/SAV
YCrCb
RGB
Table 84
CONFIGURATION SCRIPTS
The scripts listed in the following pages can be used to configure the ADV7390/ADV7391/ADV7392/ADV7393 for basic operation.
Certain features are enabled by default. If required for a specific application, additional features can be enabled. Table 63 lists the scripts
available for SD modes of operation. Similarly, Tabl e 98 and Table 115 list the scripts available for ED and HD modes of operation,
respectively. For all scripts, only the necessary register writes are included. All other registers are assumed to have their default values. The
WLCSP package supports only scripts in Table 65, Ta b l e 79, Table 82, and Table 96. In those scripts, Subaddress 0x00 must be set to 0x10.
STANDARD DEFINITION
Table 63. SD Configuration Scripts
Input Format Input Data Width1 Synchronization Format Input Color Space Output Color Space Table Number