Analog Devices ADV7171 Datasheet

Digital PAL/NTSC Video Encoder with 10-Bit

a

SSAF™ and Advanced Power Management

FEATURES
ITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder
High Quality 10-Bit Video DACs
SSAF (Super Sub-Alias Filter)
Advanced Power Management Features
CGMS (Copy Generation Management System)
WSS (Wide Screen Signalling)
Simultaneous Y, U, V, C Output Format
NTSC-M, PAL-M/N, PAL-B/D/G/H/I, PAL-60
Single 27 MHz Clock Required (32 Oversampling)
80 dB Video SNR
32-Bit Direct Digital Synthesizer for Color Subcarrier
Multistandard Video Output Support:

Composite (CVBS)
Component S-Video (Y/C)
Component YUV and RGB
EuroSCART Output (RGB + CVBS/LUMA)

Component YUV + CHROMA
Video Input Data Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
4:2:2 16-Bit Parallel Input Format
SMPTE 170M NTSC-Compatible Composite Video
ITU-R BT.470 PAL-Compatible Composite Video
Programmable Simultaneous Composite

and S-Video or RGB (SCART)/YUV Video Outputs
Programmable Luma Filters (Low-Pass [PAL/NTSC])

Notch, Extended (SSAF, CIF and QCIF)

FUNCTIONAL BLOCK DIAGRAM

TTXREQ

V

RESET

COLOR

DATA
P7–P0

P15–P8

HSYNC

FIELD/VSYNC

BLANK

POWER

MANAGEMENT

AA

CONTROL

(SLEEP MODE)

4:2:2 TO

4:4:4

INTER-

POLATOR

VIDEO TIMING

GENERATOR

8

8

8

YCrCb

TO

YUV

MATRIX

8

Y

U

V

8

CGMS & WSS

INSERTION

BLOCK

ADD

SYNC

ADD

BURST

I2C MPU PORT

9

88

8

POLATOR

POLATOR

TELETEXT

INSERTION

INTER-

INTER-

TTX

BLOCK

9

8

8

ADV7170/ADV7171*

Programmable Chroma Filters (Low-Pass [0.65 MHz,

1.0 MHz, 1.2 MHz and 2.0 MHz], CIF and QCIF)
Programmable VBI (Vertical Blanking Interval)
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
Individual ON/OFF Control of Each DAC
CCIR and Square Pixel Operation
Integrated Subcarrier Locking to External Video Source
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
Macrovision AntiTaping Rev 7.01 (ADV7170 Only)**
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
On-Board Color Bar Generation
On-Board Voltage Reference
2-Wire Serial MPU Interface (I
Single Supply +5 V or +3.3 V Operation
Small 44-Lead PQFP/TQFP Packages

APPLICATIONS
High Performance DVD Playback Systems, Portable

Video Equipment Including Digital Still Cameras and
Laptop PCs, Video Games, PC Video/Multimedia and
Digital Satellite/Cable Systems (Set-Top Boxes/IRD)

10

PROGRAMMABLE

LUMINANCE

FILTER

PROGRAMMABLE

CHROMINANCE

FILTER

REAL-TIME

CONTROL

CIRCUIT

10

10

10

SIN/COS

DDS BLOCK

YUV TO
MATRIX

U

V

RBG

10

10

10

ADV7170/ADV7171

10

2C®

Compatible and Fast I2C)

M
U

10

10-BIT

L
T

I

10

P
L
E

10

X
E
R

10

VOLTAGE

REFERENCE

CIRCUIT

DAC

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

DAC D (PIN 27)

DAC C (PIN 26)

DAC B (PIN 31)

DAC A (PIN 32)

V
R
COMP

REF
SET

CLOCK

SCLOCK SDATA ALSB

SCRESET/RTC

GND

*Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.
**This device is protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. The Macrovision anticopy process is

licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.
NOTE: ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
SSAF is a trademark of Analog Devices, Inc.
I2C is a registered trademark of Philips Corporation.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

ADV7170/ADV7171–SPECIFICATIONS

5 V SPECIFICATIONS

(VAA = +5 V 6 5%1, V

Parameter Conditions

= 1.235 V, R

REF

1

= 150 V. All specifications T

SET

Min Typ Max Units

MIN

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits
Accuracy (Each DAC)
Integral Nonlinearity R

= 300 Ω±0.6 LSB

SET

Differential Nonlinearity Guaranteed Monotonic ±1 LSB

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

V

= 0.4 V or 2.4 V ±1 µA

IN

2V

DIGITAL OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

I
I

= 400 µA 2.4 V

SOURCE

= 3.2 mA 0.4 V

SINK

Three-State Leakage Current 10 µA
Three-State Output Capacitance 10 pF

2

to T

unless otherwise noted.)

MAX

0.8 V

10 pF

ANALOG OUTPUTS

Output Current
Output Current

3
4

R

= 150 Ω, RL = 37.5 Ω 33 34.7 37 mA

SET

R

= 1041 Ω, RL = 262.5 Ω 5mA

SET

DAC-to-DAC Matching 1.5 %
Output Compliance, V
Output Impedance, R

OC

OUT

Output Capacitance, C

OUT

I

= 0 mA 30 pF

OUT

0 +1.4 V

30 kΩ

VOLTAGE REFERENCE

Reference Range, V

POWER REQUIREMENTS

V

AA

Normal Power Mode

(max)

I

DAC

(min)

I

DAC

7

I

CCT

Low Power Mode

(max)

I

DAC

(min)

I

DAC

7

I

CCT

Sleep Mode

8

I

DAC

9

I

CCT

REF

5

6

6

6

6

I

VREFOUT

= 20 µA 1.142 1.235 1.327 V

4.75 5.0 5.25 V

R

= 150 Ω, RL = 37.5 Ω 150 155 mA

SET

R

= 1041 Ω, RL = 262.5 Ω 20 mA

SET

75 90 mA

80 mA
20 mA
75 90 mA

0.1 µA

0.001 µA

Power Supply Rejection Ratio COMP = 0.1 µF 0.01 0.5 %/%

NOTES

1

The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.

2

Temperature range T

3

Full drive into 37.5␣ Ω doubly terminated load.

4

Minimum drive current (used with buffered/scaled output load).

5

Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 110°C.

6

I

is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all four DACs. Turning off individual

DAC

DACs reduces I

7

I

(Circuit Current) is the continuous current required to drive the device.

CCT

8

Total DAC current in Sleep Mode.

9

Total continuous current during Sleep Mode.

Specifications subject to change without notice.

to T

MIN

correspondingly.

DAC

: 0°C to +70°C.

MAX

–2– REV. 0

ADV7170/ADV7171

3.3 V SPECIFICATIONS

(VAA = +3.0 V – 3.6 V1, V

Parameter Conditions

STATIC PERFORMANCE

3

= 1.235 V, R

REF

1

= 150 V. All specifications T

SET

Min Typ Max Units

MIN

Resolution (Each DAC) 10 Bits
Accuracy (Each DAC)
Integral Nonlinearity R

= 300 Ω±0.6 LSB

SET

Differential Nonlinearity Guaranteed Monotonic ±1 LSB

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

DIGITAL OUTPUTS

Output High Voltage, V
Output Low Voltage, V

3

INH

INL

3, 4

IN

IN

3

OH

OL

V

= 0.4 V or 2.4 V ±1 µA

IN

I
I

= 400 µA 2.4 V

SOURCE

= 3.2 mA 0.4 V

SINK

2V

10 pF

Three-State Leakage Current 10 µA
Three-State Output Capacitance 10 pF

ANALOG OUTPUTS

Output Current
Output Current

4, 5
6

3

R

= 150 Ω, RL = 37.5 Ω 33 34.7 37 mA

SET

R

= 1041 Ω, RL = 262.5 Ω 5mA

SET

DAC-to-DAC Matching 2.0 %
Output Compliance, V
Output Impedance, R
Output Capacitance, C

POWER REQUIREMENTS

V

AA

Normal Power Mode

I

DAC

I

DAC

I

CCT

Low Power Mode

I

DAC

I

DAC

I

CCT

Sleep Mode

I

DAC

I

CCT

(max)
(min)

9

(max)
(min)

9

10
11

8

8

8

8

OC

OUT

OUT

3, 7

I

= 0 mA 30 pF

OUT

R

= 150 Ω, RL = 37.5 Ω 150 155 mA

SET

R

= 1041 Ω, RL = 262.5 Ω 20 mA

SET

0 +1.4 V

30 kΩ

3.0 3.3 3.6 V

35 mA

80 mA
20 mA
35 mA

0.1 µA

0.001 µA

Power Supply Rejection Ratio COMP = 0.1 µF 0.01 0.5 %/%

NOTES

11

The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.

12

Temperature range T

13

Guaranteed by characterization.

14

Full drive into 37.5␣ Ω load.

15

DACs can output 35 mA typically at 3.3 V (R

16

Minimum drive current (used with buffered/scaled output load).

17

Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 110°C.

18

I

is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. Turning off individual

DAC

DACs reduces I

19

I

(Circuit Current) is the continuous current required to drive the device.

CCT
10

Total DAC current in Sleep Mode.

11

Total continuous current during Sleep Mode.

Specifications subject to change without notice.

to T

MIN

correspondingly.

DAC

: 0°C to +70°C.

MAX

= 150 Ω and RL = 37.5 Ω), optimum performance obtained at 18 mA DAC current (R

SET

2

to T

unless otherwise noted.)

MAX

0.8 V

= 300 Ω and RL = 75 Ω).

SET

–3–REV. 0

ADV7170/ADV7171–SPECIFICATIONS

(VAA = +5 V 6 5%1, V

5 V DYNAMIC SPECIFICATIONS

Parameter Conditions

3, 4

3, 4

3, 4

3, 4

3, 4

MIN

3, 4

3, 4

to T

3, 4

3, 4

3, 4

3, 4

3, 4

3, 4

3, 4

: 0°C to +70°C.

MAX

Differential Gain
Differential Phase
Differential Gain
Differential Phase

3, 4

(Pedestal) RMS 80 dB rms

SNR

3, 4

(Pedestal) Peak Periodic 70 dB p-p

SNR

3, 4

(Ramp) RMS 60 dB rms

SNR

3, 4

(Ramp) Peak Periodic 58 dB p-p

SNR
Hue Accuracy
Color Saturation Accuracy
Chroma Nonlinear Gain
Chroma Nonlinear Phase
Chroma/Luma Intermod
Chroma/Luma Gain Inequality
Chroma/Luma Delay Inequality
Luminance Nonlinearity
Chroma AM Noise
Chroma PM Noise

NOTES

1

The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.

2

Temperature range T

3

Guaranteed by characterization.

4

The low pass filter only and guaranteed by design.

Specifications subject to change without notice.

otherwise noted.)

1

Normal Power Mode 0.3 0.7 %
Normal Power Mode 0.4 0.7 Degrees
Lower Power Mode 1.0 2.0 %
Lower Power Mode 1.0 2.0 Degrees

Referenced to 40 IRE 0.6 ±%

= 1.235 V, R

REF

= 150 V. All specifications T

SET

Min Typ Max Units

0.7 1.2 Degrees

0.9 1.4 %

0.3 0.5 ±Degrees

0.2 0.4 ±%

1.0 1.4 ±%

0.5 2.0 ns

0.8 1.4 ±%

82 85 dB
79 81 dB

MIN

to T

MAX

2

unless

(VAA = +3.0 V – 3.6 V1, V

3.3 V DYNAMIC SPECIFICATIONS

Parameter Conditions

Differential Gain
Differential Phase
Differential Gain
Differential Phase

3

(Pedestal) RMS 78 dB rms

SNR

3

(Pedestal) Peak Periodic 70 dB p-p

SNR

3

(Ramp) RMS 60 dB rms

SNR

3

(Ramp) Peak Periodic 58 dB p-p

SNR
Hue Accuracy
Color Saturation Accuracy
Luminance Nonlinearity
Chroma AM Noise
Chroma PM Noise
Chroma Nonlinear Gain
Chroma Nonlinear Phase
Chroma/Luma Intermod

NOTES

1

The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.

2

Temperature range T

3

Guaranteed by characterization.

4

These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4.

Specifications subject to change without notice.

3

3

3

3

3

3

3, 4

3, 4

3, 4

3, 4

3, 4

3, 4

to T

MIN

: 0°C to +70°C.

MAX

otherwise noted.)

1

Normal Power Mode 1.0 %
Normal Power Mode 0.5 Degrees
Lower Power Mode 0.6 %
Lower Power Mode 0.5 Degrees

Referenced to 40 IRE 0.6 ±%

= 1.235 V, R

REF

= 150 V. All specifications T

SET

Min Typ Max Units

1.0 Degrees

1.0 %

1.4 ±%
80 dB
79 dB

0.3 0.5 ±Degrees

0.2 0.4 ±%

MIN

to T

MAX

2

unless

–4– REV. 0

ADV7170/ADV7171

to T

MAX

2

unless

5 V TIMING SPECIFICATIONS

(VAA = 4.75 V – 5.25 V1, V
otherwise noted.)

= 1.235 V, R

REF

= 150 V. All specifications T

SET

MIN

Parameter Conditions Min Typ Max Units

MPU PORT

3, 4

SCLOCK Frequency 0 400 kHz

SCLOCK High Pulsewidth, t

SCLOCK Low Pulsewidth, t

Hold Time (Start Condition), t

Setup Time (Start Condition), t

Data Setup Time, t

5

SDATA, SCLOCK Rise Time, t

SDATA, SCLOCK Fall Time, t

Setup Time (Stop Condition), t

ANALOG OUTPUTS

3, 5

1

2

After This Period the First Clock Is Generated 0.6 µs

3

Relevant for Repeated Start Condition 0.6 µs

4

6

7

8

0.6 µs

1.3 µs

100 ns

300 ns
300 ns

0.6 µs

Analog Output Delay 7ns

DAC Analog Output Skew 0 ns

CLOCK CONTROL AND
PIXEL PORT

f

CLOCK

Clock High Time, t

Clock Low Time, t

Data Setup Time, t

Data Hold Time, t

Control Setup Time, t

Control Hold Time, t

Digital Output Access Time, t

Digital Output Hold Time, t

Pipeline Delay, t

TELETEXT

Digital Output Access Time, t

Data Setup Time, t

Data Hold Time, t

RESET CONTROL

5, 6

3, 4, 7

27 MHz

9

10

11

12

11

12

13
4

4

15

17

18

3, 4

14

16

8ns
8ns

3.5 ns
4ns
4ns
3ns

11 16 ns
8ns
48 Clock Cycles

20 ns
2ns
6ns

RESET Low Time 6 ns

NOTES

1

The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range.

2

Temperature range T

3

TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and

outputs. Analog output load ≤ 10 pF.

4

Guaranteed by characterization.

5

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.

6

Pixel Port consists of the following:

Pixel Inputs: P15–P0
Pixel Controls: HSYNC, FIELD/VSYNC, BLANK
Clock Input: CLOCK

7

Teletext Port consists of the following:

Teletext Output: TTXREQ
Teletext Input: TTX

Specifications subject to change without notice.

MIN

to T

: 0oC to +70oC.

MAX

–5–REV. 0

ADV7170/ADV7171–SPECIFICATIONS

to T

MAX

2

unless

3.3 V TIMING SPECIFICATIONS

(VAA = 3.0 V – 3.6 V1, V
otherwise noted.)

= 1.235 V, R

REF

= 150 V. All specifications T

SET

MIN

Parameter Conditions Min Typ Max Units

MPU PORT

3, 4

SCLOCK Frequency 0 400 kHz
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t

5

SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

ANALOG OUTPUTS

3, 5

1

2

After This Period the First Clock Is Generated 0.6 µs

3

Relevant for Repeated Start Condition 0.6 µs

4

6

7

8

0.6 µs

1.3 µs

100 ns

300 ns
300 ns

0.6 µs

Analog Output Delay 7ns
DAC Analog Output Skew 0 ns

CLOCK CONTROL AND
PIXEL PORT

f

CLOCK

Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
Control Setup Time, t
Control Hold Time, t
Digital Output Access Time, t
Digital Output Hold Time, t
Pipeline Delay, t

TELETEXT

Digital Output Access Time, t
Data Setup Time, t
Data Hold Time, t

RESET CONTROL

4, 5, 6

3, 4, 7

27 MHz

9

10

11

12

11

12

13

14

15

16

17

18

3, 4

8ns
8ns

3.5 ns
4ns
4ns
3ns

12 ns
8ns
48 Clock Cycles

23 ns
2ns
6ns

RESET Low Time 6 ns

NOTES

1

The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V range.

2

Temperature range T

3

TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and

outputs. Analog output load ≤ 10 pF.

4

Guaranteed by characterization.

5

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.

6

Pixel Port consists of the following:

Pixel Inputs: P15–P0
Pixel Controls: HSYNC, FIELD/VSYNC, BLANK
Clock Input: CLOCK

7

Teletext Port consists of the following:

Teletext Output: TTXREQ
Teletext Input: TTX

Specifications subject to change without notice.

MIN

to T

: 0oC to +70oC.

MAX

–6– REV. 0

SDATA

t

16

t

17

t

18

4 CLOCK

CYCLES

4 CLOCK
CYCLES

4 CLOCK

CYCLES

3 CLOCK

CYCLES

4 CLOCK

CYCLES

TXTREQ

CLOCK

TXT

SCLOCK

CLOCK

t

t

3

t

6

t

2

5

t

1

t

7

Figure 1. MPU Port Timing Diagram

ADV7170/ADV7171

t

3

t

4

t

8

CONTROL

I/PS

CONTROL

O/PS

HSYNC,

FIELD/VSYNC,

BLANK

PIXEL INPUT

DATA

HSYNC,

FIELD/VSYNC,

BLANK

t

t

9

10

Cb Y Cr Y Cb Y

t

12

t

11

t

13

t

14

Figure 2. Pixel and Control Data Timing Diagram

Figure 3. Teletext Timing Diagram

–7–REV. 0

ADV7170/ADV7171

ABSOLUTE MAXIMUM RATINGS

1

VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Voltage on Any Digital Input Pin . GND – 0.5 V to V
Storage Temperature (T
Junction Temperature (T

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +260°C

Analog Outputs to GND

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

2

Analog output short circuit to any power supply or common can be of an indefinite

duration.

) . . . . . . . . . . . . . . –65°C to +150°C

S

) . . . . . . . . . . . . . . . . . . . . . +150°C

J

2

␣ . . . . . . . . . . . GND – 0.5 V to V

+ 0.5 V

AA

AA

PACKAGE THERMAL PERFORMANCE

The 44-PQFP package used for this device takes advantage of
an ADI patented thermal coastline lead frame construction. This
maximizes heat transfer into the leads and reduces the package
thermal resistance.

The junction-to-ambient (θ

) thermal resistance in still air on a

JA

four-layer PCB is 35.5°C/W. The junction-to-case thermal resis­tance (θ

) is 13.75°C/W.

JC

ORDERING GUIDE

Temperature Package Package

Model Range Descriptions Options

Table I. Allowable Operating Conditions for KS and SU
Package Options

KS SU

Conditions 3 V 5 V 3 V 5 V

4 DAC ON Double 75R
4 DAC ON Low Power
4 DAC ON Buffering

1

Yes Yes Yes No

2

3

Yes Yes Yes No
Yes Yes Yes Yes

3 DAC ON Double 75R Yes Yes Yes No
3 DAC ON Low Power Yes Yes Yes Yes
3 DAC ON Buffering Yes Yes Yes Yes

2 DAC ON Double 75R Yes Yes Yes Yes
2 DAC ON Low Power Yes Yes Yes Yes
4 DAC ON Buffering Yes Yes Yes Yes

NOTES

1

DAC ON Double 75R refers to a condition where the DACs are terminated in
a double 75R load and low power mode is disabled.

2

DAC ON Low Power refers to a condition where the DACs are terminated in a
double 75R load and low power mode is enabled.

3

DAC ON Buffering refers to a condition where the DAC current is reduced to
5 mA and external buffers are used to drive the video load.

ADV7170KS 0°C to +70°C Plastic Quad Flatpack S-44
ADV7170SU 0°C to +70°C Thin Plastic Quad Flatpack SU-44
ADV7171KS 0°C to +70°C Plastic Quad Flatpack S-44
ADV7171SU 0°C to +70°C Thin Plastic Quad Flatpack SU-44

PIN CONFIGURATIONS

SET

SCRESET/

TTX

GND

TTXREQ

AA

V

GND

RTC

R

33
32
31
30
29
28
27
26
25
24
23

RESET

V

REF

DAC A
DAC B
V

AA

GND
V

AA

DAC D
DAC C
COMP
SDATA
SCLOCK

V

P10
P11
P12

GND

V

P3

GND

CLOCK

4344 36 35 3437

1

AA

P5
P6
P7
P8
P9

AA

PIN 1

2

IDENTIFIER

3
4
5
6
7
8

9
10
11

121314 15 16 17 18 192021 22

P14

P13

P2

P4

42

40 39 3841

ADV7170/ADV7171

PQFP/TQFP

TOP VIEW

(Not to Scale)

P15

HSYNC

P1

P0

ALSB

BLANK

FIELD/VSYNC

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7170/ADV7171 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, pr oper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

–8– REV. 0

WARNING!

ESD SENSITIVE DEVICE

ADV7170/ADV7171

PIN FUNCTION DESCRIPTIONS

Input/

Mnemonic Output Function

P15–P0 I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or 16-Bit YCrCb Pixel Port (P15–P0).

P0 represents the LSB.

CLOCK I TTL Clock Input. Requires a stable 27 MHz reference Clock for standard operation. Alter-

natively, a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.

HSYNC I/O HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (Master

Mode) or accept (Slave Mode) Sync signals.

FIELD/VSYNC I/O Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be

configured to output (Master Mode) or accept (Slave Mode) these control signals.

BLANK I/O Video Blanking Control Signal. The pixel inputs are ignored when this is Logic Level “0.”

This signal is optional.

SCRESET/RTC I This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It

can be configured as a subcarrier reset pin, in which case a high-to-low transition on this pin
will reset the subcarrier to Field 0. Alternatively, it may be configured as a Real-Time
Control (RTC) input.

V

REF

R

SET

COMP O Compensation Pin. Connect a 0.1 µF Capacitor from COMP to V

DAC A O PAL/NTSC Composite Video Output. Full-Scale Output is 180 IRE (1286 mV) for NTSC

DAC C O RED/S-Video C/V Analog Output.
DAC D O GREEN/S-Video Y/Y Analog Output
DAC B O BLUE/Composite/U Analog Output.
SCLOCK I MPU Port Serial Interface Clock Input.
SDATA I/O MPU Port Serial Data Input/Output.
ALSB I TTL Address Input. This signal set up the LSB of the MPU address.
RESET I The input resets the on chip timing generator and sets the ADV7170/ADV7171 into default

TTX/V

AA

TTXREQ/GND O Teletext Data Request Signal/ Defaults to GND

V

AA

GND G Ground Pin.

I/O Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
I A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of

the video signals.

. For Optimum Dynamic

AA

Performance in low power mode, the value of the COMP capacitor can be lowered to as low
as 2.2 nF.

and 1300 mV for PAL.

mode. This is NTSC operation, Timing Slave Mode 0, 8 Bit Operation, 2 × Composite and
S Video out and DAC B powered ON and DAC D powered OFF.

I Teletext Data/Defaults to V

when Teletext not Selected (enables backward compatibility to

AA

ADV7175/ADV7176).

when Teletext not Selected (enables back-

ward compatibility to ADV7175/ADV7176).

P Power Supply (+3 V to +5 V).

–9–REV. 0

ADV7170/ADV7171

GENERAL DESCRIPTION

The ADV7170/ADV7171 is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 8 or 16-bit component
video data into a standard analog baseband television signal
compatible with worldwide standards.

The on-board SSAF (Super Sub-Alias Filter) with extended
luminance frequency response and sharp stopband attenuation,
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution.

An advanced power management circuit enables optimal control
of power consumption in both normal operating modes and
power-down or sleep modes.

The ADV7170/ADV7171 also supports both PAL and NTSC
square pixel operation. The parts also incorporate WSS and
CGMS-A data control generation.

The output video frames are synchronized with the incoming
data timing reference codes. Optionally, the encoder accepts
(and can generate) HSYNC, VSYNC and FIELD timing sig­nals. These timing signals can be adjusted to change pulsewidth
and position while the part is in the master mode. The encoder
requires a single two times pixel rate (27 MHz) clock for stan­dard operation. Alternatively, the encoder requires a 24.54 MHz
clock for NTSC or 29.5 MHz clock for PAL square pixel mode
operation. All internal timing is generated on-chip.

A separate teletext port enables the user to directly input tele­text data during the vertical blanking interval.

The ADV7170/ADV7171 modes are set up over a two-wire
serial bidirectional port (I

2

C Compatible) with two slave addresses.

Functionally, the ADV7171 and ADV7170 are the same with
the exception that the ADV7170 can output the Macrovision
anticopy algorithm.

The ADV7170/ADV7171 is packaged in a 44-lead PQFP pack­age and a 44-lead TQFP package.

DATA PATH DESCRIPTION

For PAL B, D, G, H, I, M, N and NTSC M, N modes, YCrCb
4:2:2 data is input via the CCIR-656 Compatible Pixel Port at a
27 MHz data rate. The pixel data is demultiplexed to form

three data paths. Y typically has a range of 16 to 235, Cr and
Cb typically have a range of 128 ± 112; however, it is possible
to input data from 1 to 254 on both Y, Cb and Cr. The ADV7170/
ADV7171 supports PAL (B, D, G, H, I, M, N) and NTSC
(with and without pedestal) standards. The appropriate
SYNC, BLANK and Burst levels are added to the YCrCb
data. Macrovision antitaping (ADV7170 only), closed-captioning
and Teletext levels are also added to Y and the resultant data is
interpolated to a rate of 27 MHz. The interpolated data is
filtered and scaled by three digital FIR filters.

The U and V signals are modulated by the appropriate sub­carrier sine/cosine phases and added together to make up the
chrominance signal. The luma (Y) signal can be delayed 1–3
luma cycles (each cycle is 74 ns) with respect to the chroma
signal. The luma and chroma signals are then added together to
make up the composite video signal. All edges are slew rate
limited.

The YCrCb data is also used to generate RGB data with ap­propriate SYNC and BLANK levels. The RGB data is in
synchronization with the composite video output. Alternatively,
analog YUV data can be generated instead of RGB.

The four l0-bit DACs can be used to output:

1. Composite Video + RGB Video.

2. Composite Video + YUV Video.

3. Two Composite Video Signals + LUMA and CHROMA
(Y/C) Signals.

Alternatively, each DAC can be individually powered off if not
required.

Video output levels are illustrated in Appendix 6.

INTERNAL FILTER RESPONSE

The Y filter supports several different frequency responses,
including two low-pass responses, two notch responses, an
extended (SSAF) response, a CIF response and a QCIF re­sponse. The UV filter supports several different frequency re­sponses, including four low-pass responses, a CIF response and
a QCIF response, these can be seen in the following Figures 4
to 18.

FILTER TYPE FILTER SELECTION

MR04
LOW PASS (NTSC)
LOW PASS (PAL)
NOTCH (NTSC)
NOTCH (PAL)
EXTENDED (SSAF)
CIF
QCIF

MR03

0

0

0

0

0

1

0

1

1

0

1

0

1

1

Figure 4. Luminance Internal Filter Specifications

FILTER TYPE FILTER SELECTION

MR07

1.3 MHz LOW PASS

0.65 MHz LOW PASS

1.0 MHZ LOW PASS

2.0 MHz LOW PASS
RESERVED
CIF
QCIF

MR06

0

0

0

0

0

1

0

1

1

0

1

0

1

1

Figure 5. Chrominance Internal Filter Specifications

PASSBAND RIPPLE

MR02

0
1
0
1
0
1
0

PASSBAND RIPPLE

MR05

0
1
0
1
0
1
0

(dB)

0.091

0.15

0.015

0.095

0.051

0.018
MONOTONIC

(dB)

0.084
MONOTONIC
MONOTONIC

0.0645

0.084
MONOTONIC

3 dB BANDWIDTH

(MHz)

4.157

4.74

6.54

6.24

6.217

3.0

1.5

3 dB BANDWIDTH

(MHz)

1.395

0.65

1.0

2.2

0.7

0.5

STOPBAND

CUTOFF (MHz)

7.37

7.96

8.3

8.0

8.0

7.06

7.15

STOPBAND

CUTOFF (MHz)

3.01

3.64

3.73

5.0

3.01

4.08

STOPBAND

ATTENUATION (dB)

–56
–64
–68
–66
–61
–61
–50

STOPBAND

ATTENUATION (dB)

–45
–58.5
–49
–40

–45
–50

–10– REV. 0

0

FREQUENCY – MHz

0

–70

0

2

MAGNITUDE – dB

4681012

–10

–30

–40

–50

–60

–20

FREQUENCY – MHz

0

–70

02

MAGNITUDE – dB

4681012

–10

–30

–40

–50

–60

–20

FREQUENCY – MHz

0

–70

02

MAGNITUDE – dB

4681012

–10

–30

–40

–50

–60

–20

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

0

4681012

2

FREQUENCY – MHz

Figure 6. NTSC Low-Pass Luma Filter

0

–10

–20

–30

ADV7170/ADV7171

Figure 9. PAL Notch Luma Filter

–40

MAGNITUDE – dB

–50

–60

–70

0

Figure 7. PAL Low-Pass Luma Filter

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

0

Figure 8. NTSC Notch Luma Filter

4681012

2

2

FREQUENCY – MHz

4681012

FREQUENCY – MHz

Figure 10. Extended Mode (SSAF) Luma Filter

Figure 11. CIF Luma Filter

–11–REV. 0

ADV7170/ADV7171

FREQUENCY – MHz

0

–70

02

MAGNITUDE – dB

4681012

–10

–30

–40

–50

–60

–20

FREQUENCY – MHz

0

–70

02

MAGNITUDE – dB

4681012

–10

–30

–40

–50

–60

–20

FREQUENCY – MHz

0

–70

02

MAGNITUDE – dB

4681012

–10

–30

–40

–50

–60

–20

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02

4681012

FREQUENCY – MHz

Figure 12. QCIF Luma Filter

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02

4681012

FREQUENCY – MHz

Figure 13. 1.3 MHz Low-Pass Chroma Filter

0

Figure 15. 1.0 MHz Low-Pass Chroma Filter

Figure 16. 2.0 MHz Low-Pass Chroma Filter

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02

4681012

FREQUENCY – MHz

Figure 14. 0.65 MHz Low-Pass Chroma Filter

Figure 17. CIF Chroma Filter

–12– REV. 0

ADV7170/ADV7171

0

–10

–20

–30

–40

MAGNITUDE – dB

–50

–60

–70

02

4681012

FREQUENCY – MHz

Figure 18. QCIF Chroma Filter

COLOR BAR GENERATION

The ADV7170/ADV7171 can be configured to generate 75%
amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75%
amplitude, 100% saturation (100/0/75/0) for PAL color bars.
These are enabled by setting MR17 of Mode Register 1 to
Logic “1.”

SQUARE PIXEL MODE

The ADV7170/ADV7171 can be used to operate in square pixel
mode. For NTSC operation, an input clock of 24.5454 MHz is
required. Alternatively, for PAL operation, an input clock of

29.5 MHz is required. The internal timing logic adjusts accord­ingly for square pixel mode operation.

COLOR SIGNAL CONTROL

The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.

BURST SIGNAL CONTROL

The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.

NTSC PEDESTAL CONTROL

The pedestal on both odd and even fields can be controlled on a
line-by-line basis using the NTSC Pedestal Control Registers.
This allows the pedestals to be controlled during the vertical
blanking interval (Lines 10 to 25 and Lines 273 to 288).

PIXEL TIMING DESCRIPTION

The ADV7170/ADV7171 can operate in either 8-bit or
16-bit YCrCb Mode.

8-Bit YCrCb Mode

This default mode accepts multiplexed YCrCb inputs through
the P7-P0 pixel inputs. The inputs follow the sequence Cb0, Y0
Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a
rising clock edge.

16-Bit YCrCb Mode

This mode accepts Y inputs through the P7–P0 pixel inputs and
multiplexed CrCb inputs through the P15–P8 pixel inputs. The
data is loaded on every second rising edge of CLOCK. The inputs
follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.

SUBCARRIER RESET

Together with the SCRESET/RTC pin, and bits MR22 and
MR21 of Mode Register 2, the ADV7170/ADV7171 can be
used in subcarrier reset mode. The subcarrier will reset to Field
0 at the start of the following field when a low-to-high transition
occurs on this input pin.

REAL-TIME CONTROL

Together with the SCRESET/RTC pin, and Bits MR22 and
MR21 of Mode Register 2, the ADV7170/ADV7171 can be
used to lock to an external video source. The real-time control
mode allows the ADV7170/ADV7171 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs a digital
datastream in the RTC format (such as a ADV7185 video de­coder, see Figure 19), the part will automatically change to the
compensated subcarrier frequency on a line-by-line basis. This
digital datastream is 67 bits wide and the subcarrier is contained
in Bits 0 to 21. Each bit is 2 clock cycles long. 00Hex should be
written into all four subcarrier frequency registers when using
this mode.

VIDEO TIMING DESCRIPTION

The ADV7170/ADV7171 is intended to interface to off­the-shelf MPEG1 and MPEG2 Decoders. Consequently, the
ADV7170/ADV7171 accepts 4:2:2 YCrCb Pixel Data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing
generator. The ADV7170/ADV7171 generates all of the re­quired horizontal and vertical timing periods and levels for the
analog video outputs.

The ADV7170/ADV7171 calculates the width and placement of
analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration and
equalization pulses are inserted where required.

In addition, the ADV7170/ADV7171 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock
of 29.5 MHz for PAL. The internal horizontal line counters
place the various video waveform sections in the correct location
for the new clock frequencies.

The ADV7170/ADV7171 has four distinct master and four
distinct slave timing configurations. Timing Control is estab­lished with the bidirectional SYNC, BLANK and FIELD/
VSYNC pins. Timing Mode Register 1 can also be used to vary
the timing pulsewidths and where they occur in relation to each
other.

–13–REV. 0

ADV7170/ADV7171

COMPOSITE

VIDEO

e.g., VCR

OR CABLE

VIDEO

DECODER

(e.g., ADV7185)

MPEG

DECODER

CLOCK
SCRESET/RTC

M
U

P7–P0

X

HSYNC

FIELD/VSYNC

ADV7170/ADV7171

GREEN/LUMA/Y

RED/CHROMA/V

BLUE/COMPOSITE/U

COMPOSITE

H/LTRANSITION

COUNT START

RTC

TIME SLOT: 01

NOTES:

1

FSC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7175A/ADV7176A FSC DDS REGISTER IS

PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD

F

SC

BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7170/ADV7171.

2

SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE

3

RESET BIT
RESET ADV7175A/ADV7176A’s DDS

128

LOW

14 BITS

RESERVED

13

NOT USED IN

ADV7175A/ADV7176A

0

14

4 BITS

RESERVED

21

19

FSCPLL INCREMENT

VALID

SAMPLE

SAMPLE

INVALID

SEQUENCE

2

5 BITS

RESERVED

1

8/LLC

BIT

0

6768

RESET

BIT

RESERVED

3

Figure 19. RTC Timing and Connections

Vertical Blanking Data Insertion

It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre-/post-equalization
pulses (see Figures 21 to 32). This mode of operation is called “Partial Blanking” and is selected by setting MR31 to 1. It allows the
insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data
stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by
setting MR31 to 0.

The complete VBI is comprised of the following lines:
525/60 Systems, Lines 525 to 21 for Field 1 and Lines 262 to Line 284 for Field 2.
625/50 Systems, Lines 624 to Line 22 and Lines 311 to 335.

The “Opened VBI” consists of:
525/60 Systems, Lines 10 to 21 for Field 1 and second half of Line 273 to Line 284 for Field 2.
625/50 Systems, Line 7 to Line 22 and Lines 319 to 335.

Mode 0 (CCIR-656): Slave Option

(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7170/ADV7171 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data.

All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 20. The HSYNC, FIELD/VSYNC and BLANK
(if not used) pins should be tied high during this mode.

–14– REV. 0

ANALOG

522 523 524 525 1 2 3 4

5

67

8

9

10 11 20 21 22

DISPLAY

DISPLAY

VERTICAL BLANK

ODD FIELDEVEN FIELD

H

V

F

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

283

284

285

ODD FIELD

EVEN FIELD

DISPLAY

DISPLAY

VERTICAL BLANK

H

V

F

VIDEO

ADV7170/ADV7171

INPUT PIXELS

NTSC/PAL M SYSTEM

(525 LlNES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

EAV CODE

C

FF0000X

Y

Y

r

4 CLOCK

4 CLOCK

END OF ACTIVE

VIDEO LINE

8

10801

0

Y

0

FF00FFABABA

ANCILLARY DATA

268 CLOCK

280 CLOCK

B

(HANC)

801

0

SAV CODE

8

10FF0

0

0

XYC

Y

0

0

b

4 CLOCK

4 CLOCK

START OF ACTIVE

VIDEO LINE

C

C

Y

Y

b

r

1440 CLOCK

1440 CLOCK

C

C

Y

b

r

Figure 20. Timing Mode 0 (Slave Mode)

Mode 0 (CCIR-656): Master Option

(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7170/ADV7171 generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time

Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is
output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). The H, V and F transitions
relative to the video waveform are illustrated in Figure 23.

Figure 21. Timing Mode 0 (NTSC Master Mode)

–15–REV. 0

ADV7170/ADV7171

DISPLAY

622 623 624 625 1 2 3 4

H

V

F

DISPLAY

309 310 311 312 314 315 316 317

H

V

F

ODD FIELD EVEN FIELD

ODD FIELDEVEN FIELD

313

Figure 22. Timing Mode 0 (PAL Master Mode)

VERTICAL BLANK

5

VERTICAL BLANK

67

318

319 320

DISPLAY

22 23

21

DISPLAY

335 336

334

ANALOG

VIDEO

H

F

V

Figure 23. Timing Mode 0 Data Transitions (Master Mode)

–16– REV. 0

ADV7170/ADV7171

Mode 1: Slave Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7170/ADV7171 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input

when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is dis-
abled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure
24 (NTSC) and Figure 25 (PAL).

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

284

DISPLAY

285

DISPLAY

522 523 524 525

DISPLAY DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1234

ODD FIELDEVEN FIELD

ODD FIELD EVEN FIELD

VERTICAL BLANK

678

5

VERTICAL BLANK

9

10 11

20 21 22

283

Figure 24. Timing Mode 1 (NTSC)

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

DISPLAY

622 623 624 625 1 2 3 4

ODD FIELDEVEN FIELD

DISPLAY

309 310 311 312 313 314 315 316

ODD FIELD EVEN FIELD

VERTICAL BLANK

VERTICAL BLANK

Figure 25. Timing Mode 1 (PAL)

5

317

67

318 319

320

DISPLAY

21 22 23

DISPLAY

334 335 336

–17–REV. 0