ANALOG DEVICES ADV7150 Service Manual

现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!

CMOS 220 MHz True-Color Graphics

a

FEATURES
220 MHz, 24-Bit (30-Bit Gamma Corrected) True Color
Triple 10-Bit “Gamma Correcting” D/A Converters
Triple 256 3 10 (256 3 30) Color Palette RAM
On-Chip Clock Control Circuit
Palette Priority Select Registers
RS-343A/RS-170 Compatible Analog Outputs
TTL Compatible Digital Inputs
Standard MPU l/O Interface

10-Bit Parallel Structure

8+2 Byte Structure
Programmable Pixel Port: 24-Bit, 15-Bit and

Programmable Pixel Port: 8-Bit (Pseudo)

Pixel Data Serializer

Multiplexed Pixel Input Ports; 1:1, 2:1, 4:1
+5 V CMOS Monolithic Construction
160-Lead Plastic Quad Flatpack (QFP)
Thermally Enhanced to Achieve u

MODES OF OPERATION
24-Bit True Color (30-Bit Gamma Corrected)

@ 220 MHz

@ 170 MHz

@ 135 MHz

@ 110 MHz

< 1.08C/W

JC

Triple 10-Bit Video RAM-DAC

ADV7150

@ 85 MHz

8-Bit Pseudo Color
15-Bit True Color

APPLICATIONS
High Resolution, True Color Graphics
Professional Color Prepress Imaging

GENERAL DESCRIPTION

The ADV7150 (ADV®) is a complete analog output, Video
RAM-DAC on a single CMOS monolithic chip. The part is spe­cifically designed for use in high performance, color graphics
workstations. The ADV7150 integrates a number of graphic
functions onto one device allowing 24-bit direct True-Color op­eration at the maximum screen update rate of 220 MHz. The
ADV7150 implements 30-bit True Color in 24-bit frame buffer
designs. The part also supports other modes, including 15-bit
True Color and 8-bit Pseudo or Indexed Color. Either the Red,
Green or Blue input pixel ports can be used for Pseudo Color.

(Continued on page 12)

ADV is a registered trademark of Analog Devices, Inc.

FUNCTIONAL BLOCK DIAGRAM

V

AA

RED (R7–R0),
GREEN (G7–G0),
BLUE (B7–B0)
COLOR DATA

PALETTE
SELECTS

(PS0, PS1)

LOADIN

LOADOUT

PRGCKOUT

SCKOUT

SCKIN

SYNC

BLANK

CLOCK
CLOCK

24

A

B

C

D

P

24

X
E

24

L

P
O

24

R
T

8

CLOCK CONTROL

CLOCK DIVIDE

SYNCHRONIZATION

÷32 ÷16, ÷8, ÷4, ÷2

ECL TO CMOS

I

&

CIRCUIT

96

8

ADV7150

MUX

4:1

MUX

4:1

ADDRESS
REGISTER

8
8
8

2

MODE

REGISTER

ADDR

(A7–A0)

CE R/W C0 C1

(MR1)

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

256-COLOR/GAMMA

PALETTE RAM

RED

256 x 10

GREEN

256 x 10

BLUE

256 x 10

CONTROL REGISTERS

PIXEL MASK

REGISTER

TEST

REGISTERS

ID

REGISTER

MPU PORT

10 (8+2)

D9 – D0

COMMAND

REGISTERS

(CR1–CR3)

REVISION

REGISTER

10

10

10

DATA TO

PALETTES

REGISTER

10-BIT

RED DAC

10-BIT

GREEN DAC

10-BIT

BLUE DAC

30

RED

SYNC

OUTPUT

VOLTAGE

REFERENCE

CIRCUIT

COLOR REGISTERS

BLUE

REGISTER

GREEN

REGISTER

GND

IOR
IOR

IOG
IOG

IOB
IOB

I

PLL

SYNCOUT
V

REF

R

SET

COMP

© Analog Devices, Inc., 1996

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

ADV7150–SPECIFICA TIONS

CL = 10 pF); IOR, IOG, IOB = GND. All specifications T

MIN

1

(V

= +5 V; V

AA

2

to T

unless otherwise noted.)

MAX

= +1.235 V; R

REF

= 280 V. IOR, IOG, IOB (RL = 37.5 V,

SET

Parameter All Versions Unit Test Conditions/Comments

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits
Accuracy (Each DAC)

Integral Nonlinearity ±1 LSB max
Differential Nonlinearity ±1 LSB max Guaranteed Monotonic
Gray Scale Error ±5 % Gray Scale max

Coding Binary

DIGITAL INPUTS (Excluding CLOCK, CLOCK)

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

2 V min

0.8 V max
±10 µA max VIN = 0.4 V or 2.4 V
10 pF max

CLOCK INPUTS (CLOCK, CLOCK)

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

VAA – 1.0 V min
VAA – 1.6 V max
±10 µA max VIN = 0.4 V or 2.4 V
10 pF typ

DIGITAL OUTPUT

Output High Voltage, V
Output Low Voltage, V

OL

OH

2.4 V min I

0.4 V max I

SOURCE

= 3.2 mA

SINK

= 400 µA

Floating-State Leakage Current 20 µA max
Floating-State Output Capacitance 20 pF typ

ANALOG OUTPUTS

Gray Scale Current Range 15/22 mA min/max
Output Current

White Level Relative to Blank 17.69/20.40 mA min/max Typically 19.05 mA
White Level Relative to Black 16.74/18.50 mA min/max Typically 17.62 mA
Black Level Relative to Blank 0.95/1.90 mA min/max Typically 1.44 mA
Blank Level on IOR, IOB 0/50 µA min/max Typically 5 µA
Blank Level on IOG 6.29/8.96 mA min/max Typically 7.62 mA
Sync Level on IOG 0/50 µA min/max Typically 5 µA

LSB Size 17.22 µA typ
DAC-to-DAC Matching 3 % max Typically 1%
Output Compliance, V
Output Impedance, R

OUT

Output Capacitance, C

OC

OUT

0/+1.4 V min/V max
100 kΩ typ
30 pF max I

OUT

= 0 mA

VOLTAGE REFERENCE

Voltage Reference Range, V
Input Current, I

VREF

REF

1.14/1.26 V min/V max V
+5 µA typ

= 1.235 V for Specified Performance

REF

POWER REQUIREMENTS

V

AA

3

I

AA

3

I

AA

I

AA

I

AA

I

AA

5 V nom
400 mA max 220 MHz Parts
370 mA max 170 MHz Parts
350 mA max 135 MHz Parts
330 mA max 110 MHz Parts
315 mA max 85 MHz Parts

Power Supply Rejection Ratio 0.5 %/% max Typically 0.12%/%: COMP = 0.1 µF

DYNAMIC PERFORMANCE

Clock and Data Feedthrough

Glitch Impulse 50 pV secs typ
DAC-to-DAC Crosstalk

NOTES

1

±5% for all versions.

2

Temperature range (T

3

Pixel Port is continuously clocked with data corresponding to a linear ramp. TJ = 100°C.

4

Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.

5

TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured the 10% and 90% points. Timing reference points at 50% for inputs and outputs.

6

DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.

Specifications subject to change without notice.

MIN

to T

4, 5

6

): 0°C to +70°C; TJ (Silicon Junction Temperature) ≤ 100°C.

MAX

–30 dB typ

–23 dB typ

–2–

REV. A

TIMING CHARACTERISTICS

IOR, IOG, I0B = GND. All specifications T

CLOCK CONTROL AND PIXEL PORT

MIN

to T

4

= +5 V; V

AA

3

unless otherwise noted.)

MAX

= +1.235 V; R

REF

= 280 V. IOR, IOG, IOB (RL = 37.5 V, CL = 10 pF);

SET

1

2

(V

220 MHz 170 MHz 135 MHz 110 MHz 85 MHz

Parameter Version Version Version Version Version Units

ADV7150

Conditions/Comments

f

CLOCK

t

1

t

2

t

3

t

4

f

LOADIN

220 170 135 110 85 MHz max Pixel CLOCK Rate

4.55 5.88 7.4 9.1 11.77 ns min Pixel CLOCK Cycle Time
2 2.5 3.2 4 4 ns min Pixel CLOCK High Time
2 2.5 3 4 4 ns min Pixel CLOCK Low Time
10 10 10 10 10 ns max Pixel CLOCK to LOADOUT Delay

LOADIN Clocking Rate
1:1 Multiplexing 110 110 110 110 85 MHz max
2:1 Multiplexing 110 85 67.5 55 42.5 MHz max
4:1 Multiplexing 55 42.5 33.75 27.5 21.25 MHz max

t

5

LOADIN Cycle Time
1:1 Multiplexing 9.1 9.1 9.1 9.1 9.1 ns min
2:1 Multiplexing 9.1 11.76 14.8 18.18 23.53 ns min
4:1 Multiplexing 18.18 23.53 29.63 36.36 47.1 ns min

t

6

LOADIN High Time
1:1 Multiplexing 44444ns min
2:1 Multiplexing 45689ns min
4:1 Multiplexing 8 9 12 15 18 ns min

t

7

LOADIN Low Time
1:1 Multiplexing 44444ns min
2:1 Multiplexing 45689ns min
4:1 Multiplexing 8 9 12 15 18 ns min

t

8

t

9

t

10

5

τ–t

11
6

t

PD

1:1 Multiplexing 55555CLOCKs (1 × CLOCK = t

00000ns minPixel Data Setup Time
55555ns minPixel Data Hold Time
00000ns minLOADOUT to LOADIN Delay
τ–5 τ–5 τ–5 τ–5 τ–5 ns max LOADOUT to LOADIN Delay

Pipeline Delay

)

1

2:1 Multiplexing 66666CLOCKs
4:1 Multiplexing 88888CLOCKs

t

12

t

13

t

14

t

15

ANALOG OUTPUTS

10 10 10 10 10 ns max Pixel CLOCK to PRGCKOUT Delay
55555ns maxSCKIN to SCKOUT Delay
55555ns minBLANK to SCKIN Setup Time
11111ns minBLANK to SCKIN Hold Time

7

220 MHz 170 MHz 135 MHz 110 MHz 85 MHz

Parameter Version Version Version Version Version Units Conditions/Comments

t

16

t

17

t

18

t

SK

15 15 15 15 15 ns typ Analog Output Delay
11111ns typAnalog Output Rise/Fall Time
15 15 15 15 15 ns typ Analog Output Transition Time
22222ns maxAnalog Output Skew (IOR, IOG, IOB)
00000ns typ

MPU PORTS

8, 9

220 MHz 170 MHz 135 MHz 110 MHz 85 MHz

Parameter Version Version Version Version Version Units Conditions/Comments

t

19

t

20

t

21

t

22

8

t

23

9

t

24

9

t

25

33333ns minR/W, C0, C1 to CE Setup Time
10 10 10 10 10 ns min R/W, C0, C1 to CE Hold Time
45 45 45 45 45 ns min CE Low Time
25 25 25 25 25 ns min CE High Time
55555ns minCE Asserted to Databus Driven
45 45 45 45 45 ns max CE Asserted to Data Valid
20 20 20 20 20 ns max CE Disabled to Databus Three-Stated
55555ns min

t

26

t

27

REV. A

20 20 20 20 20 ns min Write Data (D0–D9) Setup Time
55555ns minWrite Data (D0–D9) Hold Time

–3–

ADV7150

NOTES

1

TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. ECL inputs (CLOCK, CLOCK) are

VAA–0.8 V to VAA–1.8 V, with input rise/fall times ≤ 2 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out­puts. Analog output load ≤ 10 pF. Databus (D0–D9) loaded as shown in Figure 1. Digital output load for LOADOUT, PRGCKOUT, SCKOUT, I
SYNCOUT ≤ 30 pF.

2

±5% for all versions.

3

Temperature range (T

4

Pixel Port consists of the following inputs: Pixel Inputs: RED [A, B, C, D]; GREEN [A, B, C, D]; BLUE [A, B, C, D], Palette Selects: PS0 [A, B, C, D]; PS1

[A, B, C, D]; Pixel Controls: SYNC, BLANK; Clock Inputs: CLOCK, CLOCK, LOADIN, SCKIN; Clock Outputs: LOADOUT, PRGCKOUT, SCKOUT.

5

τ is the LOADOUT Cycle Time and is a function of the Pixel CLOCK Rate and the Multiplexing Mode: 1:1 multiplexing; τ = CLOCK = t1 ns. 2:1 Multi-

plexing; τ = CLOCK × 2 = 2 × t1 ns. 4:1 Multiplexing; τ = CLOCK × 4 = 4 × t1 ns.

6

These fixed values for Pipeline Delay are valid under conditions where t10 and τ-t11 are met. If either t10 or τ-t11 are not met, the part will operate but the Pipe line De-

lay is increased by 2 additional CLOCK cycles for 2:1 Mode and is increased by 4 additional CLOCK cycles for 4:1 Mode, after calibration is performed.

7

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Output rise/fall time measured between the 10%

MIN

to T

): 0°C to +70°C; TJ (Silicon Junction Temperature) ≤ 100°C.

MAX

and 90% points of full-scale transition. Transition time measured from the 50% point of full-scale transition to the output remaining within 2% of the final output
value (Transition time does not include clock and data feedthrough).

8

t23 and t24 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V.

9

t25 is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-

lated back to remove the effects of charging the 100 pF capacitor. This means that the time, t25, quoted in the Timing Characteristics is the true value for the device
and as such is independent of external databus loading capacitances.

Specifications subject to change without notice.

I

SINK

TO
OUTPUT
PIN

100pF

+2.1V

PLL

and

CLOCK

CLOCK

LOADOUT

(1:1 MULTIPLEXING)

LOADOUT

(2:1 MULTIPLEXING)

LOADOUT

(4:1 MULTIPLEXING)

LOADIN

PIXEL INPUT

DATA*

I

SOURCE

Figure 1. Load Circuit for Databus Access and Relinquish Times

t

2

VALID

DATA

t

3

CLOCK

t

6

t

7

VALID

DATA

t

1

t

4

Figure 2. LOADOUT vs. Pixel Clock Input (CLOCK,

t

5

t8t

9

VALID

DATA

)

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC

Figure 3. LOADIN vs. Pixel Input Data

–4–

REV. A

CLOCK

LOADOUT

LOADIN

ADV7150

t

10

PIXEL INPUT

DATA*

ANALOG

OUTPUT

DATA

A

B

N

N

C

D

N

N

DIGITAL INPUT TO ANALOG

OUTPUT PIPELINE

IOR, IOR
IOG, IOG
IOB, IOB
I

PLL, SYNCOUT

A

N+1 BN+1

C

N+1DN+1

A

N–1

t

PD

B

N–1CN–1DN–1

A

N+2 BN+2

C

N+2 DN+2

ANBNCNDNA

N+1BN+1CN+1DN+1

A

N+2BN+2CN+2DN+2

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC

Figure 4. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (4:1 Multiplex Mode)

CLOCK

τ

τ– t

11

LOADOUT

LOADIN

PIXEL INPUT

DATA*

ANALOG

OUTPUT

DATA

B

N–1CN–1DN–1

A

N+1 BN+1

C

N+1DN+1

ANBNCND

IOR, IOR
IOG, IOG
IOB, IOB
I

PLL, SYNCOUT

A

B

N

N

C

D

N

N

DIGITAL INPUT

TO ANALOG

OUTPUT

PIPELINE

A

N–1

t

PD

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC

A

N+2 BN+2

C

N+2 DN+2

A

N

N+1BN+1CN+1DN+1

A

N+2BN+2CN+2DN+2

Figure 5. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (4:1 Multiplex Mode)

REV. A

–5–

ADV7150

LOADOUT

LOADIN

CLOCK

t

10

PIXEL INPUT

DATA*

ANALOG

OUTPUT

DATA

A

B

N

N

DIGITAL INPUT TO ANALOG

OUTPUT PIPELINE

IOR, IOR
IOG, IOG
IOB, IOB
I

PLL, SYNCOUT

A

N+1 BN+1

A

N+2 BN+2

A

A

N-1BN-1

t

PD

B

N

A

N

N+1BN+1AN+2BN+2

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC

Figure 6. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (2:1 Multiplex Mode)

CLOCK

τ

τ– t

11

LOADOUT

LOADIN

PIXEL INPUT

DATA*

A

B

N

N

DIGITAL INPUT TO ANALOG

OUTPUT PIPELINE

A

N+1 BN+1

A

N+2 BN+2

ANALOG

OUTPUT

DATA

IOR, IOR
IOG, IOG
IOB, IOB
I

PLL, SYNCOUT

B

A

N-1BN-1

t

PD

A

N

A

N

N+1BN+1AN+2

B

N+2

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC

Figure 7. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (2:1 Multiplex Mode)

–6–

REV. A

CLOCK

PRGCKOUT

(CLOCK/4)

PRGCKOUT

(CLOCK/8)

PRGCKOUT

(CLOCK/16)

PRGCKOUT

(CLOCK/32)

SCKIN

BLANK

ADV7150

t

12

Figure 8. Pixel Clock Input vs. Programmable Clock Output (PRGCKOUT)

t

13

t

15

t

14

BLANKING

PERIOD

SCKOUT

END OF SCAN LINE (N)

START OF SCAN LINE (N+1)

Figure 9. Video Data Shift Clock Input (SCKIN) & BLANK vs. Video Data Shift Clock Output (SCKOUT)

CLOCK

t

18

WHITE LEVEL

90 %

50 %

10 %
BLACK LEVEL

NOTE:
THIS DIAGRAM IS NOT TO SCALE. FOR THE PURPOSES OF
CLARITY, THE ANALOG OUTPUT WAVEFORM IS MAGNIFIED IN
TIME AND AMPLITUDE W.R.T THE CLOCK WAVEFORM.
I

AND SYNCOUT ARE DIGITAL VIDEO OUTPUT SIGNALS.

PLL

t

IS THE ONLY RELEVENT OUTPUT TIMING SPECIFICATION

16

FOR I

AND SYNCOUT.

PLL

FULL-SCALE
TRANSITION

ANALOG

OUTPUTS

IOR, IOR
IOG, IOG
IOB, IOB
I

PLL, SYNCOUT

t

16

t

17

REV. A

Figure 10. Analog Output Response vs. CLOCK

–7–

ADV7150

R/W, C0, C1

(READ MODE)

D0–D9

t

19

CONTROL DATA

CE

VALID

t

23

t

20

t

21

t

22

t

24

R/W = 1

t

25

D0–D9

(WRITE MODE)

R/W = 0

t

26

t

27

Figure 11. Microprocessor Port (MPU) Interface Timing

RECOMMENDED OPERATING CONDITION

Parameter Symbol Min Typ Max Units

Power Supply V
Ambient Operating Temperature T
Reference Voltage V
Output Load R

AA
A
REF
L

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7150 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS

1

VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Voltage on Any Digital Pin . . . . GND – 0.5 V to V

Ambient Operating Temperature (T
Storage Temperature (T
Junction Temperature (T

) . . . . . . . . . . . . . . –65°C to +150°C

S

) . . . . . . . . . . . . . . . . . . . . +150°C

J

) . . . . . –55°C to +125°C

A

+ 0.5 V

AA

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +260°C

Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . +220°C

Analog Outputs to GND

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.

2

. . . . . . . . . . . . . GND – 0.5 to V

AA

4.75 5.00 5.25 Volts
0 +70 °C

1.14 1.235 1.26 Volts

37.5 Ω

WARNING!

ESD SENSITIVE DEVICE

16-Lead QFP Configuration

160 121

1

PIN NO. 1
IDENTIFIER

ROW A

ROW D

ADV7150 QFP

TOP VIEW

(NOT TO SCALE)

ROW C

120

ORDERING GUIDE

1, 2, 3

Speed

220 MHz ADV7150LS220 110 MHz ADV7150LS110
170 MHz ADV7150LS170 85 MHz ADV7150LS85
135 MHz ADV7150LS135

NOTES

1

ADV7150 is packaged in a 160-pin plastic quad flatpack, QFP.

2

All devices are specified for 0°C to +70°C operation.

3

Contact sales office for latest information on package design.

–8–

40

41 80

ROW B

81

REV. A

ADV7150

ADV7150 PIN ASSIGNMENTS

Pin Pin Pin Pin
Number Mnemonic Number Mnemonic Number Mnemonic Number Mnemonic

1G3
2G3
3G3
4G3
5G4
6G4
7G4
8G4
9G5
10 G5
11 G5
12 G5

A
B
C
D
A
B
C
D
A
B
C
D

41 PS1
42 B0
43 B0
44 B0
45 B0
46 B1
47 B1
48 B1
49 B1
50 B2
5 1 B2

52 B2
13 CLOCK 53 B2
14 CLOCK 54 B3
15 LOADIN 55 B3
16 LOADOUT 56 B3
17 V
18 V

AA
AA

57 B3

58 B4
19 PRGCKOUT 59 B4
20 SCKIN 60 B4
21 SCKOUT 61 B4
22 SYNCOUT 62 B5
23 GND 63 B5
24 GND 64 B5
25 GND 65 B5
26 G6
27 G6
28 G6
29 G6
30 G7
31 G7
32 G7
33 G7
34 PS0
35 PS0
36 PS0
37 PS0
38 PS1
39 PS1
40 PS1

NC = No Connect.

A
B
C
D
A
B
C
D

A
B
C
D
A
B
C

66 B6

67 B6

68 B6

69 B6

70 B7

71 B7

72 B7

73 B7

74 CE 114 V

75 R/W 115 SYNC 155 G1

76 C0 116 BLANK 1 56 G1

77 C1 117 R0

78 D0 118 R0

79 D1 119 R0

80 GND 120 R0

D
A
B
C

D
A
B
C

D
A
B
C

D
A
B
C

D
A
B
C

D
A
B
C

D
A
B
C

D
A
B
C

D

81 NC 121 R1
82 D2 122 R1
83 NC 123 R1
84 GND 124 R1
85 GND 125 R2
86 GND 126 R2
87 D3 127 R2
88 D4 128 R2
89 D5 129 R3
90 V

AA

130 R3
91 D6 131 R3
92 D7 132 R3
93 D8 133 R4
94 D9 134 R4
95 GND 135 R4
96 GND 136 R4
97 GND 137 R5
98 IOB 138 R5
99 IOR 139 R5
100 IOG 140 R5
101 IOB 141 R6
102 IOG 142 R6
103 V
104 V
105 V

AA
AA
AA

143 R6

144 R6

145 R7
106 IOR 146 R7
107 COMP 147 R7
108 V
109 R
110 I

REF
SET

PLL

148 R7

149 G0

150 G0
111 GND 151 G0
112 V
113 V

AA
AA
AA

A
B
C
D

152 G0

153 G1

154 G1

157 G2

158 G2

159 G2

160 G2

A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D

A
B
C
D
A
B
C
D
A
B
C
D

REV. A

–9–

ADV7150

PIN FUNCTION DESCRIPTION

Mnemonic Function

RED (R0A . . . R0D–R7A . . . R7D), Pixel Port (TTL Compatible Inputs): 96 pixel select inputs, with 8 bits each for Red, 8
GREEN (G0
BLUE (B0

PS0

. . . PS0D, PS1A . . . PS1

A

LOADIN Pixel Data Load Input (TTL Compatible Input). This input latches the multiplexed

LOADOUT Pixel Data Load Output (TTL Compatible Output). This output control signal runs at

PRGCKOUT Programmable Clock Output (TTL Compatible Output). This output control signal

SCKIN Video Shift Clock Input (TTL Compatible Input). The signal on this input is internally

SCKOUT Video Shift Clock Output (TTL Compatible Output). This output is a synchronously

CLOCK,

BLANK Composite Blank (TTL Compatible Input). This video control signal drives the analog

SYNC Composite-Sync Input (TTL Compatible Input). This video control signal drives the

SYNCOUT Composite-Sync Output (TTL Compatible Output). This video output is a delayed

D0–D9 Databus (TTL Compatible Input/Output Bus). Data, including color palette values and

CE Chip Enable (TTL Compatible Input). This input must be at Logic “0,” when writing

. . . G0D–G7A. . . G7D), bits for Green and 8 bits for Blue. Each bit is multiplexed [A-D] 4:1, 2:1 or 1:1. It can

A

. . . B0D–B7A . . . B7D) be configured for 24-Bit True-Color Data, 8-Bit Pseudo-Color Data and 15-Bit True-Color

A

Data formats. Pixel Data is latched into the device on the rising edge of LOADIN.

D

Palette Priority Selects (TTL Compatible Inputs): These pixel port select inputs deter­mine whether or not the device’s pixel data port is selected on a pixel by pixel basis.
The palette selects allow switching between multiple palette devices. The device can be
preprogrammed to completely shut off the DAC analog outputs. If the values of PS0
and PS1 match the values programmed into bits MR16 and MR17 of the Mode Regis­ter, then the device is selected. Each bit is multiplexed [A-D] 4:1, 2:1 or 1:1. PS0 and
PS1 are latched into the device on the rising edge of LOADIN.

pixel data, including PS0–PS1,

BLANK and SYNC into the device.

a divided down frequency of the pixel CLOCK input. Its frequency is a function of the
multiplex rate. It can be used to directly or indirectly drive LOADIN

f

LOADOUT

= f

CLOCK

/M

where M = 1 for 1:1 Multiplex Mode

where M = 2 for 2:1 Multiplex Mode
where M = 4 for 4:1 Multiplex Mode.

runs at a divided down frequency of the pixel CLOCK input. Its frequency is user
programmable and is determined by bits CR30 and CR31 of Command Register 3

f

PRGCKOUT

= f

CLOCK

/N

where N = 4, 8, 16 and 32.

gated synchronously with the

BLANK signal. The resultant output, SCKOUT, is a

video clocking signal that is stopped during video blanking periods.

gated version of SCKIN and

BLANK. SCKOUT, is a video clocking signal that is

stopped during video blanking periods.

CLOCK Clock Inputs (ECL Compatible Inputs). These differential clock inputs are designed to

be driven by ECL logic levels configured for single supply (+5 V) operation. The clock
rate is normally the pixel clock rate of the system.

outputs to the blanking level.

IOG analog output to the
CR22 in Command Re
output, otherwise the

version of

SYNC. The delay corresponds to the number of pipeline stages of the device.

SYNC level. It is only asserted during the blanking period.

gister 2 must be set if SYNC is to be decoded onto the analog

SYNC input is ignored.

device control information is written to and read from the device over this 10-bit, bidi­rectional databus. 10-bit data or 8-bit data can be used. The databus can be configured
for either 10-bit parallel data or byte data (8+2) as well as standard 8-bit data. Any un­used bits of the databus should be terminated through a resistor to either the digital
power plane (V

) or GND.

CC

to or reading from the device over the databus (D0–D9). Internally, data is latched on
the rising edge of CE.

–10–

REV. A

ADV7150

Mnemonic Function

R/

W Read/Write Control (TTL Compatible Input). This input determines whether data is

written to or read from the device’s registers and color palette RAM. R/
be at Logic “0” to write data to the part. R/

W must be at Logic “1” and CE at Logic

“0” to read from the device.

C0, C1 Command Controls (TTL Compatible Inputs). These inputs determine the type of read

or write operation being performed on the device over the databus (see Interface Truth
Table). Data on these inputs is latched on the falling edge of

IOR, IOG; IOG, IOB; Red, Green and Blue Current Outputs (High Impedance Current Sources). These RGB

IOR;

CE.

IOB video outputs are specified to directly drive RS-343A and RS-170 video levels into dou-

bly terminated 75 Ω loads.
IOR, IOG and IOB are the complementary outputs of IOR, IOG and IOB. These out-

puts can be tied to GND if it is not required to use differential outputs.

V

REF

Voltage Reference Input (Analog Input). An external 1.235 V voltage reference is re­quired to drive this input. An AD589 (2-terminal voltage reference) or equivalent is rec­ommended. (Note: It is not recommended to use a resistor network to generate the
voltage reference.)

R

SET

Output Full-Scale Adjust Control (Analog Input). A resistor connected between this pin
and analog ground controls the absolute amplitude of the output video signal. The value
of R

is derived from the full-scale output current on IOG according to the following

SET

equations:

R

(Ω) = C1 × V

SET

R

(Ω) = C2 × V

SET

/IOG (mA); SYNC on GREEN

REF

/IOG (mA); NO SYNC on GREEN.

REF

Full-Scale output currents on IOR and IOB for a particular value of R

IOR (mA)= C2 × V

REF

(V)/R

SET

(Ω)

and

IOB (mA) = C2 × V

REF

(V)/R

SET

(Ω)

where C1 = 6,050; PEDESTAL = 7.5 IRE

where C1 = 5,723; PEDESTAL = 0 IRE

and

where C2 = 4,323; PEDESTAL = 7.5 IRE

where C1 = 3,996; PEDESTAL = 0 IRE.

COMP Compensation Pin. A 0.1 µF capacitor should be connected between this pin and VAA.
I

PLL

Phase Lock Loop Output Current (High Impedance Current Source). This output is

used to enable multiple ADV7150s along with ADV7151s to be synchronized together

with pixel resolution when using an external PLL. This output is triggered either from

the falling edge of

SYNC or BLANK as determined by bit CR21 of Command Register

2. When activated, it supplies a current corresponding to:

I

(mA) = 1,728 × V

PLL

When not using the I
V

AA

Power Supply (+5 V ± 5%). The part contains multiple power supply pins, all should be

function, this output pin should be tied to GND.

PLL

REF

(V)/R

SET

(Ω)

connected together to one common +5 V filtered analog power supply.
GND Analog Ground. The part contains multiple ground pins, all should be connected

together to the system’s ground plane.

W and CE must

are given by:

SET

REV. A

–11–