Datasheet ADV7150 Datasheet (ANALOG DEVICES)

现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!

CMOS 220 MHz True-Color Graphics

FEATURES 220 MHz, 24-Bit (30-Bit Gamma Corrected) True Color Triple 10-Bit “Gamma Correcting” D/A Converters Triple 256 3 10 (256 3 30) Color Palette RAM On-Chip Clock Control Circuit Palette Priority Select Registers RS-343A/RS-170 Compatible Analog Outputs TTL Compatible Digital Inputs Standard MPU l/O Interface

10-Bit Parallel Structure

8+2 Byte Structure Programmable Pixel Port: 24-Bit, 15-Bit and

Programmable Pixel Port: 8-Bit (Pseudo)

Pixel Data Serializer

Multiplexed Pixel Input Ports; 1:1, 2:1, 4:1 +5 V CMOS Monolithic Construction 160-Lead Plastic Quad Flatpack (QFP) Thermally Enhanced to Achieve u

MODES OF OPERATION 24-Bit True Color (30-Bit Gamma Corrected)

@ 220 MHz

@ 170 MHz

@ 135 MHz

@ 110 MHz

< 1.08C/W

Triple 10-Bit Video RAM-DAC

ADV7150

@ 85 MHz

8-Bit Pseudo Color 15-Bit True Color

APPLICATIONS High Resolution, True Color Graphics Professional Color Prepress Imaging

GENERAL DESCRIPTION

The ADV7150 (ADV®) is a complete analog output, Video RAM-DAC on a single CMOS monolithic chip. The part is specifically designed for use in high performance, color graphics workstations. The ADV7150 integrates a number of graphic functions onto one device allowing 24-bit direct True-Color operation at the maximum screen update rate of 220 MHz. The ADV7150 implements 30-bit True Color in 24-bit frame buffer designs. The part also supports other modes, including 15-bit True Color and 8-bit Pseudo or Indexed Color. Either the Red, Green or Blue input pixel ports can be used for Pseudo Color.

(Continued on page 12)

ADV is a registered trademark of Analog Devices, Inc.

FUNCTIONAL BLOCK DIAGRAM

RED (R7–R0), GREEN (G7–G0), BLUE (B7–B0) COLOR DATA

PALETTE SELECTS

(PS0, PS1)

LOADIN

LOADOUT

PRGCKOUT

SCKOUT

SCKIN

SYNC

BLANK

CLOCK CLOCK

X E

P O

R T

CLOCK CONTROL

CLOCK DIVIDE

SYNCHRONIZATION

÷32 ÷16, ÷8, ÷4, ÷2

ECL TO CMOS

CIRCUIT

ADV7150

MUX

4:1

MUX

4:1

ADDRESS REGISTER

8 8 8

MODE

ADDR

(A7–A0)

CE R/W C0 C1

(MR1)

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

256-COLOR/GAMMA

PALETTE RAM

RED

256 x 10

GREEN

256 x 10

BLUE

256 x 10

CONTROL REGISTERS

PIXEL MASK

TEST

REGISTERS

MPU PORT

10 (8+2)

D9 – D0

COMMAND

REGISTERS

(CR1–CR3)

REVISION

DATA TO

PALETTES

10-BIT

RED DAC

10-BIT

GREEN DAC

10-BIT

BLUE DAC

RED

SYNC

OUTPUT

VOLTAGE

REFERENCE

CIRCUIT

COLOR REGISTERS

BLUE

GREEN

GND

IOR IOR

IOG IOG

IOB IOB

PLL

SYNCOUT V

REF

SET

COMP

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703

ADV7150–SPECIFICA TIONS

CL = 10 pF); IOR, IOG, IOB = GND. All specifications T

MIN

= +5 V; V

to T

unless otherwise noted.)

MAX

= +1.235 V; R

REF

= 280 V. IOR, IOG, IOB (RL = 37.5 V,

SET

Parameter All Versions Unit Test Conditions/Comments

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits Accuracy (Each DAC)

Integral Nonlinearity ±1 LSB max Differential Nonlinearity ±1 LSB max Guaranteed Monotonic Gray Scale Error ±5 % Gray Scale max

Coding Binary

DIGITAL INPUTS (Excluding CLOCK, CLOCK)

Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C

INL

INH

2 V min

0.8 V max ±10 µA max VIN = 0.4 V or 2.4 V 10 pF max

CLOCK INPUTS (CLOCK, CLOCK)

Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C

INL

INH

VAA – 1.0 V min VAA – 1.6 V max ±10 µA max VIN = 0.4 V or 2.4 V 10 pF typ

DIGITAL OUTPUT

Output High Voltage, V Output Low Voltage, V

2.4 V min I

0.4 V max I

SOURCE

= 3.2 mA

SINK

= 400 µA

Floating-State Leakage Current 20 µA max Floating-State Output Capacitance 20 pF typ

ANALOG OUTPUTS

Gray Scale Current Range 15/22 mA min/max Output Current

White Level Relative to Blank 17.69/20.40 mA min/max Typically 19.05 mA White Level Relative to Black 16.74/18.50 mA min/max Typically 17.62 mA Black Level Relative to Blank 0.95/1.90 mA min/max Typically 1.44 mA Blank Level on IOR, IOB 0/50 µA min/max Typically 5 µA Blank Level on IOG 6.29/8.96 mA min/max Typically 7.62 mA Sync Level on IOG 0/50 µA min/max Typically 5 µA

LSB Size 17.22 µA typ DAC-to-DAC Matching 3 % max Typically 1% Output Compliance, V Output Impedance, R

OUT

Output Capacitance, C

OUT

0/+1.4 V min/V max 100 kΩ typ 30 pF max I

OUT

= 0 mA

VOLTAGE REFERENCE

Voltage Reference Range, V Input Current, I

VREF

REF

1.14/1.26 V min/V max V +5 µA typ

= 1.235 V for Specified Performance

REF

POWER REQUIREMENTS

5 V nom 400 mA max 220 MHz Parts 370 mA max 170 MHz Parts 350 mA max 135 MHz Parts 330 mA max 110 MHz Parts 315 mA max 85 MHz Parts

Power Supply Rejection Ratio 0.5 %/% max Typically 0.12%/%: COMP = 0.1 µF

DYNAMIC PERFORMANCE

Clock and Data Feedthrough

Glitch Impulse 50 pV secs typ DAC-to-DAC Crosstalk

NOTES

±5% for all versions.

Temperature range (T

Pixel Port is continuously clocked with data corresponding to a linear ramp. TJ = 100°C.

Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.

TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured the 10% and 90% points. Timing reference points at 50% for inputs and outputs.

DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.

Specifications subject to change without notice.

MIN

to T

4, 5

): 0°C to +70°C; TJ (Silicon Junction Temperature) ≤ 100°C.

MAX

–30 dB typ

–23 dB typ

–2–

REV. A

TIMING CHARACTERISTICS

IOR, IOG, I0B = GND. All specifications T

CLOCK CONTROL AND PIXEL PORT

MIN

to T

= +5 V; V

unless otherwise noted.)

MAX

= +1.235 V; R

REF

= 280 V. IOR, IOG, IOB (RL = 37.5 V, CL = 10 pF);

SET

220 MHz 170 MHz 135 MHz 110 MHz 85 MHz

Parameter Version Version Version Version Version Units

ADV7150

Conditions/Comments

CLOCK

LOADIN

220 170 135 110 85 MHz max Pixel CLOCK Rate

4.55 5.88 7.4 9.1 11.77 ns min Pixel CLOCK Cycle Time 2 2.5 3.2 4 4 ns min Pixel CLOCK High Time 2 2.5 3 4 4 ns min Pixel CLOCK Low Time 10 10 10 10 10 ns max Pixel CLOCK to LOADOUT Delay

LOADIN Clocking Rate 1:1 Multiplexing 110 110 110 110 85 MHz max 2:1 Multiplexing 110 85 67.5 55 42.5 MHz max 4:1 Multiplexing 55 42.5 33.75 27.5 21.25 MHz max

LOADIN Cycle Time 1:1 Multiplexing 9.1 9.1 9.1 9.1 9.1 ns min 2:1 Multiplexing 9.1 11.76 14.8 18.18 23.53 ns min 4:1 Multiplexing 18.18 23.53 29.63 36.36 47.1 ns min

LOADIN High Time 1:1 Multiplexing 44444ns min 2:1 Multiplexing 45689ns min 4:1 Multiplexing 8 9 12 15 18 ns min

LOADIN Low Time 1:1 Multiplexing 44444ns min 2:1 Multiplexing 45689ns min 4:1 Multiplexing 8 9 12 15 18 ns min

τ–t

11 6

1:1 Multiplexing 55555CLOCKs (1 × CLOCK = t

00000ns minPixel Data Setup Time 55555ns minPixel Data Hold Time 00000ns minLOADOUT to LOADIN Delay τ–5 τ–5 τ–5 τ–5 τ–5 ns max LOADOUT to LOADIN Delay

Pipeline Delay

)

2:1 Multiplexing 66666CLOCKs 4:1 Multiplexing 88888CLOCKs

ANALOG OUTPUTS

10 10 10 10 10 ns max Pixel CLOCK to PRGCKOUT Delay 55555ns maxSCKIN to SCKOUT Delay 55555ns minBLANK to SCKIN Setup Time 11111ns minBLANK to SCKIN Hold Time

220 MHz 170 MHz 135 MHz 110 MHz 85 MHz

Parameter Version Version Version Version Version Units Conditions/Comments

15 15 15 15 15 ns typ Analog Output Delay 11111ns typAnalog Output Rise/Fall Time 15 15 15 15 15 ns typ Analog Output Transition Time 22222ns maxAnalog Output Skew (IOR, IOG, IOB) 00000ns typ

MPU PORTS

8, 9

220 MHz 170 MHz 135 MHz 110 MHz 85 MHz

Parameter Version Version Version Version Version Units Conditions/Comments

33333ns minR/W, C0, C1 to CE Setup Time 10 10 10 10 10 ns min R/W, C0, C1 to CE Hold Time 45 45 45 45 45 ns min CE Low Time 25 25 25 25 25 ns min CE High Time 55555ns minCE Asserted to Databus Driven 45 45 45 45 45 ns max CE Asserted to Data Valid 20 20 20 20 20 ns max CE Disabled to Databus Three-Stated 55555ns min

REV. A

20 20 20 20 20 ns min Write Data (D0–D9) Setup Time 55555ns minWrite Data (D0–D9) Hold Time

–3–

ADV7150

NOTES

TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. ECL inputs (CLOCK, CLOCK) are

VAA–0.8 V to VAA–1.8 V, with input rise/fall times ≤ 2 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ≤ 10 pF. Databus (D0–D9) loaded as shown in Figure 1. Digital output load for LOADOUT, PRGCKOUT, SCKOUT, I SYNCOUT ≤ 30 pF.

±5% for all versions.

Temperature range (T

Pixel Port consists of the following inputs: Pixel Inputs: RED [A, B, C, D]; GREEN [A, B, C, D]; BLUE [A, B, C, D], Palette Selects: PS0 [A, B, C, D]; PS1

[A, B, C, D]; Pixel Controls: SYNC, BLANK; Clock Inputs: CLOCK, CLOCK, LOADIN, SCKIN; Clock Outputs: LOADOUT, PRGCKOUT, SCKOUT.

τ is the LOADOUT Cycle Time and is a function of the Pixel CLOCK Rate and the Multiplexing Mode: 1:1 multiplexing; τ = CLOCK = t1 ns. 2:1 Multi-

plexing; τ = CLOCK × 2 = 2 × t1 ns. 4:1 Multiplexing; τ = CLOCK × 4 = 4 × t1 ns.

These fixed values for Pipeline Delay are valid under conditions where t10 and τ-t11 are met. If either t10 or τ-t11 are not met, the part will operate but the Pipe line De-

lay is increased by 2 additional CLOCK cycles for 2:1 Mode and is increased by 4 additional CLOCK cycles for 4:1 Mode, after calibration is performed.

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Output rise/fall time measured between the 10%

MIN

to T

): 0°C to +70°C; TJ (Silicon Junction Temperature) ≤ 100°C.

MAX

and 90% points of full-scale transition. Transition time measured from the 50% point of full-scale transition to the output remaining within 2% of the final output value (Transition time does not include clock and data feedthrough).

t23 and t24 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V.

t25 is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-

lated back to remove the effects of charging the 100 pF capacitor. This means that the time, t25, quoted in the Timing Characteristics is the true value for the device and as such is independent of external databus loading capacitances.

Specifications subject to change without notice.

SINK

TO OUTPUT PIN

100pF

+2.1V

PLL

and

CLOCK

LOADOUT

(1:1 MULTIPLEXING)

LOADOUT

(2:1 MULTIPLEXING)

LOADOUT

(4:1 MULTIPLEXING)

LOADIN

PIXEL INPUT

DATA*

SOURCE

Figure 1. Load Circuit for Databus Access and Relinquish Times

VALID

DATA

CLOCK

VALID

DATA

Figure 2. LOADOUT vs. Pixel Clock Input (CLOCK,

t8t

VALID

DATA

)

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC

Figure 3. LOADIN vs. Pixel Input Data

–4–

REV. A

CLOCK

LOADOUT

LOADIN

ADV7150

PIXEL INPUT

DATA*

ANALOG

OUTPUT

DATA

DIGITAL INPUT TO ANALOG

OUTPUT PIPELINE

IOR, IOR IOG, IOG IOB, IOB I

PLL, SYNCOUT

N+1 BN+1

N+1DN+1

N–1

N–1CN–1DN–1

N+2 BN+2

N+2 DN+2

ANBNCNDNA

N+1BN+1CN+1DN+1

N+2BN+2CN+2DN+2

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC

Figure 4. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (4:1 Multiplex Mode)

CLOCK

τ– t

LOADOUT

LOADIN

PIXEL INPUT

DATA*

ANALOG

OUTPUT

DATA

N–1CN–1DN–1

N+1 BN+1

N+1DN+1

ANBNCND

IOR, IOR IOG, IOG IOB, IOB I

PLL, SYNCOUT

DIGITAL INPUT

TO ANALOG

OUTPUT

PIPELINE

N–1

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC

N+2 BN+2

N+2 DN+2

N+1BN+1CN+1DN+1

N+2BN+2CN+2DN+2

Figure 5. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (4:1 Multiplex Mode)

REV. A

–5–

ADV7150

LOADOUT

LOADIN

CLOCK

PIXEL INPUT

DATA*

ANALOG

OUTPUT

DATA

DIGITAL INPUT TO ANALOG

OUTPUT PIPELINE

IOR, IOR IOG, IOG IOB, IOB I

PLL, SYNCOUT

N+1 BN+1

N+2 BN+2

N-1BN-1

N+1BN+1AN+2BN+2

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC

Figure 6. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (2:1 Multiplex Mode)

CLOCK

τ– t

LOADOUT

LOADIN

PIXEL INPUT

DATA*

DIGITAL INPUT TO ANALOG

OUTPUT PIPELINE

N+1 BN+1

N+2 BN+2

ANALOG

OUTPUT

DATA

IOR, IOR IOG, IOG IOB, IOB I

PLL, SYNCOUT

N-1BN-1

N+1BN+1AN+2

N+2

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC

Figure 7. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (2:1 Multiplex Mode)

–6–

REV. A

CLOCK

PRGCKOUT

(CLOCK/4)

PRGCKOUT

(CLOCK/8)

PRGCKOUT

(CLOCK/16)

PRGCKOUT

(CLOCK/32)

SCKIN

BLANK

ADV7150

Figure 8. Pixel Clock Input vs. Programmable Clock Output (PRGCKOUT)

BLANKING

PERIOD

SCKOUT

END OF SCAN LINE (N)

START OF SCAN LINE (N+1)

Figure 9. Video Data Shift Clock Input (SCKIN) & BLANK vs. Video Data Shift Clock Output (SCKOUT)

CLOCK

WHITE LEVEL

90 %

50 %

10 % BLACK LEVEL

NOTE: THIS DIAGRAM IS NOT TO SCALE. FOR THE PURPOSES OF CLARITY, THE ANALOG OUTPUT WAVEFORM IS MAGNIFIED IN TIME AND AMPLITUDE W.R.T THE CLOCK WAVEFORM. I

AND SYNCOUT ARE DIGITAL VIDEO OUTPUT SIGNALS.

PLL

IS THE ONLY RELEVENT OUTPUT TIMING SPECIFICATION

FOR I

AND SYNCOUT.

PLL

FULL-SCALE TRANSITION

ANALOG

OUTPUTS

IOR, IOR IOG, IOG IOB, IOB I

PLL, SYNCOUT

REV. A

Figure 10. Analog Output Response vs. CLOCK

–7–

ADV7150

R/W, C0, C1

(READ MODE)

D0–D9

CONTROL DATA

VALID

R/W = 1

D0–D9

(WRITE MODE)

R/W = 0

Figure 11. Microprocessor Port (MPU) Interface Timing

RECOMMENDED OPERATING CONDITION

Parameter Symbol Min Typ Max Units

Power Supply V Ambient Operating Temperature T Reference Voltage V Output Load R

AA A REF L

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7150 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS

VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Voltage on Any Digital Pin . . . . GND – 0.5 V to V

Ambient Operating Temperature (T Storage Temperature (T Junction Temperature (T

) . . . . . . . . . . . . . . –65°C to +150°C

) . . . . . . . . . . . . . . . . . . . . +150°C

) . . . . . –55°C to +125°C

+ 0.5 V

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +260°C

Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . +220°C

Analog Outputs to GND

NOTES

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration.

. . . . . . . . . . . . . GND – 0.5 to V

4.75 5.00 5.25 Volts 0 +70 °C

1.14 1.235 1.26 Volts

37.5 Ω

WARNING!

ESD SENSITIVE DEVICE

16-Lead QFP Configuration

160 121

PIN NO. 1 IDENTIFIER

ROW A

ROW D

ADV7150 QFP

TOP VIEW

(NOT TO SCALE)

ROW C

120

ORDERING GUIDE

1, 2, 3

Speed

220 MHz ADV7150LS220 110 MHz ADV7150LS110 170 MHz ADV7150LS170 85 MHz ADV7150LS85 135 MHz ADV7150LS135

NOTES

ADV7150 is packaged in a 160-pin plastic quad flatpack, QFP.

All devices are specified for 0°C to +70°C operation.

Contact sales office for latest information on package design.

–8–

41 80

ROW B

REV. A

ADV7150

ADV7150 PIN ASSIGNMENTS

Pin Pin Pin Pin Number Mnemonic Number Mnemonic Number Mnemonic Number Mnemonic

1G3 2G3 3G3 4G3 5G4 6G4 7G4 8G4 9G5 10 G5 11 G5 12 G5

A B C D A B C D A B C D

41 PS1 42 B0 43 B0 44 B0 45 B0 46 B1 47 B1 48 B1 49 B1 50 B2 5 1 B2

52 B2 13 CLOCK 53 B2 14 CLOCK 54 B3 15 LOADIN 55 B3 16 LOADOUT 56 B3 17 V 18 V

AA AA

57 B3

58 B4 19 PRGCKOUT 59 B4 20 SCKIN 60 B4 21 SCKOUT 61 B4 22 SYNCOUT 62 B5 23 GND 63 B5 24 GND 64 B5 25 GND 65 B5 26 G6 27 G6 28 G6 29 G6 30 G7 31 G7 32 G7 33 G7 34 PS0 35 PS0 36 PS0 37 PS0 38 PS1 39 PS1 40 PS1

NC = No Connect.

A B C D A B C D

A B C D A B C

66 B6

67 B6

68 B6

69 B6

70 B7

71 B7

72 B7

73 B7

74 CE 114 V

75 R/W 115 SYNC 155 G1

76 C0 116 BLANK 1 56 G1

77 C1 117 R0

78 D0 118 R0

79 D1 119 R0

80 GND 120 R0

D A B C

81 NC 121 R1 82 D2 122 R1 83 NC 123 R1 84 GND 124 R1 85 GND 125 R2 86 GND 126 R2 87 D3 127 R2 88 D4 128 R2 89 D5 129 R3 90 V

130 R3 91 D6 131 R3 92 D7 132 R3 93 D8 133 R4 94 D9 134 R4 95 GND 135 R4 96 GND 136 R4 97 GND 137 R5 98 IOB 138 R5 99 IOR 139 R5 100 IOG 140 R5 101 IOB 141 R6 102 IOG 142 R6 103 V 104 V 105 V

AA AA AA

143 R6

144 R6

145 R7 106 IOR 146 R7 107 COMP 147 R7 108 V 109 R 110 I

REF SET

PLL

148 R7

149 G0

150 G0 111 GND 151 G0 112 V 113 V

AA AA AA

A B C D

152 G0

153 G1

154 G1

157 G2

158 G2

159 G2

160 G2

A B C D A B C D A B C D A B C D A B C D A B C D A B C D

A B C D A B C D A B C D

REV. A

–9–

ADV7150

PIN FUNCTION DESCRIPTION

Mnemonic Function

RED (R0A . . . R0D–R7A . . . R7D), Pixel Port (TTL Compatible Inputs): 96 pixel select inputs, with 8 bits each for Red, 8 GREEN (G0 BLUE (B0

PS0

. . . PS0D, PS1A . . . PS1

LOADIN Pixel Data Load Input (TTL Compatible Input). This input latches the multiplexed

LOADOUT Pixel Data Load Output (TTL Compatible Output). This output control signal runs at

PRGCKOUT Programmable Clock Output (TTL Compatible Output). This output control signal

SCKIN Video Shift Clock Input (TTL Compatible Input). The signal on this input is internally

SCKOUT Video Shift Clock Output (TTL Compatible Output). This output is a synchronously

CLOCK,

BLANK Composite Blank (TTL Compatible Input). This video control signal drives the analog

SYNC Composite-Sync Input (TTL Compatible Input). This video control signal drives the

SYNCOUT Composite-Sync Output (TTL Compatible Output). This video output is a delayed

D0–D9 Databus (TTL Compatible Input/Output Bus). Data, including color palette values and

CE Chip Enable (TTL Compatible Input). This input must be at Logic “0,” when writing

. . . G0D–G7A. . . G7D), bits for Green and 8 bits for Blue. Each bit is multiplexed [A-D] 4:1, 2:1 or 1:1. It can

. . . B0D–B7A . . . B7D) be configured for 24-Bit True-Color Data, 8-Bit Pseudo-Color Data and 15-Bit True-Color

Data formats. Pixel Data is latched into the device on the rising edge of LOADIN.

Palette Priority Selects (TTL Compatible Inputs): These pixel port select inputs determine whether or not the device’s pixel data port is selected on a pixel by pixel basis. The palette selects allow switching between multiple palette devices. The device can be preprogrammed to completely shut off the DAC analog outputs. If the values of PS0 and PS1 match the values programmed into bits MR16 and MR17 of the Mode Register, then the device is selected. Each bit is multiplexed [A-D] 4:1, 2:1 or 1:1. PS0 and PS1 are latched into the device on the rising edge of LOADIN.

pixel data, including PS0–PS1,

BLANK and SYNC into the device.

a divided down frequency of the pixel CLOCK input. Its frequency is a function of the multiplex rate. It can be used to directly or indirectly drive LOADIN

LOADOUT

= f

CLOCK

where M = 1 for 1:1 Multiplex Mode

where M = 2 for 2:1 Multiplex Mode where M = 4 for 4:1 Multiplex Mode.

runs at a divided down frequency of the pixel CLOCK input. Its frequency is user programmable and is determined by bits CR30 and CR31 of Command Register 3

PRGCKOUT

= f

CLOCK

where N = 4, 8, 16 and 32.

gated synchronously with the

BLANK signal. The resultant output, SCKOUT, is a

video clocking signal that is stopped during video blanking periods.

gated version of SCKIN and

BLANK. SCKOUT, is a video clocking signal that is

stopped during video blanking periods.

CLOCK Clock Inputs (ECL Compatible Inputs). These differential clock inputs are designed to

be driven by ECL logic levels configured for single supply (+5 V) operation. The clock rate is normally the pixel clock rate of the system.

outputs to the blanking level.

IOG analog output to the CR22 in Command Re output, otherwise the

version of

SYNC. The delay corresponds to the number of pipeline stages of the device.

SYNC level. It is only asserted during the blanking period.

gister 2 must be set if SYNC is to be decoded onto the analog

SYNC input is ignored.

device control information is written to and read from the device over this 10-bit, bidirectional databus. 10-bit data or 8-bit data can be used. The databus can be configured for either 10-bit parallel data or byte data (8+2) as well as standard 8-bit data. Any unused bits of the databus should be terminated through a resistor to either the digital power plane (V

) or GND.

to or reading from the device over the databus (D0–D9). Internally, data is latched on the rising edge of CE.

–10–

REV. A

ADV7150

Mnemonic Function

W Read/Write Control (TTL Compatible Input). This input determines whether data is

written to or read from the device’s registers and color palette RAM. R/ be at Logic “0” to write data to the part. R/

W must be at Logic “1” and CE at Logic

“0” to read from the device.

C0, C1 Command Controls (TTL Compatible Inputs). These inputs determine the type of read

or write operation being performed on the device over the databus (see Interface Truth Table). Data on these inputs is latched on the falling edge of

IOR, IOG; IOG, IOB; Red, Green and Blue Current Outputs (High Impedance Current Sources). These RGB

IOR;

CE.

IOB video outputs are specified to directly drive RS-343A and RS-170 video levels into dou-

bly terminated 75 Ω loads. IOR, IOG and IOB are the complementary outputs of IOR, IOG and IOB. These out-

puts can be tied to GND if it is not required to use differential outputs.

REF

Voltage Reference Input (Analog Input). An external 1.235 V voltage reference is required to drive this input. An AD589 (2-terminal voltage reference) or equivalent is recommended. (Note: It is not recommended to use a resistor network to generate the voltage reference.)

SET

Output Full-Scale Adjust Control (Analog Input). A resistor connected between this pin and analog ground controls the absolute amplitude of the output video signal. The value of R

is derived from the full-scale output current on IOG according to the following

SET

equations:

(Ω) = C1 × V

SET

(Ω) = C2 × V

SET

/IOG (mA); SYNC on GREEN

REF

/IOG (mA); NO SYNC on GREEN.

REF

Full-Scale output currents on IOR and IOB for a particular value of R

IOR (mA)= C2 × V

REF

(V)/R

SET

(Ω)

and

IOB (mA) = C2 × V

REF

(V)/R

SET

(Ω)

where C1 = 6,050; PEDESTAL = 7.5 IRE

where C1 = 5,723; PEDESTAL = 0 IRE

and

where C2 = 4,323; PEDESTAL = 7.5 IRE

where C1 = 3,996; PEDESTAL = 0 IRE.

COMP Compensation Pin. A 0.1 µF capacitor should be connected between this pin and VAA. I

PLL

Phase Lock Loop Output Current (High Impedance Current Source). This output is

used to enable multiple ADV7150s along with ADV7151s to be synchronized together

with pixel resolution when using an external PLL. This output is triggered either from

the falling edge of

SYNC or BLANK as determined by bit CR21 of Command Register

2. When activated, it supplies a current corresponding to:

(mA) = 1,728 × V

PLL

When not using the I V

Power Supply (+5 V ± 5%). The part contains multiple power supply pins, all should be

function, this output pin should be tied to GND.

PLL

REF

(V)/R

SET

(Ω)

connected together to one common +5 V filtered analog power supply. GND Analog Ground. The part contains multiple ground pins, all should be connected

together to the system’s ground plane.

W and CE must

are given by:

SET

REV. A

–11–

ADV7150

MULTIPLEXER

RED GREEN BLUE

(Continued from page 1)

The device consists of three, high speed, 10-bit, video D/A converters (RGB), three 256 × 10 (one 256 × 30) color look-up tables, palette priority selects, a pixel input data multiplexer/ serializer and a clock generator/divider circuit. The ADV7150 is capable of 1:1, 2:1 and 4:1 multiplexing. The onboard palette priority select inputs enable multiple palette devices to be connected together for use in multipalette and window applications. The part is controlled and programmed through the microprocessor (MPU) port. The part also contains a number of onboard test registers, associated with self diagnostic testing of the device. The individual Red, Green and Blue pixel input ports allow True-Color, image rendition. True-Color image rendition, at speeds of up to 220 MHz, is achieved through the use of the onboard data multiplexer/serializer. The pixel input port’s flexibility allows for direct interface to most standard frame buffer memory configurations.

The 30 bits of resolution, associated with the color look-up table and triple 10-bit DAC, realizes 24-bit True-Color resolution, while also allowing for the onboard implementation of linearization algorithms, such as Gamma-Correction. This allows effective 30-Bit True-Color operation.

CIRCUIT DETAILS AND OPERATION

OVERVIEW

Digital video or pixel data is latched into the ADV7150 over the devices Pixel Port. This data acts as a pointer to the onboard Color Palette RAM. The data at the RAM address pointed to is latched into the digital-to-analog converters (DACs) and output as an RGB analog video signal.

For the purposes of clarity of description, the ADV7150 is broken down into three separate functional blocks. These are:

1. Pixel port and clock control circuit

2. MPU port, registers and color palette

3. Digital-to-analog converters and video outputs Table I shows the architectural and packaging differences be-

tween other devices in the ADV715x series of workstation parts. (For more details consult the relevant data sheets.)

Table I. Architectural and Packaging Differences of the ADV715x Series

Description ADV7150 ADV7152* ADV7151*

24-Bit “Gamma” True Color • • 24-Bit “Standard” True Color • • 8-Bit “Gamma” Pseudo Color • • • 8-Bit “Standard” Pseudo Color • • • 15-Bit True Color • • 220 MHz – True Color • • 220 MHz – Pseudo Color • • • Triple 10-Bit DACs • • • 4:1 Multiplexing • • 2:1 Multiplexing • • • 1:1 Multiplexing • • • 160-Lead QFP • 100-Lead QFP • •

*See ADV7151 and ADV7150 data sheets for more information on these parts.

The on-chip video clock controller circuit generates all the internal clocking and some additional external clocking signals. An external ECL oscillator source with differential outputs is all that is required to drive the CLOCK and

CLOCK inputs of the ADV7150. The part can also be driven by an external clock generator chip circuit, such as the AD730.

The ADV7150 is capable of generating RGB video output signals which are compatible with RS-343A and RS-170 video standards, without requiring external buffering.

Test diagnostic circuitry has been included to complement the users system level debugging.

The ADV7150 is fabricated in a +5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with low power dissipation.

The ADV7150 is packaged in a plastic 160-pin power quad flatpack (QFP). Superior thermal dissipation is achieved by inclusion of a copper heatslug, within the standard package outline to which the die is attached.

Pixel Port and Clock Control Circuit

The Pixel Port of the ADV7150 is directly interfaced to the video/graphics pipeline of a computer graphics subsystem. It is connected directly or through a gate array to the video RAM of the systems Frame-Buffer (video memory). The pixel port on the device consists of:

Color Data RED, GREEN, BLUE Pixel Controls

SYNC, BLANK

Palette Selects PS0–PS1 The associated clocking signals for the pixel port include: Clock Inputs CLOCK, CLOCK,

LOADIN, SCKIN

Clock Outputs LOADOUT, PRGCKOUT,

SCKOUT

These onboard clock control signals are included to simplify interfacing between the part and the frame buffer. Only two control input signals are necessary to get the part operational, CLOCK and

CLOCK (ECL Levels). No additional signals or external glue logic are required to get the Pixel Port & Clock Control Circuit of the part operational.

Pixel Port (Color Data)

The ADV7150 has 96 color data inputs. The part has four (for 4:1 multiplexing) 24-bit wide direct color data inputs. These are user programmed to support a number of color data formats including 24-Bit True Color, 15-Bit True Color and 8-Bit Pseudo Color (see “Color Data Formats” section) in 4:1, 2:1 and 1:1 multiplex modes.

Figure 12. Multiplexed Color Inputs for the ADV7150

–12–

REV. A

ADV7150

CLOCK

ADV7150

CLOCK

DIVIDE BY

N (÷ N)

LOADOUT

DIVIDE BY

M (÷ M)

PRGCKOUT

LOADIN

SCKOUT

SCKIN

BLANK

LATCH

ENABLE

SYNC

TO COLOR DATA

MULTIPLEXER

ECL

TTL

M IS A FUNCTION OF MULTIPLEX RATE M = 4 IN 4:1 MULTIPLEX MODE M = 2 IN 2:1 MULTIPLEX MODE M = 1 IN 1:1 MULTIPLEX MODE

N IS INDEPENDENTLY PROGRAMMABLE N= (4, 8, 16, 32)

Color data is latched into the parts pixel port on every rising edge of LOADIN (see Timing Waveform, Figure 3). The required frequency of LOADIN is determined by the multiplex rate, where:

LOADIN

= f = f = f

/4 4:1 Multiplex Mode

CLOCK

/2 2:1 Multiplex Mode

CLOCK

1:1 Multiplex Mode

Other pixel data signals latched into the device by LOADIN include

SYNC, BLANK and PS0–PS1.

Internally, data is pipelined through the part by the differential pixel clock inputs, CLOCK and

CLOCK. The LOADIN control signal needs only have a frequency synchronous relationship to the pixel CLOCK (see “Pipeline Delay & Onboard Calibration” section). A completely phase independent LOADIN signal can be used with the ADV7150, allowing the CLOCK to occur anywhere during the LOADIN cycle.

Alternatively, the LOADOUT signal of the ADV7150 can be used. LOADOUT can be connected either directly or indirectly to LOADIN. Its frequency is automatically set to the correct LOADIN requirement.

SYNC, BLANK

The BLANK and SYNC video control signals drive the analog outputs to the blanking and

SYNC levels respectively. These signals are latched into the part on the rising edge of LOADIN. The

SYNC information is encoded onto the IOG analog signal when Bit CR22 of Command Register 2 is set to a Logic “1.” The

SYNC input is ignored if CR22 is set to “0.”

SYNCOUT

In some applications where it is not permissible to encode SYNC on green (IOG), SYNCOUT can be used as a separate TTL digital pendent (of the ADV7150)

SYNC output. This has the advantage over an inde-

SYNC in that it does not necessitate

knowing the absolute pipeline delay of the part. This allows complete independence between LOADIN/Pixel Data and CLOCK. The

SYNC input is connected to the device as normal with Bit CR22 of Command Register 2 set to “0” thereby preventing Command Register 1 is set to “1,” enabling output signal generates a TTL delay that is capable of directly driving the composite

SYNC from being encoded onto IOG. Bit CR12 of

SYNCOUT. The

SYNCOUT with correct pipeline

SYNC

signal of a computer monitor.

PS0–PS1 (Palette Priority Select Inputs)

These pixel port select inputs determine whether or not the device is selected. These controls effectively determine whether the devices RGB analog outputs are turned-on or shut down. When the analog outputs are shut down, IOR, IOG and IOB are forced to 0 mA regardless of the state of the pixel and control data inputs. This state is determined on a pixel by pixel basis as the PS0–PS1 inputs are multiplexed in exactly the same format as the pixel port color data. These controls allow for switching between multiple palette devices (see Appendix 4). If the values of PS0 and PS1 match the values programmed into bits MR16 and MR17 of the Mode Register, then the device is selected, if there is no match the device is effectively shut down.

Multiplexing

The onboard multiplexers of the ADV7150 eliminate the need for external data serializer circuits. Multiple video memory devices can be connected, in parallel, directly to the device.

VIDEO MEMORY/ FRAME BUFFER

VRAM (BANK A)

VRAM (BANK B)

VRAM (BANK C)

VRAM (BANK D)

33MHz

ADV7150

MULTIPLEXER

132 MHz

(4 x 33 MHz)

Figure 13. Direct Interfacing of Video Memory to ADV7150

Figure 13 shows four memory banks of 33 MHz memory connected to the ADV7150, running in 4:1 multiplex mode, giving a resultant pixel or dot clock rate of 132 MHz. As mentioned in the previous section, the ADV7150 supports a number of color data formats in 4:1, 2:1 and 1:1 multiplex modes.

In 1:1 multiplex mode, the ADV7150 is clocked using the LOADIN signal. This means that there is no requirement for differential ECL inputs on CLOCK and

CLOCK. The pixel clock is connected directly to LOADIN. (Note: The ECL CLOCK can still be used to generate LOADOUT PRGCKOUT, etc.)

CLOCK CONTROL CIRCUIT

The ADV7150 has an integrated Clock Control Circuit (Figure

14). This circuit is capable of both generating the ADV7150’s internal clocking signals as well as external graphics subsystem clocking signals. Total system synchronization can be attained by using the parts output clocking signals to drive the controlling graphics processor’s master clock as well as the video frame buffers shift clock signals.

Figure 14. Clock Control Circuit of the ADV7150

REV. A

–13–

ADV7150

LOADOUT

LOADIN

ADV7150

VIDEO

FRAME

BUFFER

LOADOUT

LOADIN

ADV7150

VIDEO

FRAME

BUFFER

LOADOUT(1)

LOADOUT(2)

PIXEL DATA

PIXEL

DATA

LOADIN

LOADOUT LOADOUT(1)

LOADOUT(2)

DELAY

SCKOUT

SCKIN

BLANK

LATCH

ENABLE

SYNC

LOADOUT

SCKOUT

ADV7150

VIDEO

FRAME

BUFFER

PIXEL DATA

LOADIN SCKIN

BLANK

CLOCK, CLOCK Inputs

The Clock Control Circuit is driven by the pixel clock inputs, CLOCK and ential ECL oscillator running from a +5 V supply.

Alternatively, the ADV7150 CLOCK inputs can be driven by a Programmable Clock Generator (Figure 15), such as the ICS1562. The ICS1562 is a monolithic, phase-locked-loop, clock generator chip. It is capable of synthesizing differential ECL output frequencies in a range up to 220 MHz from a single low frequency reference crystal.

LOW FREQUENCY

OSCILLATOR

CLOCK

Figure 15. PLL Generator Driving CLOCK, ADV7150

CLOCK CONTROL SIGNALS LOADOUT

The ADV7150 generates a LOADOUT control signal which runs at a divided down frequency of the pixel CLOCK. The frequency is automatically set to the programmed multiplex rate, controlled by CR37 and CR36 of Command Register 3.

LOADOUT

The LOADOUT signal is used to directly drive the LOADIN pixel latch signal of the ADV7150. This is most simply achieved by tying the LOADOUT and LOADIN pins together. Alternatively, the LOADOUT signal can be used to drive the frame buffer’s shift clock signals, returning to the LOADIN input delayed with respect to LOADOUT.

If it is not necessary to have a known fixed number of pipeline delays, then there is no limitation on the delay between LOADOUT and LOADIN (LOADOUT(1) and LOADOUT(2)).

LOADIN and Pixel Data must conform to the setup and hold times (t

If, however, it is required that the ADV7150 has a fixed number of pipeline delays (t form to timing specifications t ures 4 to 7.

CLOCK. These inputs can be driven by a differ-

GND

+5V

ECL ECL

CLOCK

GENERATOR

REF

D0-D3CSR/W

= f

CLOCK

= f

CLOCK

= f

CLOCK

and t9).

OUT+ OUT–

OUT V

/4 4:1 Multiplex Mode /2 2:1 Multiplex Mode

), LOADOUT and LOADIN must con-

GND

1:1 Multiplex Mode

220Ω

330Ω

GND

220Ω

330Ω

0.1 µF

CLOCK

and τ-t11 as illustrated in Fig-

+5V

CLOCK CLOCK

ADV7150

REF

GND

of the

Figure 16. LOADOUT vs. Pixel Clock Input (CLOCK,

CLOCK

PRGCKOUT

The PRGCKOUT control signal outputs a user programmable clock frequency. It is a divided down frequency of the pixel CLOCK (see Figure 8). The rising edge of PRGCKOUT is synchronous to the rising edge of LOADOUT

PRGCKOUT

= f

CLOCK

where N = 4, 8, 16 or 32. One application of the PRGCKOUT is to use it as the master

clock frequency of the graphics subsystems processor or controller.

SCKIN, SCKOUT

These video memory signals are used to minimize external support chips. Figure 17 illustrates the function that is provided. An input signal applied to SCKIN is synchronously AND-ed with the video blanking signal (

BLANK). The resulting signal is output on SCKOUT. Figure 9 of the Timing Waveform section shows the relationship between SCKOUT, SCKIN and

BLANK.

Figure 17. SCKOUT Generation Circuit

The SCKOUT signal is essentially the video memory shift control signal. It is stopped during the screen retrace. Figure 18 shows a suggested frame buffer to ADV7150 interface. This is a minimum chip solution and allows the ADV7150 control the overall graphics system clocking and synchronization.

Figure 18. ADV7150 Interface Using SCKIN and SCKOUT

–14–

REV. A

)

8-BIT

RED DAC

8-BIT

BLUE DAC

RED

256 x 8

GREEN

256 x 8

BLUE

256 x 8

8-BIT

GREEN DAC

RED OUT

GREEN OUT

BLUE OUT

24-BIT

COLOR DATA

24-BIT TO 24-BIT

LOOK-UP TABLE

24-BIT

COLOR DATA

ANALOG VIDEO

OUTPUTS

10-BIT

RED DAC

10-BIT

BLUE DAC

RED

256 x 10

GREEN

256 x 10

BLUE

256 x 10

10-BIT

GREEN DAC

RED OUT

GREEN OUT

BLUE OUT

8-BIT PIXEL

DATA

8-BIT TO 30-BIT

LOOK-UP TABLE

30-BIT

COLOR DATA

ANALOG VIDEO

OUTPUTS

8-BIT

RED DAC

8-BIT

BLUE DAC

RED

256 x 8

GREEN

256 x 8

BLUE

256 x 8

8-BIT

GREEN DAC

RED OUT

GREEN OUT

BLUE OUT

8-BIT PIXEL

DATA

8-BIT TO 24-BIT

LOOK-UP TABLE

24-BIT

COLOR DATA

ANALOG VIDEO

OUTPUTS

Pipeline Delay and Onboard Calibration

The ADV7150 has a fixed number of pipeline delays (tPD), so long as timings t delay is not a requirement, timings t

and τ-t11 are met. However, if a fixed pipeline

and τ-t11 can be ignored,

a calibration cycle must be run and there is no restriction on LOADIN to LOADOUT timing. If timings t

and τ-t11 are not

met, the part will function correctly though with an increased number of pipeline delays, t

+ N CLOCKS (for 4:1 mode

N = 4, for 2:1 mode N = 2, for 1:1 mode N = 0). The ADV7150 has onboard calibration circuitry which synchronizes pixel data and LOADIN with the internal ADV7150 clocking signals. Calibration can be performed in two ways: during the devices initialization sequence by toggling two bits of the Mode Register, MR10 followed by MR15, or by writing a “1” to Bit CR10 of Command Register 1 which executes a calibration on every Vertical Sync.

COLOR VIDEO MODES

The ADV7150 supports a number of color video modes all at the maximum video rate.

Command bits CR24–CR27 of Command Register 2 along with Bit MR11 of Mode Register 1 determine the color mode.

24-Bit “Gamma” True Color (CR25, CR26, CR27 = 1, 1, 1 and MR11 = 1)

The part is set to 24-bit/30-bit True-Color operation. The pixel port accepts 24 bits of color data which is directly mapped to the Look-Up Table RAM. The Look-Up Table is configured as a 256 location by 30 bits deep RAM (10 bits each for Red, Green and Blue). The output of the RAM drives the DACs with 30-bit data (10 bits each for Red, Green and Blue). The RAM is preloaded with a user determined, nonlinear function, such as a gamma correction curve.

10-BIT

RED DAC

10-BIT

GREEN DAC

10-BIT

BLUE DAC

ANALOG VIDEO

OUTPUTS

RED OUT

GREEN OUT

BLUE OUT

24-BIT

COLOR DATA

8 8 8

24-BIT TO 30-BIT LOOK-UP TABLE

RED

256 x 10

GREEN

256 x 10

BLUE

256 x 10

30-BIT

COLOR DATA

Figure 19. 24-Bit to 30-Bit True-Color Configuration

This mode allows for the display of full 24-bit, GammaCorrected True-Color Images.

24-Bit “Standard” True Color (CR25, CR26, CR27 = 1, 1, 1 and MR11 = 0)

This mode sets the part into direct 24-bit True-Color operation. The pixel port accepts 24 bits of color data which is directly mapped to Look-Up Table RAM. The Look-Up Table is configured as a 256 location by 24 bits deep RAM (8 bits each for Red, Green and Blue) and essentially acts as a bypass RAM. The output of the RAM drives the DACs with 24-bit data (8 bits each for Red, Green and Blue). The RAM is preloaded with a linear function.

This mode allows for the display of full 24-bit True-Color Images.

REV. A

–15–

ADV7150

Figure 20. 24-Bit to 24-Bit Direct True-Color Configuration

8-Bit “Gamma” Pseudo Color (CR25, CR26, CR27 = X, 0, 0 or X, 1, 0 or X, 0, 1 and MR11 = 1)

This mode sets the part into 8-bit Pseudo-Color operation. The pixel port accepts 8 bits of pixel data which indexes a 30-bit word in the Look-Up Table RAM. The Look-Up Table is configured as a 256 location by 30 bits deep RAM (10 bits each for Red, Green and Blue). The output of the RAM drives the DACs with 30-bit data (10 bits each for Red, Green and Blue).

Figure 21. 8-Bit to 30-Bit Pseudo-Color Configuration

This mode allows for the display of 256 simultaneous colors out of a total palette of millions of addressable colors.

8-Bit “Standard” Pseudo Color (CR25, CR26, CR27 = X, 0, 0 or X, 1, 0 or X, 0, 1 and MR11 = 0)

This mode sets the part into 8-bit Pseudo-Color operation. The pixel port accepts 8 bits of pixel data which indexes a 24-bit word in the Look-Up Table RAM. The Look-Up Table is configured as a 256 location by 24 bits deep RAM (10 bits each for Red, Green and Blue). The output of the RAM drives the DACs with 24-bit data (8 bits each for Red, Green and Blue).

Figure 22. 8-Bit to 24-Bit Pseudo-Color Configuration

This mode allows for the display of 256 simultaneous colors out of a total palette of millions of addressable colors.

ADV7150

15-Bit “Gamma” True Color (CR24, CR25, CR26, CR27 = 0, 0, 1, 1 or 1, 0, 1, 1 and MR11 = 1)

The part is set to 15-bit True-Color operation. The pixel port accepts 15-bits of color data which is mapped to the 5 LSBs of each of the red, green and blue palettes of the Look-Up Table RAM. The Look-Up Table is configured as a 32 location by 30 bits deep RAM (10 bits each for Red, Green and Blue). The output of the RAM drives the DACs with 30-bit data (10 bits each for Red, Green and Blue).

15-BIT

COLOR DATA

5 5

15-BIT TO 30-BIT LOOK-UP TABLE

RED

32 x 10

GREEN

32 x 10

BLUE

32 x 10

30-BIT

COLOR DATA

ANALOG VIDEO

10-BIT

RED DAC

10-BIT

GREEN DAC

10-BIT

BLUE DAC

OUTPUTS

RED OUT

GREEN OUT

BLUE OUT

Figure 23. 15-Bit to 30-Bit True-Color Configuration

This mode allows for the display of 15-bit, Gamma-Corrected True-Color Images.

15-Bit “Standard” True Color (CR24, CR25, CR26, CR27 = 0, 0, 1, 1 or 1, 0, 1, 1 and MR11 = 0)

The part is set to 15-bit True-Color operation. The pixel port accepts 15 bits of color data which is mapped to the 5 LSBs of each of the red, green and blue palettes of the Look-Up Table RAM. The Look-Up Table is configured as a 32 location by 24 bits deep RAM (8 bits each for Red, Green and Blue). The output of the RAM drives the DACs with 24-bit data (8 bits each for Red, Green and Blue).

8-BIT

RED DAC

8-BIT

GREEN DAC

8-BIT

BLUE DAC

ANALOG VIDEO

OUTPUTS

RED OUT

GREEN OUT

BLUE OUT

15-BIT

COLOR DATA

5 5 5

15-BIT TO 24-BIT

LOOK-UP TABLE

RED

32 x 8

GREEN

32 x 8

BLUE

32 x 8

24-BIT

COLOR DATA

Figure 24. 15-Bit to 24-Bit True-Color Configuration

R4 R3 R2 R1 R0

G4 G3 G2 G1 G0

B4 B3 B2 B1 B0

PIXEL INPUT DATA

x x x

R6 R5 R4 R3 R2 R1 R0

G7 G6 G5 G4 G3 G2 G1 G0

B7 B6 B5 B4 B3 B2 B1

PIN ASSIGNMENTS

R4 R3 R2 R1 R0

x x x

G4 G3 G2 G1 G0

x x x

B4 B3 B2 B1 B0

x x x

DATA LATCHED TO PIXEL PORT

0 0

0 R4 R3

R2 R1 R0

G4 G3

G2 G1 G0

B2 B1 B0

DATA INTERNALLY SHIFTED TO 5 LSBS

256 x 10

RAM

(RED LUT)

LOCATION "31"

LOCATION "0"

256 x 10

RAM

(GREEN LUT)

LOCATION "31"

LOCATION "0"

256 x 10

RAM

(BLUE LUT)

LOCATION "31"

LOCATION "0"

DATA LATCHES FIRST 32 LOCATIONS OF RAM

TO RED DAC

TO GREEN DAC

TO BLUE DAC

Figure 25. 15-Bit True-Color Mapping Using R3–R7, G3–G7 and B3–B7

This mode allows for the display of 15-bit True-Color Images.

PIXEL PORT MAPPING

The pixel data to the ADV7150 is automatically mapped in the parts pixel port as determined by the pixel data mode programmed (Bits CR24–CR27 of Command Register 2).

Pixel data in the 24-bit True-Color modes is directly mapped to the 24 color inputs R0–R7, G0–G7 and B0–B7.

There are three modes of operation for 8-bit Pseudo Color. Each mode maps the input pixel data differently. Data can be input one of the three color channels, R0–R7 or G0–G7 or B0–B7.

–16–

REV. A

ADV7150

R7 R6 R5 R4 R3 R2 R1 R0

G7 G6 G5 G4 G3 G2 G1 G0

B7 B6 B5 B4 B3 B2 B1

PIN ASSIGNMENTS

R4 R3 R2 R1 R0 G4 G3 G2

x G1 G0 G4 B4 B3 B2

x x x x x x x x

DATA LATCHED TO PIXEL PORT

0 0

0 R4 R3

R2 R1 R0

G4 G3

G1 G0

0 B4 B3

B2 B1 B0

DATA INTERNALLY SHIFTED TO 5 LSBS

256 x 10

RAM

(RED LUT)

LOCATION "31"

LOCATION "0"

256 x 10

RAM

(GREEN LUT)

LOCATION "31"

LOCATION "0"

256 x 10

RAM

(BLUE LUT)

LOCATION "31"

LOCATION "0"

DATA LATCHES FIRST 32 LOCATIONS OF RAM

TO RED DAC

TO GREEN DAC

TO BLUE DAC

R4 R3 R2 R1 R0 G4 G3 G2

x G1 G0 B4 B3 B2 B1

PIXEL INPUT DATA

Figure 26. 15-Bit True-Color Mapping Using R0–R7 and G0–G6

The part has two modes of operation for 15-bit True Color. In the first mode, data is input to the device over the red, green and blue channel (R3–R7, G3–G7 and B3–B7) and is internally mapped to locations 0 to 31 of the Look-Up Table (LUT) according to Figure 25. In the second mode, data is input to the device over just two of the color ports, red and green (R0–R7 and G0–G6) and is internally mapped to LUT locations 0 to 31 according to Figure 26. (Note: Data on unused pixel inputs is ignored.)

MICROPROCESSOR (MPU) PORT

The ADV7150 supports a standard MPU Interface. All the functions of the part are controlled via this MPU port. Direct access is gained to the Address Register, Mode Register and all the Control Registers as well as the Color Palette. The following sections describe the setup for reading and writing to all of the devices registers.

MPU Interface

The MPU interface (Figure 27) consists of a bidirectional, 10-bit wide databus and interface control signals and R/

W. The 10-bit wide databus is user configurable as

illustrated.

Table II. Databus Width Table

Databus RAM/DAC Read/Write Width Resolution Mode

10-Bit 10-Bit 10-Bit Parallel 10-Bit 8-Bit 8-Bit Parallel 8-Bit 10-Bit 8+2 Byte 8-Bit 8-Bit 8-Bit Parallel

The ADV7150 contains a number of onboard registers including the Mode Register (MR17–MR10), Address Register (A7– A0) and nine Control Registers as well as Red (R9–R0), Green (G9–G0) and Blue (B9–B0) Color Registers. These registers control the entire operation of the part. Figure 28 shows the internal register configuration.

Control lines C1 and C0 determine which register the MPU is accessing. C1 and C0 also determine whether the Address Register is pointing to the color registers and look-up table RAM or the control registers. If C1, C0 = 1, 0 the MPU has access to whatever control register is pointed to by the Address Register (A7–A0). If C1, C0 = 0, 1 the MPU has access to the Look-Up Table RAM (Color Palette) through the associated color registers. The

The R/

CE input latches data to or from the part.

W control input determines between read or write ac-

cesses. The Truth Tables III and IV show all modes of access to the various registers and color palette for both the 8-bit wide databus configuration and 10-bit wide databus configuration. It should be noted that after power-up, the devices MPU port is automatically set to 10-bit wide operation (see Power-On Reset section).

Color Palette Accesses

Data is written to the color palette by first writing to the address register of the color palette location to be modified. The MPU performs three successive write cycles for each of the red, green and blue registers (10-bit or 8-bit). An internal pointer moves from red to green to blue after each write is completed. This pointer is reset to red after a blue write or whenever the address register is written. During the blue write cycle, the three bytes of red, green and blue are concatenated into a single 30-bit/24-bit word and written to the RAM location as specified in the address register (A7–A0). The address register then automatically increments to point to the next RAM location and a similar red, green and blue palette write sequence is performed. The address register resets to 00H following a blue write cycle to color palette RAM location FFH.

CE, C0, C1

REV. A

–17–

ADV7150

ADDRESS

ADDR

(A7–A0)

CONTROL REGISTERS

R/W

MODE

(MR1)

C0 C1

PIXEL MASK

TEST

REGISTERS

MPU PORT

10 (8+2)

D9 – D0

COMMAND

REGISTERS

(CR1–CR3)

REVISION

DATA TO

PALETTES

Figure 27. MPU Port and Register Configuration

RED

COLOR REGISTERS

GREEN

BLUE

Data is read from the color palette by first writing to the address register of the color palette location to be read. The MPU performs three successive read cycles from each of the red, green and blue locations (10-bit or 8-bit) of the RAM. An internal pointer moves from red to green to blue after each read is completed. This pointer is reset to red after a blue read or whenever the address register is written. The address register then automatically increments to point to the next RAM location, and a similar red, green and blue palette read sequence is performed. The address register resets to 00H following a blue read cycle of color palette RAM location FFH.

MODE REGISTER

(MR17–MR10)

C1 = 1 C0 = 0

ADDRESS

(A15–A0)

00H

01H

02H

03H 04H 05H 06H 07H 08H 09H 0AH 0BH

* THIS REGISTER IS READ ONLY. A READ CYCLE WILL RETURN ZEROS "00".

CONTROL

REGISTERS

PIXEL TEST REGISTER R G B DAC TEST REGISTER R G B

SYNC, BLANK & I TEST REGISTER

ID REGISTER (READ ONLY) PIXEL MASK REGISTER COMMAND REGISTER 1 COMMAND REGISTER 2 COMMAND REGISTER 3 RESERVED* (READ ONLY) RESERVED* (READ ONLY) RESERVED* (READ ONLY) REVISION REGISTER

PLL

ADDRESS REGISTER

(A7–A0)

The MPU can write to or read from all of the ADV7150s registers. C0 and C1 determine whether the Mode Register or Address Register is being accessed. Access to these registers is direct. The Control Registers are accessed indirectly. The Address Register must point to the desired Control Register. Figure 28 along with the 8-bit and 10-bit Interface Truth Tables illustrate the structure and protocol for device communication over the MPU port.

C1 = 1 C0 = 1

C1 = 0 C0 = 0

C1 = 0 C0 = 1

RED

(R9–R0)

POINTS TO LOCATION CORRESPONDING TO ADDRESS REG (A7–A0)

GREEN

(G9–G0)

LOOK-UP TABLE RAM

(256 x 30)

ADDRESS REG = ADDRESS REG + 1

BLUE

(B9–B0)

Figure 28. Internal Register Configuration and Address Decoding

–18–

REV. A

ADV7150

Table III. Interface Truth Table (10-Bit Databus Mode)

R/W C1 C0 Databus (D9–D0) Operation Result

0 1 1 DB7–DB0 Write to Mode Register DB7–DB0 → MR17–MR10 0 0 0 DB7–DB0 Write to Address Register DB7–DB0 → A7–A0 0 1 0 DB7–DB0 Write to Control Registers DB7–DB0 → Control Register

(Particular Control Register Determined by Address Register)

0 0 1 DB9–DB0 Write to RED Register DB9–DB0 → R9–R0 0 0 1 DB9–DB0 Write to GREEN Register DB9–DB0 → G9–G0 0 0 1 DB9–DB0 Write to BLUE Register DB9–DB0 → B9–B0

Write RGB Data to RAM Location Pointed to by Address Register (A7–A0) Address Register = Address Register + 1

1 1 1 DB7–DB0 Read Mode Register MR17–MR10 → DB7–DB0 1 0 0 DB7–DB0 Read Address Register A7–A0 → DB7–DB0 1 1 0 DB7–DB0 Read Control Registers Register Data → DB7–DB0

(Particular Control Register Determined by Address Register)

1 0 1 DB9–DB0 Read RED RAM Location R9–R0 → DB9–DB0 1 0 1 DB9–DB0 Read GREEN RAM Location G9–G0→ DB9–DB0 1 0 1 DB9–DB0 Read BLUE RAM Location B9–B0 → DB9–DB0

(RAM Location Pointed to by Address Register(A7–A0))

Address Register = Address Register + 1

DB = Data Bit.

Table IV. Interface Truth Table (8-Bit Databus Mode)*

R/W C1 C0 Databus (D7–D0) Operation Result

0 1 1 DB7–DB0 Write to Mode Register DB7–DB0 → MR17–MR10 0 0 0 DB7–DB0 Write to Address Register DB7–DB0 → A7–A0 0 1 0 DB7–DB0 Write to Control Registers DB7–DB0 → Control Registers

(Particular Control Register Determined by Address Register (A7–A0))

0 0 1 DB9–DB2 Write to RED Register DB9–DB2 → R9–R2 0 0 1 DB1–DB0 Write to RED Register DB1–DB0 → R1–R0 0 0 1 DB9–DB2 Write to GREEN Register DB9–DB2 → G9–G2 0 0 1 DB1–DB0 Write to GREEN Register DB1–DB0 → G1–G0 0 0 1 DB9–DB2 Write to BLUE Register DB9–DB2 → B9–B2 0 0 1 DB1–DB0 Write to BLUE Register DB1–DB0 → B1–B0

Write RGB Data to RAM Location Pointed to by Address Register (A7-A0) Address Register = Address Register + 1

1 1 1 DB7–DB0 Read Mode Register MR17–MR10 → DB7–DB0 1 0 0 DB7–DB0 Read Address Register A7–A0 → DB7–DB0 1 1 0 DB7–DB0 Read Control Registers Register Data → DB7–DB0

(Particular Control Register Determined by Address Register)

1 0 1 DB9–DB2 Read RED RAM Location R9–R2 → DB9–DB2 1 0 1 DB1–DB0 Read RED RAM Location R1–R0 → DB1–DB0 1 0 1 DB9–DB2 Read GREEN RAM Location G9–G2 → DB9–DB2 1 0 1 DB1–DB0 Read GREEN RAM Location G1–G0 → DB1–DB0 1 0 1 DB9–DB2 Read BLUE RAM Location B9–B2 → DB9–DB2 1 0 1 DB1–DB0 Read BLUE RAM Location B1–B0 → DB1–DB0

(RAM Location Pointed to by Address Register (A7–A0))

Address Register = Address Register + 1

*Writing or reading 10-bit data (DB9–DB0) over an 8-bit databus (D7–D0) requires two write or two read cycles.

:DB9–DB2 is mapped to D7–D0 on the first cycle. :DB1–DB0 is mapped to D1–D0 on the second cycle.

DB = Data Bit.

REV. A

–19–

ADV7150

Power-On Reset

On power-up of the ADV7150 executes a power-on reset operation. This initializes the pixel port such that the pixel sequence ABCD starts at A. The Mode Register (MR17–MR10), Command Register 2 (CR27–CR20) and Command Register 3 (CR37–CR30) have all bits set to a Logic “1.” Command Register 1 (CR17–CR10) has all bits set to a Logic “0.”

The output clocking signals are also set during this reset period.

PRGCKOUT = CLOCK/32 LOADOUT = CLOCK/4

The power-on reset is activated when V

goes from 0 V to

5 V. This reset is active for 1 µs. The ADV7150 should not be accessed during this reset period. The pixel clock should be applied at power-up.

MR19

RESERVED*

* THESE BITS ARE READ-ONLY RESERVED BITS. A READ CYCLE WILL RETURN ZEROS "00."

MR18 MR15 MR14 MR13 MR12

PALETTE SELECT

MATCH BITS CONTROL

MR16 PS0

MR17 PS1

MR17 MR16

CALIBRATE

LOADIN

MR15

OPERATIONAL MODE CONTROL

MR14 MR13

0 0 RESERVED 0 1 NORMAL OPERATION 1 0 RESERVED 1 1 RESERVED

The following section describes each register, including Address Register, Mode Register and each of the nine Control Registers in terms of its configuration.

Address Register (A7–A0)

As illustrated in the previous tables, the C0 and C1 control inputs, in conjunction with this address register specify which control register, or color palette location is accessed by the MPU port. The address register is 8-bits wide and can be read from as well as written to. When writing to or reading from the color palette on a sequential basis, only the start address needs to be written. After a red, green and blue write sequence, the address register is automatically incremented.

MR11 MR10

MPU DATA BUS WIDTH

MR12

0 8-BIT (D7–D0) 1 10-BIT (D9–D0)

RAM-DAC

RESOLUTION CONTROL

MR11

0 8-BIT 1 10-BIT

RESET CONTROL

MR10

Mode Register 1 (MR1) (MR19–MR10)

MODE REGISTER MR1 (MR19–MR10)

The mode register is a 10-bit wide register. However for programming purposes, it may be considered as an 8-bit wide register (MR18 and MR19 are both reserved). It is denoted as MR17–MR10 for simplification purposes.

The diagram shows the various operations under the control of the mode register. This register can be read from as well written to. In read mode, if MR18 and MR19 are read back, they are both returned as zeros.

Mode Register (MR17–MR10) Bit Description Reset Control (MR10)

This bit is used to reset the pixel port sampling sequence. This ensures that the pixel sequence ABCD starts at A. It is reset by writing a “1” followed by a “0” followed by a “1.” This bit must be run through this cycle during the initialization sequence.

RAM-DAC Resolution Control (MR11)

When this is programmed with a “1,” the RAM is 30 bits deep (10 bits each for red, green and blue) and each of the three DACs is configured for 10-bit resolution. When MR11 is

–20–

programmed with a “0,” the RAM is 24-bits deep (8 bits each for red, green and blue) and the DACs are configured for 8-bit resolution. The two LSBs of the 10-bit DACs are pulled down to zero in 8-bit RAM-DAC mode.

MPU Databus Width (MR12)

This bit determines the width of the MPU port. It is configured as either a 10-bit wide (D9–D0) or 8-bit wide (D7–D0) bus. 10-bit data can be written to the device when configured in 8-bit wide mode. The 8 MSBs are first written on D7–D0, then the two LSBs are written over D1–D0. Bits D9–D8 are zeros in 8-bit mode.

Operational Mode Control (MR14–MR13)

When MR14 is “0” and MR13 is “1,” the part operates in normal mode.

Calibrate LOADIN (MR15)

This bit automatically calibrates the onboard LOADIN/ LOADOUT synchronization circuit. A “0” to “1” transition initiates calibration. This bit is set to “0” in normal operation. See “Pipeline Delay and Calibration” section. This bit must be run through this cycle during the initialization sequence.

REV. A

ADV7150

Palette Select Match Bits Control (MR17–MR16)

These bits allow multiple palette devices to work together. When bits PS1 and PS0 match MR17 and MR16 respectively, the device is selected. If these bits do not match, the device is not selected and the analog video outputs drive 0 mA, see “Palette Priority Select Inputs” section.

CONTROL REGISTERS

The ADV7150 has 9 control registers. To access each register, two write operations must be performed. The first write to the address register specifies which of the 9 registers is to be accessed. The second access determines the value written to that particular control register.

Pixel Test Register (Address Reg (A7–A0) = 00H)

This register is used when the device is in test/diagnostic mode. It is a 24-bit (8 bits each for RED, GREEN and BLUE) wide read-only register which allows the MPU to read data on the pixel port, see “Test Diagnostic” section.

DAC Test Register (Address Reg (A7–A0) = 01H)

This register is used when the device is in test/diagnostic mode. It is a 30-bit (10 bits each for RED, GREEN and BLUE) wide read-only register which allows MPU access to the DAC port, see “Test Diagnostic” section.

SYNC, BLANK and I

Test Register

PLL

(Address Reg (A7–A0) = 02H)

This register is used when the device is in test/diagnostic mode. It is a 3-bit wide (3 LSBs) read/write register which allows MPU access to these particular pixel control bits, see “Test Diagnostic” section.

ID Register (Address Reg (A7–A0) = 03H)

This is an 8-bit wide “Identification” read-only register. For the ADV7150 it will always return the hexadecimal value 8EH.

Pixel Mask Register (Address Reg (A7–A0) = 04H)

The contents of the pixel mask register are individually bit-wise logically AND-ed with the Red, Green and Blue pixel input stream of data. It is an 8-bit read/write register with D0 corresponding to R0, G0 and B0. For normal operation, this register is set with FFH.

COMMAND REGISTER 1 (CR1) (Address Reg (A7–A0) = 05H)

This register contains a number of control bits as shown in the diagram. CR1 is a 10-bit wide register. However for programming purposes, it may be considered as an 8-bit wide register (CR18 to CR19 are reserved).

The diagram below shows the various operations under the control of CR1. This register can be read from as well as written to. In write mode, “0” should be written to CR11 and CR13 to CR17. In read mode, CR11 and CR13 to CR19 are returned as zeros.

COMMAND REGISTER 1-BIT DESCRIPTION Calibration Control (CR10)

This bit automatically calibrates the onboard LOADIN/ LOADOUT synchronization circuit. MR15 of Mode Register MR1 must be set to “0.”

SYNCOUT Control (CR12)

This bit specified whether the video SYNCOUT signal is to be enabled. On power up a “0” is written to the bit and “

SYNCOUT” is set three-state.

CR18CR19

RESERVED*

*THESE BITS ARE READ–ONLY RESERVED BITS. A READ CYCLE WILL RETURN ZEROS "00."

CR17 CR16 CR15 CR14 CR12 CR11 CR10CR13

CR17-CR13

(00000)

THESE BITS SHOULD BE SET TO ZERO

SYNCOUT CONTROL

CR12

0 DISABLE 1 ENABLE SYNCOUT

Command Register 1 (CR1) (CR19–CR10)

CR11

(0)

THIS BIT SHOULD BE SET TO ZERO

CALIBRATION CONTROL

CR10

DISABLE

CALIBRATES ON EVERY VERTICAL SYNC (MR15=0)

REV. A

–21–

ADV7150

COMMAND REGISTER 2 (CR2) (Address Reg (A7–A0) = 06H)

This register contains a number of control bits as shown in the diagram. CR2 is a 10-bit wide register. However, for programming purposes, it may be considered as an 8-bit wide register (CR28 and CR29 are both reserved).

The diagram shows the various operations under the control of CR2. This register can be read from as well written to. In read mode, CR28 and CR29 are both returned as zeros.

COMMAND REGISTER 2-BIT DESCRIPTION R7 Trigger Polarity Control (CR20)

This bit is used when the device is in test/diagnostic mode. It determines whether the pixel data is latched into the test registers in the rising or falling edge of R7. (See “Test Diagnostics” section.)

Trigger Control (CR21)

PLL

This bit specifies whether the I

output is triggered from

PLL

BLANK or SYNC.

SYNC Recognition Control (CR22)

This bit specifies whether the video SYNC input is to be encoded onto the IOG analog output or ignored.

Pedestal Enable Control (CR23)

This bit specifies whether a 0 IRE or a 7.5 IRE blanking pedestal is to be generated on the video outputs.

True-Color/Pseudo-Color Mode Control (CR27–CR24)

These 4 bits specify the various color modes. These include a 24-bit true-color mode, two 15-bit true-color modes and three 8-bit pseudo color modes.

CR29 CR28

RESERVED*

*THESE BITS ARE READONLY RESERVED BITS. A READ CYCLE WILL RETURN ZEROS "00."

TRUE COLOR/PSEUDO-COLOR MODE CONTROL

CR27 CR26 CR24CR25

1 1100

1101

1000 000

CR26 CR25 CR24CR27

PEDESTAL ENABLE

CONTROL

CR23

0  0 IRE 1  7.5 IRE

MODE

8-BIT PSEUDO COLOR ON R7–R0 8-BIT PSEUDO COLOR ON G7–G0 8-BIT PSEUDO COLOR ON B7–B0 15-BIT TRUE COLOR ON R7–R3, G7–G3, B7–B3 15-BIT TRUE COLOR ON R7–R0, G6–G0

0111

24-BIT TRUE COLOR R7–R0, G7–G0, B7–B0

SYNC RECOGNITION CONTROL

CR22

0  IGNORE 1  DECODE

TRIGGER CONTROL

PLL

CR21

Command Register 2 (CR2) (CR29–CR20)

CR21CR23 CR22

SYNC

BLANK

R7 TRIGGER POLARITY CONTROL

CR20

–22–

REV. A

ADV7150

COMMAND REGISTER 3 (CR3) (Address Reg (A7–A0) = 07H)

This register contains a number of control bits as shown in the diagram. CR3 is a 10-bit wide register. However for programming purposes, it may be considered as an 8-bit wide register (CR38 and CR39 are both reserved).

The diagram shows the various operations under the control of CR3. This register can be read from as well written to. In read mode, CR38 and CR39 are both returned as zeros.

COMMAND REGISTER 3-BIT DESCRIPTION PRGCKOUT Frequency Control (CR31–CR30)

These bits specify the output frequency of the PRGCKOUT output. PRGCKOUT is a divided down version of the pixel CLOCK.

CR39 CR38 CR37 CR36 CR35 CR34 CR32 CR31 CR30CR33

RESERVED*

*THESE BITS ARE READONLY RESERVED BITS. A READ CYCLE WILL RETURN ZEROS "00."

EXTRA BLANK PIPELINE DELAY CONTROL (ADDS TO PIXEL PIPELINE DELAY; tPD)

CR35 CR34 CR33 CR32

BLANK Pipeline Delay Control (CR35–CR32)

These bits specify the additional pipeline delay that can be added to the pipeline delay (t

BLANK function, relative to the overall device

). As the BLANK control normally enters the

video DAC from a shorter pipeline than the video pixel data, this control is useful in deskewing the pipeline differential.

Pixel Multiplex Control (CR37–CR36)

These bits specify the device’s multiplex mode. It, therefore, also determines the frequency of the LOADOUT signal. LOADOUT is a divided down version of the pixel CLOCK.

Revision Register (Address Reg (A7–A0) = 0BH)

This register is a read only register containing the revision of silicon.

0 0 1

0 1 0

+ 1 x LOADOUT

+ 2 x LOADOUT

+ 15 x LOADOUT

PIXEL MULTIPLEX CONTROL

CR37 CR36

1:1 MUXING: LOADOUT = CLOCK ÷ 1

0 0 1 1

2:1 MUXING LOADOUT = CLOCK ÷ 2

RESERVED

4:1 MUXING :LOADOUT = CLOCK÷ 4

Command Register 3 (CR3) (CR39–CR30)

PRGCKOUT FREQUENCY

CONTROL

CR31 CR30

0 1 0 1

CLOCK ÷ 4

CLOCK ÷ 8

CLOCK ÷ 16 CLOCK ÷ 32

0 0 1

REV. A

–23–

ADV7150

DIGITAL-TO-ANALOG CONVERTERS (DACS) AND VIDEO OUTPUTS

The ADV7150 contains three high speed video DACs. The DAC outputs are represented as the three primary analog color signals IOR (red video), IOG (green video) and IOB (blue video). Other analog signals on the part include I complementary video outputs

IOR, IOG, IOB. These complementary outputs can be used to drive differentially terminated video loads, they will have equal but opposite output levels to IOR, IOG and IOB when loaded with a resistive load similar to IOR, IOG and IOB.

DACs and Analog Outputs

The part contains three matched 10-bit digital-to-analog converters. The DACs are designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each digital input are routed to either IOR, IOG, IOB (bit = “l”) or IOR, IOG, IOB (bit = “0”). (Normally IOR, IOG, IOB = GND.)

The analog video outputs are high impedance current sources. Each of the these three RGB current outputs are specified to directly drive a 37.5 Ω load (doubly terminated 75 Ω).

IOR, IOG, IOB

DACs

ZS = 75Ω

(SOURCE

TERMINATION)

ZO = 75Ω

(CABLE)

Figure 29. DAC Output Termination (Doubly Terminated 75

Ω

Load)

PLL

and V

as well as

REF

ZL = 75Ω (MONITOR)

Reference Input and R

SET

An external 1.23 V voltage reference is required to drive the analog outputs of the ADV7150. The reference voltage is connected to the V

A resistor R and ground. For specified performance, R

input.

REF

is connected between the R

SET

input of the part

SET

has a value of

SET

280 Ω. This corresponds to the generation of RS-343A video levels (with

SYNC on IOG and Pedestal = 7.5 IRE) into a doubly terminated 75 Ω load. Figure 30 illustrates the resulting video waveform, and the Video Output Truth Table shows the corresponding control input stimuli.

IOR, IOB IOG mA mA VV

1.44 0.054 9.05 0.340

26.67 1.0000.71419.05

0.286

7.62

92.5 IRE

7.5 IRE

40 IRE

GRAY SCALE

Figure 30. Composite Video Waveform ( on IOG; Pedestal = 7.5 IRE; R

= 280 Ω)

SET

SYNC

WHITE LEVEL

BLACK LEVEL

BLANK LEVEL

SYNC LEVEL

Decoded

Variations on RS-343A

Various other video output configurations can be implemented by the ADV7150, including RS-170. Values of R

for particu-

SET

lar output video formats/levels are calculated by using the equations for R table shows calculated values of R

given in the “Pin Configuration” section. The

SET

for some of the most com-

SET

mon variants on the RS-343A standard. The associated waveforms are shown in the diagrams.

Table V. Video Output Truth Table

IOG IOR, IOB DAC

Description (mA) (mA) SYNC BLANK Input Data

WHITE LEVEL 26.67 19.05 1 1 3FFH VIDEO Video + 9.05 Video + 1.44 1 1 Data VIDEO to

BLANK Video + 1.44 Video + 1.44 0 1 Data BLACK LEVEL 9.05 1.44 1 1 000H BLACK to

BLANK 1.44 1.44 0 1 000H BLANK LEVEL 7.62 0 1 0 xxxH SYNC LEVEL 0 0 0 0 xxxH

Decoded on IOG; Pedestal = 0 IRE; R

= 265 Ω.

SET

–24–

REV. A

ADV7150

IOR, IOB IOG mA mA VV

26.67 1.0000.69818.62

0.302

8.05

100 IRE

GRAY SCALE

43 IRE

Figure 31. Composite Video Waveform SYNC

IOR, IOB, IOG

mA V

19.05 0.714

0.054

1.44

92.5 IRE

GRAY SCALE

7.5 IRE

WHITE LEVEL

BLACK LEVEL

BLANK LEVEL

Figure 32. Composite Video Waveform (Pedestal = 7.5 IRE; R

IOR, IOB, IOG

mA V

19.05 0.714

= 280 Ω)

SET

WHITE LEVEL

BLACK/ BLANK LEVEL

SYNC LEVEL

(V) Video Signal

SET

265 280 No

SYNC decoded on IOG; Pedestal = 0 IRE

SYNC decoded; Pedestal = 7.5 IRE

259 No SYNC decoded; Pedestal = 0 IRE

Synchronization Output Control

PLL

This output synchronization signal is used in applications where it is necessary to synchronize multiple palette devices (ADV7150 + ADV7151) to subpixel resolution. Each devices I

PLL

output signal is in phase with its analog RGB output signal. If multiple devices have differing output delays, the time difference can be derived from the I to phase shift the

signals. This time difference is then used

PLL

CLOCK inputs on one or other of the devices

inputs. The I

signal is internally triggered by either the falling edge

PLL

SYNC or BLANK as determined by CR21 of Command

100 IRE

GRAY SCALE

Figure 33. Composite Video Waveform (Pedestal = 0 IRE; R

= 259 Ω)

SET

BLACK/ BLANK LEVEL

REV. A

–25–

ADV7150

APPENDIX 1

BOARD DESIGN AND LAYOUT CONSIDERATIONS

POWER SUPPLY DECOUPLING (0.1µF AND 0.01µF CAPACITOR FOR EACH VAA GROUP)

+5V (VAA)

0.1µF

COMP

ADV7150

GND

0.1µF 0.01µF

ANALOG POWER PLANE

IOR

IOG

IOB

IOR

IOG

IOB

REF

PLL

SET

(1% METAL)

SET

280Ω

75Ω 75Ω

V R

)

+5V (V

1kΩ

AD589 (1.2V REF)

75Ω

COMPLIMENTARY

OUTPUTS

0.1µF

0.01µF

+5V (VAA)

33µF

CO-AXIAL CABLE

(75Ω)

BNC

CONNECTORS

NOTES:

1. ALL RESISTORS ARE 1% METAL FILM

2. 0.1µF AND 0.01µF CAPACITORS ARE CERAMIC

3. ADDITIONAL DIGITALCIRCUITRY OMITTED FOR CLARITY

0.01µF

0.1µF

(FERRITE BEAD)

75Ω

MONITOR

(CRT)

0.1µF

+5V (VCC)

0.01µF

0.1µF

Recommended Analog Circuit Layout

The ADV7150 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system level design such that high speed, accurate performance is achieved. The “Recommended Analog Circuit Layout” shows the analog interface between the device and monitor.

The layout should be optimized for lowest noise on the ADV7150 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of V

and GND pins should by minimized so as to minimize inductive ringing.

Ground Planes

The ground plane should encompass all ADV7150 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7150, the analog output traces, and all the digital signal traces leading up to the ADV7150. The ground plane is the graphics board’s common ground plane.

Power Planes

The ADV7150 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (V

This power plane should be connected to the regular PCB

–26–

power plane (VCC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7150.

The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7150 power pins and voltage reference circuitry.

Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode.

Supply Decoupling

For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 µF ceramic capacitor decoupling. Each group of V

pins on the ADV7150 must have at least one 0.1 µF decoupling capacitor to GND. These capacitors should be placed as close as possible to the device.

It is important to note that while the ADV7150 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three terminal voltage regulator for supplying power to the analog power plane.

REV. A

ADV7150

Digital Signal Interconnect

The digital inputs to the ADV7150 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane.

Due to the high clock rates involved, long clock lines to the ADV7150 should be avoided to reduce noise pickup.

Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (V

), and not the

analog power plane.

Analog Signal Interconnect

The ADV7150 should be located as close as possible to the output connectors to minimize noise pick-up and reflections due to impedance mismatch.

The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection.

APPENDIX 2

TYPICAL FRAME BUFFER INTERFACE

CLOCK

GENERATOR

CLOCK

Digital Inputs, especially Pixel Data Inputs and clocking signals (CLOCK, LOADOUT, LOADIN, etc.) should never overlay any of the analog signal circuitry and should be kept as far away as possible.

For best performance, the analog outputs (IOR, IOG, IOB) should each have a 75 Ω load resistor connected to GND. These resistors should be placed as close as possible to the ADV7150 so as to minimize reflections. Normally, the differential analog outputs (

IOR, IOG, IOB) are connected directly to GND. In some applications, improvements in performance are achieved by terminating these differential outputs with a resistive load similar in value to the video load. For a doubly terminated 75 Ω load, this means that

IOR, IOG, IOB are each

terminated with 37.5 Ω resistors.

ECL

TTL

CLOCK

GRAPHICS PROCESSOR/ CONTROLLER

FRAME

BUFFER/

VIDEO

MEMORY

BLANK

SYNC

VRAM

(BANK A)

VRAM

(BANK B)

VRAM

(BANK C)

VRAM

(BANK D)

33MHz

PRGCKOUT

LOADOUT

SCKOUT

BLANK

SCKIN

LOADIN

DIVIDE BY N

(÷ N)

DIVIDE BY M

LATCH

ENABLESYNC

(÷ M)

ADV7150

MULTIPLEXER

24 TO

PALETTE/RAM & DAC

REV. A

–27–

ADV7150

APPENDIX 3

10-BIT DACS AND GAMMA CORRECTION

10-Bit DACs

10-Bit RAM-DAC resolution allows for nonlinear video correction, in particular Gamma Correction. The ADV7150 allows for an increase in color resolution from 24-bit to 30-bit effective color without the necessity of a 30-bit deep frame buffer. In true-color mode, for example, the part effectively operates as a 24-bit to 30-bit color look-up table.

Up to now we have assumed that there exists a linear relationship between the actual RGB values input to a monitor and the intensity produced on the screen. This, however, is not the case. Half scale digital input (1000 0000) might correspond to only 20% output intensity on the CRT (Cathode Ray Tube). The intensity (I

) produced on a CRT by an input value IIN is given by:

CRT

= (IIN)

where χ ranges from 2.0 to 2.8. If the individual values of χ for red, green and blue are known,

then so called “Gamma Correction” can be applied to each of the three video input signals (I

);

therefore:

IN(corrected)

= k(IIN)

1/χ

(k = 1, normally)

Traditionally, there has been a tradeoff between implementing a nonlinear graphics function, such as gamma correction, and color dynamic range. The ADV7150 overcomes this by increasing the individual color resolution of each of the red, green and blue primary colors from 8 bits per color channel to 10 bits per channel (24 bits to 30 bits).

The table highlights the loss of resolution when 8-bit data is gamma-corrected to a value of 2.7 and quantized in a traditional 8-bit system. Note that there is no change in the 8-bit quantized data for linear changes in the input data over much of the transfer function. On the other hand, when quantized to 10 bits via the 10-bit RAMs and 10-bit DACs of the ADV7150, all changes on the input 8-bit data are reflected in corresponding changes in the 10-bit data.

The graph shows a typical gamma curve corresponding to a gamma value of 2.7. This is programmed to the red, green and blue RAMs of the color lookup table instead of the more traditional linear function. Different curves corresponding to any particular gamma value can be independently programmed to each of the red, green and blue RAMs.

Other applications of the 10-bit RAM-DAC include closed-loop monitor color calibration.

Gamma Correction 8 Bits vs. 10 Bits

Gamma Corrected Quantized to Quantized to

8-Bit Data (2.7) 8 Bits 10 Bits

240 0.977797 250 1001 241 0.979304 250 1002 242 0.980807 251 1004 243 0.982306 251 1005 244 0.983801 251 1007 245 0.985292 252 1008 246 0.986780 252 1010 247 0.988264 252 1011 248 0.989744 253 1013 249 0.991220 253 1015 250 0.992693 254 1016 251 0.994161 254 1018 252 0.995626 254 1019 253 0.997088 255 1021 254 0.998546 255 1022 255 1.000000 255 1023

1.00

0.90

0.80

0.70

0.60

0.50

0.40

0.30

DAC OUTPUT – Normalized to 1

0.20

0.10

0.00 0

GAMMA CORRECTION CURVE

LINEAR RESPONSE PRECEIVED BY THE EYE

CRT RESPONSE

INPUT CODE – Decimal

2241921601289664

Gamma Correction Curve (Gamma Value = 2.7)

256

–28–

REV. A

APPENDIX 4

DACs

IOR, IOG, IOB

ZO = 75Ω

ZS = 75Ω

(SOURCE

TERMINATION)

ZL = 75Ω (MONITOR)

(CABLE)

DACs

IOR, IOG, IOB

(DEVICE: 2)

(DEVICE: 1)

MULTIPLE PALETTE APPLICATIONS

ADV7150

Palette Priority Select Inputs

The palette priority selection inputs allow up to four separate palette devices to be used in a single system to drive a single monitor with subpixel resolution. The IOR, IOG and IOB analog video output signals of each device are connected together, as shown. Signal inputs (PS0, PS1) determine on a pixel by pixel basis which palette device drives the monitor. This allows for implementation of multiple windows applications with each device acting as an independent palette. During initialization, each device is assigned two match bits, MR16 (PS0) and MR17 (PS1) in Mode Register MR1. PS0 and PS1 inputs will select one of the preprogrammed devices at any instant when PS0, PS1 matches MR16, MR17, respectively. PS0 and PS1 are multiplexed similar to the pixel data, thus allowing for subpixel resolution. The diagrams show an example of one ADV7150 operating in

ADV7150

R0–R7 G0–G7 B0–B7

PS0, PS1

256 x 30

RAM

PALETTE SELECT BITS

MR16 MR17

0 0

ANALOG

O/P

conjunction with three ADV7151’s (Pseudo-Color RAM-DACs). Each displayed window on the monitor is driven by one of the four devices, as determined on a pixel basis by PS0, PS1. Each device’s analog output signals are connected together as shown.

Note: Only one palette device is selected at any particular instant. The analog output levels of the unselected devices will be 0 mA.

Other applications for the palette priority function using a minimum of two devices (one ADV7150 and one ADV7151) include:

Cursor Overlay on 24-Bit Graphics Active Live Video Overlay (from Frame Grabber) Text/Character Generation and Overlay

Multiple Devices Termination for a Single Monitor

REV. A

P0–P7

ADV7151 (1)

256 x 30

PALETTE

PALETTE SELECT BITS

MR16 MR17

0 1

ADV7151 (2)

256 x 30

PALETTE

PALETTE SELECT BITS

MR16 MR17

1 0

ADV7151 (3)

256 x 30

PALETTE

PALETTE SELECT BITS

MR16 MR17

1 1

Multiple Devices Driving a Multiwindow Application

RGB

ANALOG

VIDEO

RGB

ANALOG

VIDEO

RGB

ANALOG

VIDEO

VIDEO TO MONITOR

–29–

MONITOR

TRUE-COLOR BACKGROUND

WINDOW 1

(Pseudo-Color)

PS0=0: PS1=1

WINDOW 2

(Pseudo-Color)

PS0=1: PS1=0

WINDOW 3

(Pseudo-Color)

PS0=1: PS1=1

ADV7150

APPENDIX 5

INITIALIZATION AND PROGRAMMING

ADV7150 Initialization

After power has been supplied, the ADV7150 must be initialized. The Mode Register and Control Registers must be set. The values written to the various registers will be determined by the desired operating mode of the part, i.e., True Color/Pseudo Color, 2:1 Muxing/2:1 Muxing, etc.

Example 1

Color Mode 24-Bit True Color Multiplexing 2:1 Databus 8-Bit RAM-DAC Resolution 8-Bit SYNC Enabled on IOG Pedestal 7.5 IRE

Write 09H to Mode Register (MR1) 1 1 0 Resets to Normal Operation, 8-Bit Bus/RAM-DAC Write 08H to Mode Register (MR1) 1 1 0 *(Initializes Pipelining Write 09H to Mode Register (MR1) 1 1 0 *( “ Write 29H to Mode Register (MR1) 1 1 0 *(Calibrates LOADOUT/LOADIN Timing Write 09H to Mode Register (MR1) 1 1 0 *( “ Write 04H to Address Register (A7–A0) 0 0 0 Address Reg Points to Pixel Mask Register Write FFH to Pixel Mask Register 1 0 0 Sets the Pixel Mask to All “1s” Write 05H to Address Register (A7–A0) 0 0 0 Address Reg Points to Command Register 1 (CR1) Write 00H to Command Reg 1 (CR1) 1 0 0 Write 06H to Address Register (A7–A0) 0 0 0 Address Reg Points to Command Register 2 (CR2) Write ECH to Command Reg 2 (CR2) 1 0 0 Sets 24-Bit Color, 7.5 IRE, Write 07H to Address Register (A7–A0) 0 0 0 Address Reg Points to Command Register 3 (CR3) Write C0H to Command Reg 3 (CR3) 1 0 0 Sets 2:1 Multiplexing, PRGCKOUT = CLOCK/4

Color Palette RAM Initialization C1 C0 R/W Comment

Write 00H to Address Register (A7–A0) 0 0 0 Points to Color Palette RAM Write 00H (Red Data) to RAM Location (00H) 0 1 0 (Initializes Palette RAM Write 00H (Green Data) to RAM Location (00H) 0 1 0 ( to a Linear Ramp** Write 00H (Blue Data) to RAM Location (00H) 0 1 0 ( Write 01H (Red Data) to RAM Location (01H) 0 1 0 ( Write 01H (Green Data) to RAM Location (01H) 0 1 0 ( Write 01H (Blue Data) to RAM Location (01H) 0 1 0 (

• ••• • •••(

• ••• • •••( Write FFH (Red Data) to RAM Location (FFH) 0 1 0 ( Write FFH (Green Data) to RAM Location (FFH) 0 1 0 ( Write FFH (Blue Data) to RAM Location (FFH) 0 1 0 (RAM Initialization Complete

The following section gives examples of initialization of the ADV7150 operating in various modes.

W Comment

SYNC on Green (IOG)

**These four command lines reset the ADV7150. The pipelines for each of the Red, Creen and Blue pixel inputs are synchronously reset to the Multiplexer’s

“A” input. Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.” LOADIN/LOADOUT timing is internally synchronized by writing a “0” followed by a “1” followed by a “0” to Mode Register MR15.

**This sequence of instructions would, of course, normally be coded using some form of loop instruction.

–30–

REV. A

ADV7150

Example 2

Color Mode 24-Bit Gamma Corrected True Color (30 Bits) Multiplexing 2:1 Databus 10 Bit RAM-DAC Resolution 10 Bit SYNC Ignored Pedestal 0 IRE Calibration Every Vertical Sync

Write 0FH to Mode Register (MR1) 1 1 0 Resets to Normal Operation, 10-Bit Bus/RAM-DAC Write 0EH to Mode Register (MR1) 1 1 0 *(Initializes Pipelining Write 0FH to Mode Register (MR1) 1 1 0 *( “ Write 2FH to Mode Register (MR1) 1 1 0 *(Calibrates LOADOUT/LOADIN Timing Write 0FH to Mode Register (MR1) 1 1 0 *( “ Write 04H to Address Register (A7–A0) 0 0 0 Address Reg Points to Pixel Mask Register Write FFH to Pixel Mask Register 1 0 0 Sets the Pixel Mask to All “1s” Write 05H to Address Register (A7–A0) 0 0 0 Address Reg Points to Command Register 1 (CR1) Write 01H to Command Reg 1 (CR1) 0 0 0 Calibrates Every Vertical Sync Write 06H to Address Register (A7–A0) 0 0 0 Address Reg Points to Command Register 2 (CR2) Write E0H to Command Reg 2 (CR2) 1 0 0 Sets 24-Bit Color, 0 IRE, No Write 07H to Address Register (A7–A0) 0 0 0 Address Reg Points to Command Register 3 (CR3) Write 41H to Command Reg 3 (CR3) 1 0 0 Sets 2:1 Multiplexing, PRGCKOUT =

Color Palette RAM Initialization C1 C0 R/

W Comment

Write 00H to Address Register (A7–A0) 0 0 0 Points to Color Palette RAM Write 000H (Red Data) to RAM Location (00H) 0 1 0 (Initializes Palette RAM Write 000H (Green Data) to RAM Location (00H) 0 1 0 ( to a “Gamma” Ramp** Write 000H (Blue Data) to RAM Location (00H) 0 1 0 ( Write xxxH (Red Data) to RAM Location (01H) 0 1 0 ( Write xxxH (Green Data) to RAM Location (01H) 0 1 0 ( Write xxxH (Blue Data) to RAM Location (01H) 0 1 0 (

• ••• • •••(

• ••• • •••( Write 3FFH (Red Data) to RAM Location (FFH) 0 1 0 ( Write 3FFH (Green Data) to RAM Location (FFH) 0 1 0 ( Write 3FFH (Blue Data) to RAM Location (FFH) 0 1 0 (RAM Initialization Complete

**These four command lines reset the ADV7150 The pipelines for each of the Red, Green and Blue pixel inputs are synchronously reset to the Multiplexer’s “A” in-

put. Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.” LOADIN/LOADOUT timing is internally synchronized by writing a “0” followed by a “1” followed by a “0” to Mode Register MR15.

**Data for a gamma curve characteristic is obtainable in Appendix 3.

The previous examples show the register initialization sequence for the ADV7150. These show control data going to the registers and palette RAM. As well as this writing function, it may also be necessary, due to system diagnostic requirements, to confirm that correct data has been transferred to each register and palette RAM location. There are two ways to incorporate register value/RAM value checking:

1. READ after each WRITE: After data is written to a particular register, it can be read back immediately. The following table shows an example with Command Registers CR2 and CR3.

C1 C0 R/W D0–D7 Comment

0 0 0 06H Select Command Register 2 (CR2) 1 0 0 E0H Sets 24-Bit True-Color 1 0 1 E0H Command Reg 2 Value Read-Back 0 0 0 07H Select Command Register 3 (CR3) 1 0 0 40H Set 2:1 Mux Mode 1 0 1 40H Command Reg 3 Value Read-Back

2. READ after all WRITEs completed: All registers and the color palette RAM are written to and set. Once this is complete, all registers are again accessed but this time in Read-Only mode. The table below shows this method for Command Registers CR2 and CR3.

C1 C0 R/W D0–D7 Comment

0 0 0 06H Select Command Register 2 (CR2) 1 0 0 E0H Sets 24-Bit True-Color 0 0 0 07H Select Command Register 3 (CR3) 1 0 0 40H Set 2:1 Mux Mode 0 0 0 06H Select CR2 1 0 1 E0H CR2 Value Read-Back 0 0 0 07H Select CR3 1 0 1 40H CR3 Value Read-Back 1 0 1 40H CR3 Value Read-Back

It is clear that this latter case requires more command lines than the previous READ after each WRITE case.

SYNC

CLOCK/8

REV. A

–31–

ADV7150

APPENDIX 6

TEST DIAGNOSTICS

SYNC

BLANK

PIXEL

DATA

INPUT

MUX

GRAPHICS PIPELINE GRAPHICS PIPELINE

TRIGGER

DECODE

PIXEL TEST

CE R/W C0 C1 D0–D9

COLOR

PALETTE

RAM

COLOR

REGISTERS

Test/Diagnostic Block Diagram

The ADV7150 contains onboard circuitry which enables both device and system level test diagnostics. The test circuitry can be used to test the frame buffer memory as well as the functionality of the ADV7150. A number of test registers are integrated into the part which effectively allow for monitoring of the graphics pipeline. Pixel data is read from the graphics pipeline independent of the pixel CLOCK. The pixel data itself contains the triggering information that latches data into the test registers. This allows for system diagnostics in a continuously clocked graphics system. The test register data is then read by the microprocessor over the MPU.

Access to the test registers is as described in the “Microprocessor (MPU) Port” section. This section also gives the address decode locations for the various test registers.

Test Trigger (R7)

The test trigger is decoded from the pixel data stream. Bit R7 of the RED channel is assigned the task of latching pixel data into the test registers. A “0” to “1” or a “1” to “0” (as determined by bit CR20 of Command Register 2) transition on R7, fills the test register with the corresponding pixel data. This effectively means that a sequence of data travels along the graphics pipeline, with the test registers taking a sample only when there is a transition on Bit R7. The following example shows a sequence with the ADV7150 preset to sample the graphics pipeline on a low to high transition of R7.

RED GREEN BLUE

Pixel 0: 00000000 00000000 00000000

Pixel 1: 0........ ........ ........

Pixel 2: 1........ ........ ........

Pixel 3: 0........ ........ ........

.... ...

Pixel n- l: 0........ ........ ........

Pixel n: 1........ ........ ........

Pixel n: 0........ ........ ........

In the above sequence of pixels, there is a rising edge on R7 on Pixel 2. The Red, Green and Blue data for Pixel 2, therefore, gets latched into the Pixel Test Register. Pixel 2 continues down

–32–

DACs

TRIGGER

MPU PORT

DECODE

DAC TEST

REGISTERS

SYNC

PLL

BLANK

TEST

the graphics pipeline and after a number of clocks get latched into the DAC Test Register. This data can then be read from the Pixel Test Register and the DAC Test Registers over the MPU Port. This data will remain in the Pixel Test Registers and the DAC Test Registers until the next rising edge of R7 causes new data to be latched in.

In the above example, the next rising edge of R7 occurs on the Pixel n input. Therefore the data in the Pixel Test Registers and DAC Test Registers must be read over the MPU before the Pixel n data is applied, otherwise they will be overwritten by the Pixel n data and the Pixel 2 data will be lost.

Pixel Test Register

The read-only Pixel Test Register is 24 bits wide, 8 bits each for red green and blue. It is situated directly after the Pixel Mask Register. After data is latched into this register by a transition on R7, it is read in three cycles over the MPU Port as described in the “Microprocessor (MPU) Port” section.

DAC Test Register

The DAC Test Register is latched with data some CLOCKs after the Pixel Test Register. The DAC Test Register is a 30-bit wide read-only register, corresponding to 10 bits each for red, green and blue data. It is located the Color Palette RAM. If the RAM-DAC is in 8-bit after resolution mode, the upper two bits of the red, green and blue data will be zero. After data is latched into the DAC Test Register by a transition on R7, it is read in three or six cycles over the MPU Port as described in the “Microprocessor (MPU) Port” section.

SYNC, BLANK and I

Test Register

PLL

This is an 8-bit wide register but with only three effective bits. The three lower bits correspond to

SYNC, BLANK and I

PLL

respectively. The upper bits should be masked in software. This register is at the same position in the graphics pipeline as the DAC Test Register. When pixel data is latched into the DAC Test Register, the corresponding status of I

is latched into this register. It is read over the MPU Port as

PLL

SYNC, BLANK and

described in the “Microprocessor (MPU) Port” section. (Note: If

BLANK is low, the corresponding pixel data to the

DAC Test Register will be all “0s.”)

REV. A

APPENDIX 7

THERMAL AND ENVIRONMENTAL CONSIDERATIONS

ADV7150

The ADV7150 is a very highly integrated monolithic silicon device. This high level of integration, in such a small package, inevitably leads to consideration of thermal and environmental conditions in which the ADV7150 must operate. Reliability of the device is significantly enhanced by keeping it as cool as possible. In order to avoid destructive damage to the device, the absolute maximum junction temperature of 150°C must never be exceeded. Certain applications, depending on pixel data rates, may require forced air cooling, or external heatsinks. The following data is intended as a guide in evaluating the operating conditions of a particular application so that optimum device and system performance is achieved.

It should be noted that information on package characteristics pub-

lished herein may not be the most up to date at the time of reading this. Advances in package compounds and manufacture will inevitably lead to improvements in the thermal data. Please contact your local sales office for the most up-to-date information.

Power Dissipation

The diagram shows graphs of power dissipation in watts vs. pixel clock frequency for the ADV7150.

1.50

= 5V

= 1.2V

1.25

1.00

0.75

POWER DISSIPATION – Watts

0.50

NOTE: THE "WORST CASE ON-SCREEN PATTERN" CORRESPONDS TO FULL-SCALE TRANSITION ON EACH PIXEL VALUE FOR EVERY CLOCK EDGE (00H, FFH, 00H, ... ). THE "TYPICAL ON-SCREEN PATTERN" CORRESPONDS TO LINEAR CHANGES IN THE PIXEL INPUT (I. E., A BLACK TO WHITE RAMP). IN GENERAL, COLOR IMAGES TEND TO APPROXIMATE THIS CHARACTERISTIC.

REF

= +25°C

60 22080 180 200160140120100

PIXEL CLOCK FREQUENCY – MHz

Table A. Thermal Characteristics vs. Airflow

Air Velocity 0 50 100 200 (Linear feet/min) (Still Air)

(°C/W)

No Heatsink 25.5 23 21 19 EG&G D10100-28 Heatsink 23 20 18 16 Thermalloy 2290 Heatsink 19 17 15 12

Thermal Model

The junction temperature of the device in a specific application is given by:

= TA + PD (

) (1)

= TA + PD (

) (2)

where:

= Junction Temperature of Silicon (°C)

= Ambient Temperature (°C)

= Power Dissipation (W)

= Junction to Case Thermal Resistance (°C/W)

= Case to Ambient Thermal Resistance (°C/W)

= Junction to Ambient Thermal Resistance (°C/W)

Package Enhancements

The standard QFP package has been enhanced to a PowerQuad2 package. This supports an improved thermal performance compared to standard QFP. In this case, the die is attached to heatslug so that the power that is dissipated can be conducted to the external surface of the package. This provides a highly efficient path for the transfer of heat to the package surface. The package configuration also provides an efficient thermal path from the ADV7150 to the Printed Circuit Board via the leads.

Heatsinks

The maximum silicon junction temperature should be limited to 100°C. Temperatures greater than this will reduce long term device reliability. To ensure that the silicon junction temperature stays within prescribed limits, the addition of an external heatsink may be necessary. Heatsinks, will reduce θ

as shown

in the “Thermal Characteristics vs. Airflow” table.

Typical Power Dissipation vs. Pixel Rate

Package Characteristics

The table of thermal characteristics shows typical information for the ADV7150 (160-Lead Plastic Power QFP) using various values of Airflow.

Junction to Case (θ

) Thermal Resistance for this particular

part is:

(160-Lead Plastic Power QFP) = 1.0°C/W

(Note: θ

REV. A

is independent of airflow.)

–33–

ADV7150

APPENDIX 8

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

S-160

160-Lead Plastic Power Quad Flatpack

0.037 (0.95)

0.026 (0.65)

SEATING

PLANE

0.004 (0.10) MAX

0.070 (1.77)

0.062 (1.57)

0.160 (4.07)

4°±4° MAX

0.145 (3.67)

0.125 (3.17)

MAX

6°±4°

10°

0.070 (1.77)

0.062 (1.57)

121

160

120

1.239 (31.45)

1.219 (30.95)

1.107 (28.10)

1.100 (27.90)

PIN 1

0.026 (0.65) MIN

TOP VIEW

(PINS DOWN)

0.014 (0.35)

0.011 (0.27)

–34–

REV. A

–35–

C1695–10–8/94

–36–

PRINTED IN U.S.A.

REV. A

Datasheet ADV7150 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual