ANALOG DEVICES ADV 7123 KSTZ Datasheet
CMOS, 330 MHz
V
FEATURES
330 MSPS throughput rate
Triple 10-bit digital-to-analog converters (DACs)
SFDR
−70 dB at f
−53 dB at f
RS-343A-/RS-170-compatible output
Complementary outputs
DAC output current range: 2.0 mA to 26.5 mA
TTL-compatible inputs
Internal reference (1.235 V)
Single-supply 5 V/3.3 V operation
48-lead LQFP package
Low power dissipation (30 mW minimum @ 3 V)
Low power standby mode (6 mW typical @ 3 V)
Industrial temperature range (−40°C to +85°C)
Pb-free (lead-free) package
APPLICATIONS
Digital video systems (1600 × 1200 @ 100 Hz)
High resolution color graphics
Digital radio modulation
Image processing
Instrumentation
Video signal reconstruction
= 50 MHz; f
CLK
= 140 MHz; f
CLK
= 1 MHz
OUT
= 40 MHz
OUT
Triple 10-Bit High Speed Video DAC
ADV7123
FUNCTIONAL BLOCK DIAGRAM
AA
BLANK
SYNC
R9 TO R0
G9 TO G0
B9 TO B0
PSAVE
CLOCK
10
REGISTER
10
REGISTER
10
REGISTER
POWER-DOWN
DATA
DATA
DATA
MODE
10
10
10
R
COMPGND
SET
Figure 1.
DAC
DAC
DAC
BLANK AND
SYNC LOGIC
VOLTAGE
REFERENCE
CIRCUIT
ADV7123
IOR
IOR
IOG
IOG
IOB
IOB
V
REF
00215-001
GENERAL DESCRIPTION
The ADV7123 (ADV®) is a triple high speed, digital-to-analog
converter on a single monolithic chip. It consists of three high
speed, 10-bit, video DACs with complementary outputs, a
standard TTL input interface, and a high impedance, analog
output current source.
The ADV7123 has three separate 10-bit-wide input ports. A
single 5 V/3.3 V power supply and clock are all that are required
to make the part functional. The ADV7123 has additional video
control signals, composite
SYNC
The ADV7123 also has a power save mode.
ADV is a registered trademark of Analog Devices, Inc.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
and
BLANK
.
The ADV7123 is fabricated in a 5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. The ADV7123 is available in a
48-lead LQFP package.
PRODUCT HIGHLIGHTS
1. 330 MSPS throughput.
2. Guaranteed monotonic to 10 bits.
3. Compatible with a wide variety of high resolution color
graphics systems, including RS-343A and RS-170.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
ADV7123
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
5 V Specifications ......................................................................... 3
3.3 V Specifications ...................................................................... 4
5 V Dynamic Specifications ........................................................ 5
3.3 V Dynamic Specifications ..................................................... 6
5 V Timing Specifications ........................................................... 7
3.3 V Timing Specifications ........................................................ 8
Absolute Maximum Ratings ............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 12
5 V Typical Performance Characteristics ................................ 12
3 V Typical Performance Characteristics ................................ 14
Terminology .................................................................................... 16
Circuit Description and Operation .............................................. 17
Digital Inputs .............................................................................. 17
Clock Input .................................................................................. 17
Video Synchronization and Control ........................................ 18
Reference Input ........................................................................... 18
DACs ............................................................................................ 18
Analog Outputs .......................................................................... 18
Gray Scale Operation ................................................................. 19
Video Output Buffers ................................................................. 19
PCB Layout Considerations ...................................................... 19
Digital Signal Interconnect ....................................................... 19
Analog Signal Interconnect....................................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
7/10—Rev. C to Rev. D
Changes to Figure 2 .......................................................................... 9
Changes to Figure 22 and Figure 23 ............................................. 17
Changes to Table 9 .......................................................................... 18
3/09—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Features Section............................................................ 1
Changes to Table 5 ............................................................................ 7
Changes to Table 6 ............................................................................ 8
Changes to Table 8 .......................................................................... 10
Changed f
Changes to Figure 6, Figure 7, and Figure 8................................ 12
Changes to Figure 13 and Figure 17 ............................................. 14
Deleted Ground Planes Section, Power Planes Section, and
Supply Decoupling Section ........................................................... 15
Changes to Figure 23 ...................................................................... 17
Changes to Table 9, Analog Outputs Section, Figure 24, and
Figure 25 .......................................................................................... 18
Changes to Video Output Buffers Section and PCB Layout
Considerations Section .................................................................. 19
Changes to Analog Signal Interconnect Section and
Figure 28 .......................................................................................... 20
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
CLOCK
to f
..................................................................... 12
CLK
10/02—Rev. A to Rev. B
Change in Title ................................................................................... 1
Change to Feature .............................................................................. 1
Change to Product Highlights ......................................................... 1
Change Specifications ....................................................................... 3
Change to Pin Function Descriptions ......................................... 10
Change to Reference Input section .............................................. 18
Change to Figure 28 ....................................................................... 22
Updated Outline Dimensions ....................................................... 23
Change to Ordering Guide ............................................................ 23
Rev. D | Page 2 of 24
ADV7123
SPECIFICATIONS
5 V SPECIFICATIONS
VAA = 5 V ± 5%, V
Table 1.
Parameter Min Typ Max Unit Test Conditions1
STATIC PERFORMANCE
Resolution (Each DAC) 10 Bits
Integral Nonlinearity (BSL) −1 ±0.4 +1 LSB
Differential Nonlinearity −1 ±0.25 +1 LSB Guaranteed Monotonic
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH 2 V
Input Low Voltage, VIL 0.8 V
Input Current, IIN −1 +1 μA VIN = 0.0 V or VDD
PSAVE Pull-Up Current
Input Capacitance, CIN 10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA
DAC-to-DAC Matching 1.0 5 %
Output Compliance Range, VOC 0 1.4 V
Output Impedance, R
Output Capacitance, C
Offset Error −0.025 +0.025 % FSR Tested with DAC output = 0 V
Gain Error2 −5.0 +5.0 % FSR FSR = 17.62 mA
VOLTAGE REFERENCE, EXTERNAL AND
INTERNAL
Reference Range, V
POWER DISSIPATION
Digital Supply Current3 3.4 9 mA f
10.5 15 mA f
18 25 mA f
Analog Supply Current 67 72 mA R
8 mA R
Standby Supply Current4 2.1 5.0 mA
Power Supply Rejection Ratio 0.1 0.5 %/%
1
Temperature range T
2
Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal = V
3
Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
4
These maximum/minimum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.
= 1.235 V, R
REF
= 560 Ω, CL = 10 pF. All specifications T
SET
MIN
to T
,1 unless otherwise noted, T
MAX
20 μA
Green DAC, SYNC
2.0 18.5 mA
100 kΩ
OUT
10 pF I
OUT
RGB DAC, SYNC
= 0 mA
OUT
1.12 1.235 1.35 V
REF
= 50 MHz
CLK
= 140 MHz
CLK
= 240 MHz
CLK
= 560 Ω
SET
= 4933 Ω
SET
= low, digital, and control inputs at VDD
PSAVE
to T
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
MIN
MAX
/R
× K × (0x3FFH) and K = 7.9896.
REF
SET
= high
= low
J MAX
= 110°C.
Rev. D | Page 3 of 24
ADV7123
3.3 V SPECIFICATIONS
VAA = 3.0 V to 3.6 V, V
Table 2.
Parameter2 Min Typ Max Unit Test Conditions1
STATIC PERFORMANCE
Resolution (Each DAC) 10 Bits R
Integral Nonlinearity (BSL) −1 +0.5 +1 LSB R
Differential Nonlinearity −1 +0.25 +1 LSB R
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Input Current, IIN −1 +1 μA VIN = 0.0 V or VDD
PSAVE Pull-Up Current
Input Capacitance, CIN 10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA
DAC-to-DAC Matching 1.0 %
Output Compliance Range, VOC 0 1.4 V
Output Impedance, R
Output Capacitance, C
Offset Error 0 0 % FSR Tested with DAC output = 0 V
Gain Error3 0 % FSR FSR = 17.62 mA
VOLTAGE REFERENCE, EXTERNAL
Reference Range, V
VOLTAGE REFERENCE, INTERNAL
Voltage Reference, V
POWER DISSIPATION
Digital Supply Current4 2.2 5.0 mA f
6.5 12.0 mA f
11 15 mA f
16 mA f
Analog Supply Current 67 72 mA R
8 mA R
Standby Supply Current 2.1 5.0 mA
Power Supply Rejection Ratio 0.1 0.5 %/%
1
Temperature range T
2
These maximum/minimum specifications are guaranteed by characterization to be over the 3.0 V to 3.6 V range.
3
Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal = V
4
Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
= 1.235 V, R
REF
= 560 Ω, CL = 10 pF. All specifications T
SET
MIN
to T
MAX
= 680 Ω
SET
= 680 Ω
SET
= 680 Ω
SET
20 μA
Green DAC, SYNC
2.0 18.5 mA
70 kΩ
OUT
10 pF
OUT
1.12 1.235 1.35 V
REF
1.235 V
REF
to T
MIN
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
MAX
× K × (0x3FFH) and K = 7.9896.
REF/RSET
RGB DAC, SYNC
= 50 MHz
CLK
= 140 MHz
CLK
= 240 MHz
CLK
= 330 MHz
CLK
= 560 Ω
SET
= 4933 Ω
SET
= low, digital, and control inputs at VDD
PSAVE
,1 unless otherwise noted, T
= high
= low
J MAX
= 110°C.
Rev. D | Page 4 of 24
ADV7123
5 V DYNAMIC SPECIFICATIONS
VAA = 5 V ± 5%,1 V
Table 3.
Parameter1 Min Typ Max Unit
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist2
Single-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
Double-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
Spurious-Free Dynamic Range Within a Window
Single-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 140 MHz; f
CLK
Double-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 140 MHz; f
CLK
Total Harmonic Distortion
f
= 50 MHz; f
CLK
TA = 25°C 66 dBc
T
to T
MIN
f
= 50 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
= 1.235 V, R
REF
= 1.00 MHz 67 dBc
OUT
= 2.51 MHz 67 dBc
OUT
= 5.04 MHz 63 dBc
OUT
= 20.2 MHz 55 dBc
OUT
= 2.51 MHz 62 dBc
OUT
= 5.04 MHz 60 dBc
OUT
= 20.2 MHz 54 dBc
OUT
= 40.4 MHz 48 dBc
OUT
= 2.51 MHz 57 dBc
OUT
= 5.04 MHz 58 dBc
OUT
= 20.2 MHz 52 dBc
OUT
= 40.4 MHz 41 dBc
OUT
= 1.00 MHz 70 dBc
OUT
= 2.51 MHz 70 dBc
OUT
= 5.04 MHz 65 dBc
OUT
= 20.2 MHz 54 dBc
OUT
= 2.51 MHz 67 dBc
OUT
= 5.04 MHz 63 dBc
OUT
= 20.2 MHz 58 dBc
OUT
= 40.4 MHz 52 dBc
OUT
= 2.51 MHz 62 dBc
OUT
= 5.04 MHz 61 dBc
OUT
= 20.2 MHz 55 dBc
OUT
= 40.4 MHz 53 dBc
OUT
= 1.00 MHz; 1 MHz Span 77 dBc
OUT
= 5.04 MHz; 2 MHz Span 73 dBc
OUT
= 5.04 MHz; 4 MHz Span 64 dBc
OUT
= 1.00 MHz; 1 MHz Span 74 dBc
OUT
= 5.00 MHz; 2 MHz Span 73 dBc
OUT
= 5.00 MHz; 4 MHz Span 60 dBc
OUT
= 1.00 MHz
OUT
65 dBc
MAX
= 2.00 MHz 64 dBc
OUT
= 2.00 MHz 63 dBc
OUT
= 2.00 MHz 55 dBc
OUT
= 560 Ω, CL = 10 pF. All specifications are TA = 25°C, unless otherwise noted, T
SET
Rev. D | Page 5 of 24
J MAX
= 110°C.
ADV7123
Parameter1 Min Typ Max Unit
DAC PERFORMANCE
Glitch Impulse 10 pV-sec
DAC-to-DAC Crosstalk3 23 dB
Data Feedthrough4, 5 22 dB
Clock Feedthrough4, 5 33 dB
1
These maximum/minimum specifications are guaranteed by characterization over the 4.75 V to 5.25 V range.
2
Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, V
3
DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5
TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured from the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
3.3 V DYNAMIC SPECIFICATIONS
VAA = 3.0 V to 3.6 V1, V
Table 4.
Parameter Min Typ Max Unit
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist2
Single-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
Double-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
Spurious-Free Dynamic Range Within a Window
Single-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 140 MHz; f
CLK
Double-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 140 MHz; f
CLK
= 1.235 V, R
REF
= 1.00 MHz 67 dBc
OUT
= 2.51 MHz 67 dBc
OUT
= 5.04 MHz 63 dBc
OUT
= 20.2 MHz 55 dBc
OUT
= 2.51 MHz 62 dBc
OUT
= 5.04 MHz 60 dBc
OUT
= 20.2 MHz 54 dBc
OUT
= 40.4 MHz 48 dBc
OUT
= 2.51 MHz 57 dBc
OUT
= 5.04 MHz 58 dBc
OUT
= 20.2 MHz 52 dBc
OUT
= 40.4 MHz 41 dBc
OUT
= 1.00 MHz 70 dBc
OUT
= 2.51 MHz 70 dBc
OUT
= 5.04 MHz 65 dBc
OUT
= 20.2 MHz 54 dBc
OUT
= 2.51 MHz 67 dBc
OUT
= 5.04 MHz 63 dBc
OUT
= 20.2 MHz 58 dBc
OUT
= 40.4 MHz 52 dBc
OUT
= 2.51 MHz 62 dBc
OUT
= 5.04 MHz 61 dBc
OUT
= 20.2 MHz 55 dBc
OUT
= 40.4 MHz 53 dBc
OUT
= 1.00 MHz; 1 MHz Span 77 dBc
OUT
= 5.04 MHz; 2 MHz Span 73 dBc
OUT
= 5.04 MHz; 4 MHz Span 64 dBc
OUT
= 1.00 MHz; 1 MHz Span 74 dBc
OUT
= 5.00 MHz; 2 MHz Span 73 dBc
OUT
= 5.00 MHz; 4 MHz Span 60 dBc
OUT
= 680 Ω, CL = 10 pF. All specifications are TA = 25°C, unless otherwise noted, T
SET
.
REF
= 110°C.
J MAX
Rev. D | Page 6 of 24
ADV7123
Parameter Min Typ Max Unit
Total Harmonic Distortion
f
= 50 MHz; f
CLK
TA = 25°C 66 dBc
T
to T
MIN
f
= 50 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
DAC PERFORMANCE
Glitch Impulse 10 pV-sec
DAC-to-DAC Crosstalk3 23 dB
Data Feedthrough4, 5 22 dB
Clock Feedthrough4, 5 33 dB
1
These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range.
2
Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, V
3
DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5
TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
5 V TIMING SPECIFICATIONS
VAA = 5 V ± 5%,1 V
= 1.00 MHz
OUT
65 dBc
MAX
= 2.00 MHz 64 dBc
OUT
= 2.00 MHz 64 dBc
OUT
= 2.00 MHz 55 dBc
OUT
.
REF
= 1.235 V, R
REF
= 560 Ω, CL = 10 pF. All specifications T
SET
MIN
to T
,2 unless otherwise noted, T
MAX
J MAX
= 110°C.
Table 5.
Parameter3 Symbol Min Typ Max Unit Conditions
ANALOG OUTPUTS
Analog Output Delay t6 5.5 ns
Analog Output Rise/Fall Time4 t7 1.0 ns
Analog Output Transition Time5 t8 15 ns
Analog Output Skew6 t9 1 2 ns
CLOCK CONTROL
CLOCK Frequency7 f
0.5 50 MHz 50 MHz grade
CLK
0.5 140 MHz 140 MHz grade
0.5 240 MHz 240 MHz grade
Data and Control Setup t1 0.5 ns
Data and Control Hold t2 1.5 ns
CLOCK Period t3 4.17 ns
CLOCK Pulse Width High t4 1.875 ns f
CLOCK Pulse Width Low t5 1.875 ns f
CLOCK Pulse Width High t4 2.85 ns f
CLOCK Pulse Width Low t5 2.85 ns f
CLOCK Pulse Width High t4 8.0 ns f
CLOCK Pulse Width Low t5 8.0 ns f
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
= 240 MHz
= 240 MHz
= 140 MHz
= 140 MHz
= 50 MHz
= 50 MHz
Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles
PSAVE Up Time
1
These maximum and minimum specifications are guaranteed over this range.
2
Temperature range: T
3
Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
CLK
6
to T
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.
MIN
MAX
t
2 10
10
ns
Rev. D | Page 7 of 24
ADV7123
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V to 3.6 V,1 V
Table 6.
Parameter3 Symbol Min Typ Max Unit Conditions
ANALOG OUTPUTS
Analog Output Delay t6 7.5 ns
Analog Output Rise/Fall Time4 t
Analog Output Transition Time5 t
Analog Output Skew6 t
CLOCK CONTROL
CLOCK Frequency7 f
140 MHz 140 MHz grade
240 MHz 240 MHz grade
330 MHz 330 MHz grade
Data and Control Setup t1 0.2 ns
Data and Control Hold t2 1.5 ns
CLOCK Period t3 3 ns
CLOCK Pulse Width High6 t4 1.4 ns f
CLOCK Pulse Width Low6 t5 1.4 ns f
CLOCK Pulse Width High t4 1.875 ns f
CLOCK Pulse Width Low t5 1.875 ns f
CLOCK Pulse Width High t4 2.85 ns f
CLOCK Pulse Width Low t5 2.85 ns f
CLOCK Pulse Width High t4 8.0 ns f
CLOCK Pulse Width Low t5 8.0 ns f
Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles
PSAVE Up Time
1
These maximum and minimum specifications are guaranteed over this range.
2
Temperature range: T
3
Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
CLK
6
to T
MIN
= 1.235 V, R
REF
= 560 Ω, CL = 10 pF. All specifications T
SET
MIN
1.0 ns
7
15 ns
8
1 2 ns
9
50 MHz 50 MHz grade
CLK
t
4 10
10
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
MAX
t
3
t
4
t
5
to T
,2 unless otherwise noted, T
MAX
ns
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
= 110°C.
J MAX
= 330 MHz
= 330 MHz
= 240 MHz
= 240 MHz
= 140 MHz
= 140 MHz
= 50 MHz
= 50 MHz
CLOCK
(R9 TO R0, G9 TO G0, B9 TO B0,
(IOR, IOR, IOG, IOG, IOB, IOB)
NOTES
1. OUTPUT DELAY (
OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FAL L TIME (
3. TRANSITION TIME (
FINAL OUTPUT VALUE.
DIGITAL INPUTS
SYNC, BLANK)
ANALOG OUT PUT S
t
) MEASURED FRO M THE 50% POINT OF THE RI SING EDGE OF CLOCK T O THE 50% POINT
6
t
t
) MEASURED FRO M THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF T HE
8
t
2
t
1
) MEASURED BETWEEN THE 10% AND 90% PO INTS OF FULL-SCALE TRANSIT ION.
7
t
6
t
8
t
7
Figure 2. Timing Diagram
Rev. D | Page 8 of 24
00215-002
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