Page 1
CMOS, 330 MHz
V
FEATURES
330 MSPS throughput rate
Triple 10-bit digital-to-analog converters (DACs)
SFDR
−70 dB at f
−53 dB at f
RS-343A-/RS-170-compatible output
Complementary outputs
DAC output current range: 2.0 mA to 26.5 mA
TTL-compatible inputs
Internal reference (1.235 V)
Single-supply 5 V/3.3 V operation
48-lead LQFP package
Low power dissipation (30 mW minimum @ 3 V)
Low power standby mode (6 mW typical @ 3 V)
Industrial temperature range (−40°C to +85°C)
Pb-free (lead-free) package
APPLICATIONS
Digital video systems (1600 × 1200 @ 100 Hz)
High resolution color graphics
Digital radio modulation
Image processing
Instrumentation
Video signal reconstruction
= 50 MHz; f
CLK
= 140 MHz; f
CLK
= 1 MHz
OUT
= 40 MHz
OUT
Triple 10-Bit High Speed Video DAC
ADV7123
FUNCTIONAL BLOCK DIAGRAM
AA
BLANK
SYNC
R9 TO R0
G9 TO G0
B9 TO B0
PSAVE
CLOCK
10
REGISTER
10
REGISTER
10
REGISTER
POWER-DOWN
DATA
DATA
DATA
MODE
10
10
10
R
COMPGND
SET
Figure 1.
DAC
DAC
DAC
BLANK AND
SYNC LOGIC
VOLTAGE
REFERENCE
CIRCUIT
ADV7123
IOR
IOR
IOG
IOG
IOB
IOB
V
REF
00215-001
GENERAL DESCRIPTION
The ADV7123 (ADV®) is a triple high speed, digital-to-analog
converter on a single monolithic chip. It consists of three high
speed, 10-bit, video DACs with complementary outputs, a
standard TTL input interface, and a high impedance, analog
output current source.
The ADV7123 has three separate 10-bit-wide input ports. A
single 5 V/3.3 V power supply and clock are all that are required
to make the part functional. The ADV7123 has additional video
control signals, composite
SYNC
The ADV7123 also has a power save mode.
ADV is a registered trademark of Analog Devices, Inc.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
and
BLANK
.
The ADV7123 is fabricated in a 5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. The ADV7123 is available in a
48-lead LQFP package.
PRODUCT HIGHLIGHTS
1. 330 MSPS throughput.
2. Guaranteed monotonic to 10 bits.
3. Compatible with a wide variety of high resolution color
graphics systems, including RS-343A and RS-170.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
Page 2
ADV7123
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
5 V Specifications ......................................................................... 3
3.3 V Specifications ...................................................................... 4
5 V Dynamic Specifications ........................................................ 5
3.3 V Dynamic Specifications ..................................................... 6
5 V Timing Specifications ........................................................... 7
3.3 V Timing Specifications ........................................................ 8
Absolute Maximum Ratings ............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 12
5 V Typical Performance Characteristics ................................ 12
3 V Typical Performance Characteristics ................................ 14
Terminology .................................................................................... 16
Circuit Description and Operation .............................................. 17
Digital Inputs .............................................................................. 17
Clock Input .................................................................................. 17
Video Synchronization and Control ........................................ 18
Reference Input ........................................................................... 18
DACs ............................................................................................ 18
Analog Outputs .......................................................................... 18
Gray Scale Operation ................................................................. 19
Video Output Buffers ................................................................. 19
PCB Layout Considerations ...................................................... 19
Digital Signal Interconnect ....................................................... 19
Analog Signal Interconnect....................................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
7/10—Rev. C to Rev. D
Changes to Figure 2 .......................................................................... 9
Changes to Figure 22 and Figure 23 ............................................. 17
Changes to Table 9 .......................................................................... 18
3/09—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Features Section............................................................ 1
Changes to Table 5 ............................................................................ 7
Changes to Table 6 ............................................................................ 8
Changes to Table 8 .......................................................................... 10
Changed f
Changes to Figure 6, Figure 7, and Figure 8................................ 12
Changes to Figure 13 and Figure 17 ............................................. 14
Deleted Ground Planes Section, Power Planes Section, and
Supply Decoupling Section ........................................................... 15
Changes to Figure 23 ...................................................................... 17
Changes to Table 9, Analog Outputs Section, Figure 24, and
Figure 25 .......................................................................................... 18
Changes to Video Output Buffers Section and PCB Layout
Considerations Section .................................................................. 19
Changes to Analog Signal Interconnect Section and
Figure 28 .......................................................................................... 20
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
CLOCK
to f
..................................................................... 12
CLK
10/02—Rev. A to Rev. B
Change in Title ................................................................................... 1
Change to Feature .............................................................................. 1
Change to Product Highlights ......................................................... 1
Change Specifications ....................................................................... 3
Change to Pin Function Descriptions ......................................... 10
Change to Reference Input section .............................................. 18
Change to Figure 28 ....................................................................... 22
Updated Outline Dimensions ....................................................... 23
Change to Ordering Guide ............................................................ 23
Rev. D | Page 2 of 24
Page 3
ADV7123
SPECIFICATIONS
5 V SPECIFICATIONS
VAA = 5 V ± 5%, V
Table 1.
Parameter Min Typ Max Unit Test Conditions1
STATIC PERFORMANCE
Resolution (Each DAC) 10 Bits
Integral Nonlinearity (BSL) −1 ±0.4 +1 LSB
Differential Nonlinearity −1 ±0.25 +1 LSB Guaranteed Monotonic
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH 2 V
Input Low Voltage, VIL 0.8 V
Input Current, IIN −1 +1 μA VIN = 0.0 V or VDD
PSAVE Pull-Up Current
Input Capacitance, CIN 10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA
DAC-to-DAC Matching 1.0 5 %
Output Compliance Range, VOC 0 1.4 V
Output Impedance, R
Output Capacitance, C
Offset Error −0.025 +0.025 % FSR Tested with DAC output = 0 V
Gain Error2 −5.0 +5.0 % FSR FSR = 17.62 mA
VOLTAGE REFERENCE, EXTERNAL AND
INTERNAL
Reference Range, V
POWER DISSIPATION
Digital Supply Current3 3.4 9 mA f
10.5 15 mA f
18 25 mA f
Analog Supply Current 67 72 mA R
8 mA R
Standby Supply Current4 2.1 5.0 mA
Power Supply Rejection Ratio 0.1 0.5 %/%
1
Temperature range T
2
Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal = V
3
Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
4
These maximum/minimum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.
= 1.235 V, R
REF
= 560 Ω, CL = 10 pF. All specifications T
SET
MIN
to T
,1 unless otherwise noted, T
MAX
20 μA
Green DAC, SYNC
2.0 18.5 mA
100 kΩ
OUT
10 pF I
OUT
RGB DAC, SYNC
= 0 mA
OUT
1.12 1.235 1.35 V
REF
= 50 MHz
CLK
= 140 MHz
CLK
= 240 MHz
CLK
= 560 Ω
SET
= 4933 Ω
SET
= low, digital, and control inputs at VDD
PSAVE
to T
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
MIN
MAX
/R
× K × (0x3FFH) and K = 7.9896.
REF
SET
= high
= low
J MAX
= 110°C.
Rev. D | Page 3 of 24
Page 4
ADV7123
3.3 V SPECIFICATIONS
VAA = 3.0 V to 3.6 V, V
Table 2.
Parameter2 Min Typ Max Unit Test Conditions1
STATIC PERFORMANCE
Resolution (Each DAC) 10 Bits R
Integral Nonlinearity (BSL) −1 +0.5 +1 LSB R
Differential Nonlinearity −1 +0.25 +1 LSB R
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Input Current, IIN −1 +1 μA VIN = 0.0 V or VDD
PSAVE Pull-Up Current
Input Capacitance, CIN 10 pF
ANALOG OUTPUTS
Output Current 2.0 26.5 mA
DAC-to-DAC Matching 1.0 %
Output Compliance Range, VOC 0 1.4 V
Output Impedance, R
Output Capacitance, C
Offset Error 0 0 % FSR Tested with DAC output = 0 V
Gain Error3 0 % FSR FSR = 17.62 mA
VOLTAGE REFERENCE, EXTERNAL
Reference Range, V
VOLTAGE REFERENCE, INTERNAL
Voltage Reference, V
POWER DISSIPATION
Digital Supply Current4 2.2 5.0 mA f
6.5 12.0 mA f
11 15 mA f
16 mA f
Analog Supply Current 67 72 mA R
8 mA R
Standby Supply Current 2.1 5.0 mA
Power Supply Rejection Ratio 0.1 0.5 %/%
1
Temperature range T
2
These maximum/minimum specifications are guaranteed by characterization to be over the 3.0 V to 3.6 V range.
3
Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal = V
4
Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
= 1.235 V, R
REF
= 560 Ω, CL = 10 pF. All specifications T
SET
MIN
to T
MAX
= 680 Ω
SET
= 680 Ω
SET
= 680 Ω
SET
20 μA
Green DAC, SYNC
2.0 18.5 mA
70 kΩ
OUT
10 pF
OUT
1.12 1.235 1.35 V
REF
1.235 V
REF
to T
MIN
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
MAX
× K × (0x3FFH) and K = 7.9896.
REF/RSET
RGB DAC, SYNC
= 50 MHz
CLK
= 140 MHz
CLK
= 240 MHz
CLK
= 330 MHz
CLK
= 560 Ω
SET
= 4933 Ω
SET
= low, digital, and control inputs at VDD
PSAVE
,1 unless otherwise noted, T
= high
= low
J MAX
= 110°C.
Rev. D | Page 4 of 24
Page 5
ADV7123
5 V DYNAMIC SPECIFICATIONS
VAA = 5 V ± 5%,1 V
Table 3.
Parameter1 Min Typ Max Unit
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist2
Single-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
Double-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
Spurious-Free Dynamic Range Within a Window
Single-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 140 MHz; f
CLK
Double-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 140 MHz; f
CLK
Total Harmonic Distortion
f
= 50 MHz; f
CLK
TA = 25°C 66 dBc
T
to T
MIN
f
= 50 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
= 1.235 V, R
REF
= 1.00 MHz 67 dBc
OUT
= 2.51 MHz 67 dBc
OUT
= 5.04 MHz 63 dBc
OUT
= 20.2 MHz 55 dBc
OUT
= 2.51 MHz 62 dBc
OUT
= 5.04 MHz 60 dBc
OUT
= 20.2 MHz 54 dBc
OUT
= 40.4 MHz 48 dBc
OUT
= 2.51 MHz 57 dBc
OUT
= 5.04 MHz 58 dBc
OUT
= 20.2 MHz 52 dBc
OUT
= 40.4 MHz 41 dBc
OUT
= 1.00 MHz 70 dBc
OUT
= 2.51 MHz 70 dBc
OUT
= 5.04 MHz 65 dBc
OUT
= 20.2 MHz 54 dBc
OUT
= 2.51 MHz 67 dBc
OUT
= 5.04 MHz 63 dBc
OUT
= 20.2 MHz 58 dBc
OUT
= 40.4 MHz 52 dBc
OUT
= 2.51 MHz 62 dBc
OUT
= 5.04 MHz 61 dBc
OUT
= 20.2 MHz 55 dBc
OUT
= 40.4 MHz 53 dBc
OUT
= 1.00 MHz; 1 MHz Span 77 dBc
OUT
= 5.04 MHz; 2 MHz Span 73 dBc
OUT
= 5.04 MHz; 4 MHz Span 64 dBc
OUT
= 1.00 MHz; 1 MHz Span 74 dBc
OUT
= 5.00 MHz; 2 MHz Span 73 dBc
OUT
= 5.00 MHz; 4 MHz Span 60 dBc
OUT
= 1.00 MHz
OUT
65 dBc
MAX
= 2.00 MHz 64 dBc
OUT
= 2.00 MHz 63 dBc
OUT
= 2.00 MHz 55 dBc
OUT
= 560 Ω, CL = 10 pF. All specifications are TA = 25°C, unless otherwise noted, T
SET
Rev. D | Page 5 of 24
J MAX
= 110°C.
Page 6
ADV7123
Parameter1 Min Typ Max Unit
DAC PERFORMANCE
Glitch Impulse 10 pV-sec
DAC-to-DAC Crosstalk3 23 dB
Data Feedthrough4, 5 22 dB
Clock Feedthrough4, 5 33 dB
1
These maximum/minimum specifications are guaranteed by characterization over the 4.75 V to 5.25 V range.
2
Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, V
3
DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5
TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured from the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
3.3 V DYNAMIC SPECIFICATIONS
VAA = 3.0 V to 3.6 V1, V
Table 4.
Parameter Min Typ Max Unit
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist2
Single-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
Double-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
f
= 140 MHz; f
CLK
Spurious-Free Dynamic Range Within a Window
Single-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 140 MHz; f
CLK
Double-Ended Output
f
= 50 MHz; f
CLK
f
= 50 MHz; f
CLK
f
= 140 MHz; f
CLK
= 1.235 V, R
REF
= 1.00 MHz 67 dBc
OUT
= 2.51 MHz 67 dBc
OUT
= 5.04 MHz 63 dBc
OUT
= 20.2 MHz 55 dBc
OUT
= 2.51 MHz 62 dBc
OUT
= 5.04 MHz 60 dBc
OUT
= 20.2 MHz 54 dBc
OUT
= 40.4 MHz 48 dBc
OUT
= 2.51 MHz 57 dBc
OUT
= 5.04 MHz 58 dBc
OUT
= 20.2 MHz 52 dBc
OUT
= 40.4 MHz 41 dBc
OUT
= 1.00 MHz 70 dBc
OUT
= 2.51 MHz 70 dBc
OUT
= 5.04 MHz 65 dBc
OUT
= 20.2 MHz 54 dBc
OUT
= 2.51 MHz 67 dBc
OUT
= 5.04 MHz 63 dBc
OUT
= 20.2 MHz 58 dBc
OUT
= 40.4 MHz 52 dBc
OUT
= 2.51 MHz 62 dBc
OUT
= 5.04 MHz 61 dBc
OUT
= 20.2 MHz 55 dBc
OUT
= 40.4 MHz 53 dBc
OUT
= 1.00 MHz; 1 MHz Span 77 dBc
OUT
= 5.04 MHz; 2 MHz Span 73 dBc
OUT
= 5.04 MHz; 4 MHz Span 64 dBc
OUT
= 1.00 MHz; 1 MHz Span 74 dBc
OUT
= 5.00 MHz; 2 MHz Span 73 dBc
OUT
= 5.00 MHz; 4 MHz Span 60 dBc
OUT
= 680 Ω, CL = 10 pF. All specifications are TA = 25°C, unless otherwise noted, T
SET
.
REF
= 110°C.
J MAX
Rev. D | Page 6 of 24
Page 7
ADV7123
Parameter Min Typ Max Unit
Total Harmonic Distortion
f
= 50 MHz; f
CLK
TA = 25°C 66 dBc
T
to T
MIN
f
= 50 MHz; f
CLK
f
= 100 MHz; f
CLK
f
= 140 MHz; f
CLK
DAC PERFORMANCE
Glitch Impulse 10 pV-sec
DAC-to-DAC Crosstalk3 23 dB
Data Feedthrough4, 5 22 dB
Clock Feedthrough4, 5 33 dB
1
These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range.
2
Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, V
3
DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5
TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
5 V TIMING SPECIFICATIONS
VAA = 5 V ± 5%,1 V
= 1.00 MHz
OUT
65 dBc
MAX
= 2.00 MHz 64 dBc
OUT
= 2.00 MHz 64 dBc
OUT
= 2.00 MHz 55 dBc
OUT
.
REF
= 1.235 V, R
REF
= 560 Ω, CL = 10 pF. All specifications T
SET
MIN
to T
,2 unless otherwise noted, T
MAX
J MAX
= 110°C.
Table 5.
Parameter3 Symbol Min Typ Max Unit Conditions
ANALOG OUTPUTS
Analog Output Delay t6 5.5 ns
Analog Output Rise/Fall Time4 t7 1.0 ns
Analog Output Transition Time5 t8 15 ns
Analog Output Skew6 t9 1 2 ns
CLOCK CONTROL
CLOCK Frequency7 f
0.5 50 MHz 50 MHz grade
CLK
0.5 140 MHz 140 MHz grade
0.5 240 MHz 240 MHz grade
Data and Control Setup t1 0.5 ns
Data and Control Hold t2 1.5 ns
CLOCK Period t3 4.17 ns
CLOCK Pulse Width High t4 1.875 ns f
CLOCK Pulse Width Low t5 1.875 ns f
CLOCK Pulse Width High t4 2.85 ns f
CLOCK Pulse Width Low t5 2.85 ns f
CLOCK Pulse Width High t4 8.0 ns f
CLOCK Pulse Width Low t5 8.0 ns f
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
= 240 MHz
= 240 MHz
= 140 MHz
= 140 MHz
= 50 MHz
= 50 MHz
Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles
PSAVE Up Time
1
These maximum and minimum specifications are guaranteed over this range.
2
Temperature range: T
3
Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
CLK
6
to T
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.
MIN
MAX
t
2 10
10
ns
Rev. D | Page 7 of 24
Page 8
ADV7123
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V to 3.6 V,1 V
Table 6.
Parameter3 Symbol Min Typ Max Unit Conditions
ANALOG OUTPUTS
Analog Output Delay t6 7.5 ns
Analog Output Rise/Fall Time4 t
Analog Output Transition Time5 t
Analog Output Skew6 t
CLOCK CONTROL
CLOCK Frequency7 f
140 MHz 140 MHz grade
240 MHz 240 MHz grade
330 MHz 330 MHz grade
Data and Control Setup t1 0.2 ns
Data and Control Hold t2 1.5 ns
CLOCK Period t3 3 ns
CLOCK Pulse Width High6 t4 1.4 ns f
CLOCK Pulse Width Low6 t5 1.4 ns f
CLOCK Pulse Width High t4 1.875 ns f
CLOCK Pulse Width Low t5 1.875 ns f
CLOCK Pulse Width High t4 2.85 ns f
CLOCK Pulse Width Low t5 2.85 ns f
CLOCK Pulse Width High t4 8.0 ns f
CLOCK Pulse Width Low t5 8.0 ns f
Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles
PSAVE Up Time
1
These maximum and minimum specifications are guaranteed over this range.
2
Temperature range: T
3
Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
CLK
6
to T
MIN
= 1.235 V, R
REF
= 560 Ω, CL = 10 pF. All specifications T
SET
MIN
1.0 ns
7
15 ns
8
1 2 ns
9
50 MHz 50 MHz grade
CLK
t
4 10
10
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
MAX
t
3
t
4
t
5
to T
,2 unless otherwise noted, T
MAX
ns
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
CLK_MAX
= 110°C.
J MAX
= 330 MHz
= 330 MHz
= 240 MHz
= 240 MHz
= 140 MHz
= 140 MHz
= 50 MHz
= 50 MHz
CLOCK
(R9 TO R0, G9 TO G0, B9 TO B0,
(IOR, IOR, IOG, IOG, IOB, IOB)
NOTES
1. OUTPUT DELAY (
OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FAL L TIME (
3. TRANSITION TIME (
FINAL OUTPUT VALUE.
DIGITAL INPUTS
SYNC, BLANK)
ANALOG OUT PUT S
t
) MEASURED FRO M THE 50% POINT OF THE RI SING EDGE OF CLOCK T O THE 50% POINT
6
t
t
) MEASURED FRO M THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF T HE
8
t
2
t
1
) MEASURED BETWEEN THE 10% AND 90% PO INTS OF FULL-SCALE TRANSIT ION.
7
t
6
t
8
t
7
Figure 2. Timing Diagram
Rev. D | Page 8 of 24
00215-002
Page 9
ADV7123
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
VAA to GND 7 V
Voltage on Any Digital Pin GND − 0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) −40°C to +85°C
Storage Temperature (TS) −65°C to +150°C
Junction Temperature (TJ) 150°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase Soldering (1 Minute) 220°C
I
to GND1 0 V to VAA
OUT
1
Analog output short circuit to any power supply or common GND can be of
an indefinite duration.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. D | Page 9 of 24
Page 10
ADV7123
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SET
R
36
V
REF
35
COMP
34
IOR
33
IOR
32
IOG
31
IOG
30
V
AA
V
29
AA
28
IOB
27
IOB
26
GND
25
GND
B9
CLOCK
00215-003
BLANK
SYNC
R9R8R7R6R5R4R3R2R1R0PSAVE
48 47 46 45 44 43 42 41 40 39 38 37
1
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
PIN 1
2
INDICATOR
3
4
5
6
7
8
9
10
11
12
13
AA
V
ADV7123
TOP VIEW
(Not to Scale)
14 15
161718
B0B1B2B3B4B5B6B7B8
19 202122 23 24
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 10,
14 to 23,
39 to 48
11
12
G0 to G9,
B0 to B9,
R0 to R9
Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog outputs,
BLANK
Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a 40 IRE current
SYNC
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of CLOCK. R0,
G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular printed circuit board (PCB) power or ground plane.
IOR, IOB, and IOG, to the blanking level. The BLANK
BLANK
is a Logic 0, the R0 to R9, G0 to G9, and B0 to B9 pixel inputs are ignored.
source. This is internally connected to the IOG analog output. SYNC
signal is latched on the rising edge of CLOCK. While
does not override any other control or
data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising
edge of CLOCK. If sync information is not required on the green channel, the SYNC
Logic 0.
13, 29, 30 VAA Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7123 must be connected.
24 CLOCK
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R9, G0 to G9, B0 to B9, SYNC
pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven
BLANK
by a dedicated TTL buffer.
25, 26 GND Ground. All GND pins must be connected.
27, 31, 33
, IOG, IOR Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video
IOB
outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω load. If
the complementary outputs are not required, these outputs should be tied to ground.
28, 32, 34 IOB, IOG, IOR
Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or
not they are all being used.
35 COMP
36 V
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
REF
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor
must be connected between COMP and V
.
AA
input should be tied to
, and
Rev. D | Page 10 of 24
Page 11
ADV7123
Pin No. Mnemonic Description
37 R
R
The relationship between R
IOR, IOB (mA) = 7989.6 × V
38
SET
PSAVE
A resistor (R
) connected between this pin and GND controls the magnitude of the full-scale video signal.
SET
Note that the IRE relationships are maintained, regardless of the full-scale output current. For nominal video
levels into a doubly terminated 75 Ω load, R
output current on IOG (assuming I
(Ω) = 11,445 × V
SET
IOG (mA) = 11,445 × V
(V)/IOG (mA)
REF
SET
(V)/R
REF
is connected to IOG) is given by:
SYNC
and the full-scale output current on IOR, IOG, and IOB is given by:
(Ω) (SYNC being asserted)
SET
(V)/R
REF
The equation for IOG is the same as that for IOR and IOB when SYNC
= 530 Ω. The relationship between R
SET
(Ω)
SET
and the full-scale
SET
is not being used, that is, SYNC tied
permanently low.
Power Save Control Pin. Reduced power consumption is available on the ADV7123 when this pin is active.
Rev. D | Page 11 of 24
Page 12
ADV7123
TYPICAL PERFORMANCE CHARACTERISTICS
5 V TYPICAL PERFORMANCE CHARACTERISTICS
VAA = 5 V, V
SFDR (dBc)
Figure 4. SFDR vs. f
SFDR (dBc)
Figure 5. SFDR vs. f
72.0
71.8
71.6
71.4
= 1.235 V, I
REF
70
60
50
40
30
20
10
0
0.1 1
@ f
OUT
80
70
60
50
40
30
20
10
0
0.1 1 20.22.51 40.4 1005.04
SFDR (DE)
SFDR (SE)
@ f
OUT
= 17.62 mA, 50 Ω doubly terminated load, differential output loading, TA = 25°C, unless otherwise noted.
OUT
SFDR (DE)
SFDR (SE)
f
OUT
= 140 MHz (Single-Ended and Differential) Figure 7. THD vs. f
CLK
f
OUT
= 50 MHz (Single-Ended and Differential) Figure 8. Linearity vs. I
CLK
(MHz)
(MHz)
20.22.51 40.4
76
(MHz)
(mA)
SECOND
HARMONIC
THIRD
HARMONIC
OUT
00215-007
17.622
00215-008
0.75
74
72
70
68
66
THD (dBc)
64
62
60
1005.04
00215-004
00215-005
58
0 160
1.0
0.9
0.8
0.7
0.6
0.5
0.4
LINEARITY (LSB)
0.3
0.2
0.1
0
1.0
0.5
FOURTH
HARMONIC
50 100 140
f
CLK
@ f
= 2 MHz (Second, Third, and Fourth Harmonics)
CLK
OUT
I
OUT
71.2
SFDR (dBc)
71.0
70.8
70.6
70.4
Figure 6. SFDR vs. Temperature @ f
TEMPERATURE (°C)
= 50 MHz (f
CLK
= 1 MHz)
OUT
856545–10 255
0215-006
Rev. D | Page 12 of 24
0
ERROR (LSB)
–0.5
–1.0
CODE (INL)
1023
–0.16
00215-009
Figure 9. Typical Linearity (INL)
Page 13
ADV7123
–
–
–
5
5
–45
SFDR (dBm)
–85
0kHz
START
Figure 10. Single-Tone SFDR @ f
5
–45
SFDR (dBm)
–85
0kHz
START
Figure 11. Single-Tone SFDR @ f
35MHz 70MHz
= 140 MHz (f
CLK
35MHz 70MHz
= 140 MHz (f
CLK
OUT
= 2 MHz)
OUT
= 20 MHz)
STOP
STOP
–45
SFDR (dBm)
–85
0kHz
00215-010
START
Figure 12. Dual-Tone SFDR @ f
35MHz 70MHz
= 140 MHz (f
CLK
= 13.5 MHz, f
OUT1
STOP
= 14.5 MHz)
OUT2
00215-012
00215-011
Rev. D | Page 13 of 24
Page 14
ADV7123
3 V TYPICAL PERFORMANCE CHARACTERISTICS
VAA = 3 V, V
SFDR (dBc)
Figure 13. SFDR vs. f
= 1.235 V, I
REF
70
60
OUT
SFDR (SE)
@ f
CLK
50
40
30
20
10
0
1.0 20.22.51 40.4 1005.04
= 17.62 mA, 50 Ω doubly terminated load, differential output loading, TA = 25°C.
OUT
76
SFDR (DE)
f
(MHz)
OUT
= 140 MHz (Single-Ended and Differential)
74
72
70
68
66
THD (dBc)
64
62
60
58
00215-013
Figure 16. THD vs. f
THIRD HARMONIC
CLK
SECOND HARMONIC
50 100 1400 160
FREQUENCY (M Hz )
@ f
= 2 MHz (Second, Third, and Fourth Harmonics)
OUT
FOURTH
HARMONIC
0215-016
80
70
60
50
40
SFDR (dBc)
30
20
10
0
0.1 1 20.22.51 40.4 1005.04
Figure 14. SFDR vs. f
72.0
71.8
71.6
71.4
71.2
SFDR (dBc)
71.0
70.8
70.6
SFDR (DE)
SFDR (SE)
OUT
f
(MHz)
OUT
@ f
= 140 MHz (Single-Ended and Differential)
CLK
1.0
0.9
0.8
0.7
0.6
0.5
0.4
LINEARITY (LSB)
0.3
0.2
0.1
0
2
I
(mA)
00215-014
Figure 17. Linearity vs. I
1.0
0.5
0
LINEARITY (LSB)
–0.5
OUT
OUT
17.62
00215-017
0.75
1023
–0.42
70.4
20 85 145
TEMPERATURE (°C)
Figure 15. SFDR vs. Temperature @ f
= 50 MHz, (f
CLK
= 1 MHz)
OUT
1650
0215-015
Rev. D | Page 14 of 24
–1.0
CODE (INL)
Figure 18. Typical Linearity
00215-018
Page 15
ADV7123
–
–
–
5
–45
SFDR (dBm)
–85
0kHz
START
Figure 19. Single-Tone SFDR @ f
5
–45
SFDR (dBm)
35MHz 70MHz
= 140 MHz (f
CLK
= 2 MHz)
OUT
STOP
5
–45
SFDR (dBm)
–85
0kHz
00215-019
START
Figure 21. Dual-Tone SFDR @ f
35MHz 70MHz
= 140 MHz (f
CLK
= 13.5 MHz, f
OUT1
STOP
= 14.5 MHz)
OUT2
00215-021
–85
0kHz
START
Figure 20. Single-Tone SFDR @ f
35MHz 70MHz
= 140 MHz (f
CLK
OUT
STOP
= 20 MHz)
00215-020
Rev. D | Page 15 of 24
Page 16
ADV7123
TERMINOLOGY
Blanking Level
SYNC
The level separating the
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level that shuts off the picture
tube, resulting in the blackest possible picture.
Color Video (RGB)
This refers to the technique of combining the three primary
colors of red, green, and blue to produce color pictures within
the usual spectrum. In RGB monitors, three DACs are required,
one for each color.
Sync Signal (
The position of the composite video signal that synchronizes
the scanning process.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. A 10-bit DAC contains 1024 different
levels, while an 8-bit DAC contains 256.
SYNC
)
portion from the video portion
Raster Scan
The most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Sync Level
The peak level of the
Video Signal
The portion of the composite video signal that varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion that can be
visually observed.
SYNC
signal.
Rev. D | Page 16 of 24
Page 17
ADV7123
CIRCUIT DESCRIPTION AND OPERATION
The ADV7123 contains three 10-bit DACs, with three input
channels, each containing a 10-bit register. Also integrated
on board the part is a reference amplifier. The CRT control
functions,
BLANK
and
SYNC
, are integrated on board the
ADV7123.
DIGITAL INPUTS
There are 30 bits of pixel data (color information), R0 to R9, G0
to G9, and B0 to B9, latched into the device on the rising edge
of each clock cycle. This data is presented to the three 10-bit
DACs and then converted to three analog (RGB) output
waveforms (see Figure 22).
CLOCK
DIGITAL INPUTS
(R9 TO R0, G9 TO G0,
B9 TO B0,
SYNC, BLANK)
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG,
IOB, IOB)
Figure 22. Video Data Input/Output
The ADV7123 has two additional control signals that are latched
to the analog video outputs in a similar fashion.
SYNC
are each latched on the rising edge of CLOCK to maintain
synchronization with the pixel data stream.
The
BLANK
and
SYNC
functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK
and
SYNC
digital inputs. shows the analog
output, RGB video waveform of the ADV7123. The influence of
and
BLANK
on the analog video waveform is illustrated.
SYNC
RED AND BLUE
mA V
18.67 0.7
DATA
Figure 23
GREEN
mA V
26.0 0.975
BLANK
and
00215-022
Tabl e 9 details the resultant effect on the analog outputs of
BLANK
and
SYNC
.
All these digital inputs are specified to accept TTL logic levels.
CLOCK INPUT
The CLOCK input of the ADV7123 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and thus the required CLOCK frequency, is determined by the
on-screen resolution, according to the following equation:
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/
(Retrace Factor)
where:
Horiz Res is the number of pixels per line.
Ver t Re s is the number of lines per frame.
Refresh Rate is the horizontal scan rate. This is the rate at which
the screen must be refreshed, typically 60 Hz for a noninterlaced
system, or 30 Hz for an interlaced system.
Retrace Factor is the total blank time factor. This takes into
account that the display is blanked for a certain fraction of the
total duration of each frame (for example, 0.8).
Therefore, for a graphics system with a 1024 × 1024 resolution,
a noninterlaced 60 Hz refresh rate, and a retrace factor of 0.8,
Dot Rate = 1024 × 1024 × 60/0.8 = 78.6 MHz
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7123
on the rising edge of CLOCK, as described in the Digital Inputs
section. It is recommended that the CLOCK input to the
ADV7123 be driven by a TTL buffer (for example, 74F244).
WHITE LEVEL
00
NOTES
1. OUTPUT S CONNECTED TO A DOUBLY TERMI NATED 75Ω LOAD.
2. V
= 1.235V, R
REF
3. RS-343 LEV E LS AND TOLE RANCES ASSUMED ON ALL LEVELS .
7.2 0.271
00
= 530Ω.
SET
Figure 23. Typical RGB Video Output Waveform
Rev. D | Page 17 of 24
BLANK LEVEL
SYNC LEVEL
00215-023
Page 18
ADV7123
Table 9. Typical Video Output Truth Table (R
Video Output Level IOG (mA)
IOG
White Level 26.0 0 18.67 0 1 1 0x3FFH
Video Video + 7.2 18.67 − Video Video 18.67 − Video 1 1 Data
Video to BLANK
Video 18.67 − Video Video 18.67 − Video 0 1 Data
Black Level 7.2 18.67 0 18.67 1 1 0x000H
Black to BLANK
BLANK Level
SYNC Level
0 18.67 0 18.67 0 1 0x000H
7.2 18.67 0 18.67 1 0 0xXXXH (don’t care)
0 18.67 0 18.67 0 0 0xXXXH (don’t care)
VIDEO SYNCHRONIZATION AND CONTROL
The ADV7123 has a single composite sync (
control. Many graphics processors and CRT controllers have the
ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC), and composite
SYNC
.
In a graphics system that does not automatically generate a
composite
SYNC
signal, the inclusion of some additional logic
circuitry enables the generation of a composite
The sync current is internally connected directly to the IOG
output, thus encoding video synchronization information onto
the green video channel. If it is not required to encode sync
information onto the ADV7123, the
SYNC
to logic low.
REFERENCE INPUT
The ADV7123 contains an on-board voltage reference. The V
pin is normally terminated to V
through a 0.1 F capacitor.
AA
Alternatively, the part can, if required, be overdriven by an
external 1.23 V reference (AD1580).
A resistance, R
, connected between the R
SET
determines the amplitude of the output video level according to
Equation 1 and Equation 2 for the ADV7123.
IOG (mA) = 11,445 × V
IOR, IOB (mA) = 7989.6 × V
REF
(V)/R
REF
(Ω) (1)
SET
(V)/R
SET
Equation 1 applies to the ADV7123 only, when
SYNC
used. If
is not being encoded onto the green channel,
Equation 1 is similar to Equation 2.
Using a variable value of R
allows for accurate adjustment of
SET
the analog output video levels. Use of a fixed 560 R
yields the analog output levels quoted in the Specifications section.
These values typically correspond to the RS-343A video waveform values, as shown in Figure 23.
DACs
The ADV7123 contains three matched 10-bit DACs. The DACs
are designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each digital input are
routed to either the analog output (bit = 1) or GND (bit = 0)
by a sophisticated decoding scheme. Because all this circuitry is
on one monolithic device, matching between the three DACs is
optimized. As well as matching, the use of identical current
= 530 Ω, R
SET
(mA)
SYNC
SYNC
) input
IOR/IOB (mA)
signal.
input should be tied
REF
pin and GND,
SET
(Ω) (2)
SYNC
is being
resistor
SET
Rev. D | Page 18 of 24
= 37.5 Ω)
LOAD
IOR/IOB
(mA)
SYNC BLANK
DAC Input Data
sources in a monolithic design guarantees monotonicity and
low glitch. The on-board operational amplifier stabilizes the
full-scale output current against temperature and power supply
variations.
ANALOG OUTPUTS
The ADV7123 has three analog outputs, corresponding to the
red, green, and blue video signals.
The red, green, and blue analog outputs of the ADV7123 are
high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.5 load, such
as a doubly terminated 75 coaxial cable. Figure 24 shows
the required configuration for each of the three RGB outputs
connected into a doubly terminated 75 load. This arrangement
develops RS-343A video output voltage levels across a 75
monitor.
A suggested method of driving RS-170 video levels into a 75
monitor is shown in Figure 25. The output current levels of the
DACs remain unchanged, but the source termination resistance,
Z
, on each of the three DACs is increased from 75 to 150 .
S
IOR, IOG, IOB
DACs
= 75Ω
Z
S
(SOURCE
TERMINATION)
TERMINATION REPEATED THREE TIMES
FOR RED, GRE E N, AND BLUE DACs
Figure 24. Analog Output Termination for RS-343A
IOR, IOG, IOB
DACs
= 150Ω
Z
S
(SOURCE
TERMINATION)
TERMINATION REPEATED THREE TIMES
FOR RED, GRE E N, AND BLUE DACs
Figure 25. Analog Output Termination for RS-170
More detailed information regarding load terminations for
various output configurations, including RS-343A and RS-170,
is available in the AN-205 Application Note, Video Formats and
Required Load Terminations, available from Analog Devices, at
www.analog.com.
= 75Ω
Z
0
(CABLE)
= 75Ω
Z
0
(CABLE)
= 75Ω
Z
L
(MONITOR)
= 75Ω
Z
L
(MONITOR)
00215-024
00215-025
Page 19
ADV7123
Figure 23 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 load of Figure 24.
As well as the gray scale levels, black level to white level, Figure 23
also shows the contributions of
SYNC
and
BLANK
for the
ADV7123. These control inputs add appropriately weighted
currents to the analog outputs, producing the specific output
level requirements for video applications. details how
the
SYNC
and
BLANK
inputs modify the output levels.
Tabl e 9
GRAY SCALE OPERATION
The ADV7123 can be used for standalone, gray scale (monochrome), or composite video applications (that is, only one
channel used for video information). Any one of the three
channels, red, green, or blue, can be used to input the digital
video data. The two unused video data channels should be tied
to Logic 0. The unused analog outputs should be terminated
with the same load as that for the used channel; that is, if the
red channel is used and IOR is terminated with a doubly
terminated 75 load (37.5 ), IOB and IOG should be
terminated with 37.5 resistors (see Figure 26).
37.5Ω
37.5Ω
DOUBLY
TERMINATED
7.5Ω LOAD
0215-026
VIDEO
OUTPUT
Figure 26. Input and Output Connections for Standalone Gray Scale or
R0
R9
ADV7123
G0
G9
B0
B9
IOR
IOG
IOB
GND
Composite Video
VIDEO OUTPUT BUFFERS
The ADV7123 is specified to drive transmission line loads. The
analog output configuration to drive such loads is described in
the Analog Outputs section and illustrated in Figure 27. However,
in some applications it may be required to drive long transmission line cable lengths. Cable lengths greater than 10 meters can
attenuate and distort high frequency analog output pulses. The
inclusion of output buffers compensates for some cable distortion.
Buffers with large full power bandwidths and gains between
two and four are required. These buffers also need to be able to
supply sufficient current over the complete output voltage swing.
Analog Devices produces a range of suitable op amps for such
applications. These include the AD843, AD844, AD847, and
AD848 series of monolithic op amps. In very high frequency
applications (80 MHz), the AD8061 is recommended. More
information on line driver buffering circuits is given in the
relevant op amp data sheets.
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit results in any desired video level.
Z
2
IOR, IOG, IOB
DACs
= 75Ω
Z
S
(SOURCE
TERMINATION)
Z
1
+V
0.1µF
S
7
2
AD848
3
Figure 27. AD848 As an Output Buffer
6
0.1µF
4
–V
S
GAIN (G) = 1 +
75Ω
Z
= 75Ω
0
(CABLE)
Z
Z
ZL = 75Ω
(MONITOR)
1
2
PCB LAYOUT CONSIDERATIONS
The ADV7123 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7123, it is imperative
that great care be given to the PCB layout. Figure 28 shows a
recommended connection diagram for the ADV7123.
The layout should be optimized for lowest noise on the
ADV7123 power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling.
Shorten the lead length between groups of V
and GND pins
AA
to minimize inductive ringing.
It is recommended to use a 4-layer printed circuit board with a
single ground plane. The ground and power planes should
separate the signal trace layer and the solder side layer. Noise
on the analog power plane can be further reduced by using
multiple decoupling capacitors (see Figure 28). Optimum
performance is achieved by using 0.1 F and 0.01 F ceramic
capacitors. Individually decouple each V
pin to ground by
AA
placing the capacitors as close as possible to the device with the
capacitor leads as short as possible, thus minimizing lead
inductance. It is important to note that while the ADV7123
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) provides EMI
suppression between the switching power supply and the main
PCB. Alternatively, consideration can be given to using a 3terminal voltage regulator.
DIGITAL SIGNAL INTERCONNECT
Isolate the digital signal lines to the ADV7123 as much as
possible from the analog outputs and other analog circuitry.
Digital signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the
ADV7123 should be avoided to minimize noise pickup.
Connect any active pull-up termination resistors for the digital
inputs to the regular PCB power plane (V
power plane.
) and not the analog
CC
00215-027
Rev. D | Page 19 of 24
Page 20
ADV7123
G
ANALOG SIGNAL INTERCONNECT
Place the ADV7123 as close as possible to the output connectors, thus minimizing noise pickup and reflections due to
impedance mismatch.
The video output signals should overlay the ground plane and
not the analog power plane, thereby maximizing the high
frequency power supply rejection.
POWER SUPPLY DECOUPLIN
(0.1µF AND 0.01µF CAPACITOR
FOR EACH V
0.1µF
COMP V
35
R9 TO R0
1TO 10
G9 TO G0
B9 TO B0
VIDEO
DATA
INPUTS
V
AA
39 TO 48
14 TO 23
ADV7123
SYNC
12
BLANK
11
CLOCK
24
PSAVE
38
GND
13, 29,
30
AA
36
V
REF
AD1580
R
37
SET
IOR
IOG
IOB
IOR
IOG
IOB
25, 26
34
32
28
33
31
27
R
530Ω
75Ω 75Ω
COMPLEMENTARY
OUTPUTS
Figure 28. Typical Connection Diagram
0.1µF
SET
For optimum performance, the analog outputs should each
have a source termination resistance to ground of 75 (doubly
terminated 75 configuration). This termination resistance
should be as close as possible to the ADV7123 to minimize
reflections.
Additional information on PCB design is available in the
AN-333 Application Note, Design and Layout of a Video
Graphics System for Reduced EMI, which is available from
Analog Devices at www.analog.com.
GROUP)
AA
0.01µF
V
AA
V
AA
1
2
1kΩ
1µF
COAXIAL CABLE
75Ω
75Ω
CONNECTORS
BNC
75Ω
75Ω
75Ω
MONITOR (CRT)
00215-028
Rev. D | Page 20 of 24
Page 21
ADV7123
OUTLINE DIMENSIONS
9.20
1
12
0.50
BSC
48
13
9.00 SQ
8.80
PIN 1
TOP VIEW
(PINS DOWN)
37
24
0.27
0.22
0.17
36
7.20
7.00 SQ
6.80
25
051706-A
1.45
1.40
1.35
0.15
SEATING
0.05
PLANE
VIEW A
ROTATED 90° CCW
0.75
0.60
0.45
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
1.60
MAX
VIEW A
LEAD PITCH
Figure 29. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
1, 2
Model
ADV7123KSTZ50 −40°C to +85°C 50 MHz 48-Lead LQFP ST-48
ADV7123KSTZ140 −40°C to +85°C 140 MHz 48-Lead LQFP ST-48
ADV7123KST140-RL −40°C to +85°C 140 MHz 48-Lead LQFP ST-48
ADV7123JSTZ240 0°C to 70°C 240 MHz 48-Lead LQFP ST-48
ADV7123JSTZ240-RL 0°C to 70°C 240 MHz 48-Lead LQFP ST-48
ADV7123JSTZ330 0°C to 70°C 330 MHz 48-Lead LQFP ST-48
1
Z = RoHS Compliant Part.
2
ADV7123JSTZ330 is available in a 3.3 V version only.
Temperature Range Speed Option Package Description Package Option
Rev. D | Page 21 of 24
Page 22
ADV7123
NOTES
Rev. D | Page 22 of 24
Page 23
ADV7123
NOTES
Rev. D | Page 23 of 24
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ADV7123
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00215-0-7/10(D)
Rev. D | Page 24 of 24
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