Analog Devices ADV7120KST50, ADV7120KST30, ADV7120KP80, ADV7120KP50, ADV7120KP30 Datasheet

CMOS

REF WHITE

PIXEL

INPUT

PORT

IOR

IOG

IOB

R0
R7

CLOCK

8

SYNC

ADV7120

V

REF

GND

G0
G7

8

B0
B7

8

BLANK

FS

ADJUST

8

8

8

I

SYNC

V

AA

REFERENCE
AMPLIFIER

COMP

DAC

CONTROL
REGISTER

SYNC

CONTROL

RED

REGISTER

GREEN

REGISTER

BLUE

REGISTER

DAC

DAC

a

FEATURES
80 MHz Pipelined Operation
Triple 8-Bit D/A Converters
RS-343A/RS-170 Compatible Outputs
TTL Compatible Inputs
+5 V CMOS Monolithic Construction
40-Pin DIP or 44-Pin PLCC and 48-Lead TQFP

APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Video Signal Reconstruction
Desktop Publishing
Direct Digital Synthesis (DDS) and I/Q Modulation

SPEED GRADES*
80 MHz
50 MHz
30 MHz

80 MHz, Triple 8-Bit Video DAC

ADV7120

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The ADV7120 (ADV) is a digital to analog video converter on
a single monolithic chip. The part is specifically designed for
high resolution color graphics and video systems. It is also ideal
for any high speed communications type applications requiring
low cost, high speed DACs. It consists of three, high speed,
8-bit, video D/A converters (RGB); a standard TTL input inter­face and high impedance, analog output, current sources.

The ADV7120 has three separate, 8-bit, pixel input ports, one
each for red, green and blue video data. Additional video input
controls on the part include composite sync, blank and refer­ence white. A single +5 V supply, an external 1.23 V reference
and pixel clock input are all that are required to make the part
operational.

The ADV7120 is capable of generating RGB video output sig­nals, which are compatible with RS-343A and RS-170 video
standards, without requiring external buffering.

The ADV7120 is fabricated in a +5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with low power dissipation. The part is packaged in both a 0.6",
40-pin plastic DIP and a 44-pin plastic leaded (J-lead) chip car­rier, PLCC. The ADV7120 is also available in a very small 48­lead Thin Quad Flatpack (TQFP).

ADV is a registered trademark of Analog Devices, Inc.

*Speed grades up to 140 MHz are also available upon special request.

Please contact Analog Devices or its representatives for further details.

PRODUCT HIGHLIGHTS

1. Fast video refresh rate, 80 MHz.

2. Compatible with a wide variety of high resolution color
graphics video systems.

3. Guaranteed monotonic with a maximum differential non­linearity of ±0.5 LSB. Integral nonlinearity is guaranteed to
be a maximum of ±1 LSB.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

ADV7120–SPECIFICATIONS

(VAA = +5 V 6 5%; V
I

connected to I0G. All Specifications T

SYNC

= +1.235 V; RL = 37.5 V, CL = 10 pF; R

REF

MIN

1

to T

unless otherwise noted.)

MAX

= 560 V.

SET

Parameter All Versions Units Test Conditions/Comments

STATIC PERFORMANCE

Resolution (Each DAC) 8 Bits
Accuracy (Each DAC)

Integral Nonlinearity, INL ±1 LSB max
Differential Nonlinearity, DNL ±0.5 LSB max Guaranteed Monotonic
Gray Scale Error ±5 % Gray Scale max Max Gray Scale Current: IOG = (V

IOR, IOB = (V

* 12,082/R

REF

REF

* 8,627/R

SET

) mA

) mA

SET

Coding Binary

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

2

2 V min

0.8 V max
±1 µA max VIN = 0.4 V or 2.4 V
10 pF max

ANALOG OUTPUTS

Gray Scale Current Range 15 mA min

22 mA max

Output Current

White Level Relative to Blank 17.69 mA min Typically 19.05 mA

20.40 mA max

White Level Relative to Black 16.74 mA min Typically 17.62 mA

18.50 mA max

Black Level Relative to Blank 0.95 mA min Typically 1.44 mA

1.90 mA max

Blank Level on IOR, IOB 0 µA min Typically 5 µA

50 µA max

Blank Level on IOG 6.29 mA min Typically 7.62 mA

9.5 mA max

Sync Level on IOG 0 µA min Typically 5 µA

50 µA max

LSB Size 69.1 µA typ
DAC to DAC Matching 5 % max Typically 2%
Output Compliance, V

Output Impedance, R

OC

OUT

Output Capacitance, C

OUT

2

2

–1 V min
+1.4 V max
100 kΩ typ
30 pF max I

OUT

= 0 mA

VOLTAGE REFERENCE

Voltage Reference Range, V
Input Current, I

VREF

REF

1.14/1.26 V min/V max V
–5 mA typ

= 1.235 V for Specified Performance

REF

POWER REQUIREMENTS

V

AA

I

AA

5 V nom
125 mA max Typically 80 mA: 80 MHz Parts

100 mA max Typically 70 mA: 50 MHz & 35 MHz Parts
Power Supply Rejection Ratio 0.5 %/% max Typically 0.12%/%: f = 1 kHz, COMP = 0.1 µF
Power Dissipation 625 mW max Typically 400 mW: 80 MHz Parts

500 mW max Typically 350 mW: 50 MHz & 30 MHz Parts

DYNAMIC PERFORMANCE

Glitch Impulse
DAC Noise

2, 3, 4

2, 3

50 pV secs typ

200 pV secs typ
Analog Output Skew 2 ns max Typically 1 ns

NOTES

1

Temperature range (T

2

Sample tested at +25°C to ensure compliance.

3

TTL input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and

outputs. See timing notes in Figure 1.

4

This includes effects due to clock and data feedthrough as well as RGB analog crosstalk.

Specifications subject to change without notice.

MIN

to T

MIN

); 0°C to +70°C.

–2–

REV. B

ADV7120

TIMING CHARACTERISTICS

(VAA = +5 V 6 5%; V

1

I

connected to IOG. All Specifications T

SYNC

= +1.235 V; RL = 37.5 V, CL = 10 pF; R

REF

MIN

2

to T

unless otherwise noted.)

MAX

= 560 V.

SET

Parameter 80 MHz Version 50 MHz Version 30 MHz Version Units Conditions/Comments

f

MAX

t

l

t

2

t

3

t

4

t

5

t

6

80 50 30 MHz max Clock Rate
3 6 8 ns min Data & Control Setup Time
2 2 2 ns min Data & Control Hold Time

12.5 20 33.3 ns min Clock Cycle Time
4 7 9 ns min Clock Pulse Width High Time
4 7 9 ns min Clock Pulse Width Low Time
30 30 30 ns max Analog Output Delay
20 20 20 ns typ

t

7

3

t

8

NOTES

1

TTL input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs
and outputs. See timing notes in Figure 1.

2

Temperature range (T

3

Sample tested at +25°C to ensure compliance.

Specifications subject to change without notice.

3 3 3 ns max Analog Output Rise/Fall Time
12 15 15 ns typ Analog Output Transition Time

to T

MIN

): 0°C to +70°C

MAX

CLOCK

DIGITAL INPUTS

(R0-R7, G0-G7, B0-B7;

SYNC, BLANK,

REF WHITE)

t

t

4

5

1

DATA

t

2

t

t

8

6

t

3

t

ANALOG OUTPUTS

(IOR, IOG, IOB, I

)

SYNC

NOTES

1. OUTPUT DELAY (
CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.

2. TRANSITION TIME (
TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.

3. OUTPUT RISE/FALL TIME (
OF FULL TRANSITION.

t

) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF

6

t

) MEASURED FROM THE 50% POINT OF FULL-SCALE

8

t

) MEASURED BETWEEN THE 10% AND 90% POINTS

7

Figure 1. Video Input/Output Timing

t

7

REV. B

–3–

ADV7120

IOR
IOG

V

AA

IOB

CLOCK

V

AA

G0
G1

G4
G5
G6

G2
G3

R7

R6

R3

R2

R1

R5

B0

B1

B4

B5

B6

B2

B3

R4

FS ADJUST

V

REF

COMP

NC

GND

B7

R0

GND
GND

GND

GND

V

AA

G7

44

2

6

4
5

18

1

35
34
33

37

36

3

7
8

11
12

13

9

10

203921 242322

38

404142

25

28
27
26

43

31
30
29

32

15 16 1714

TOP VIEW

(Not to Scale)

ADV7120

BLANK

SYNC

48 47 46 45

19

GND

GND

NC

NC

GND

NC

NC = NO CONNECT

RECOMMENDED OPERATING CONDITIONS

ORDERING GUIDE

Parameter Symbol Min Typ Max Units

Power Supply V

AA

4.75 5.00 5.25 Volts

Ambient Operating

Temperature T
Output Load R
Reference Voltage V

A
L
REF

ABSOLUTE MAXIMUM RATINGS

0 +70 °C

37.5 Ω

1.14 1.235 1.26 Volts

1

VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V

Voltage on Any Digital Pin . . . . . GND –0.5 V to V

Ambient Operating Temperature (T
Storage Temperature (T
Junction Temperature (T

) . . . . . . . . . . . . . . –65°C to +150°C

S

) . . . . . . . . . . . . . . . . . . . . +150°C

J

) . . . . . . . . 0°C to +70°C

A

+0.5 V

AA

Soldering Temperature (10 secs) . . . . . . . . . . . . . . . . . .300°C

Model Speed Range

ADV7120KN80 80 MHz 0°C to +70°C N-40A
ADV7120KN50 50 MHz 0°C to +70°C N-40A
ADV7120KN30 30 MHz 0°C to +70°C N-40A
ADV7120KP80 80 MHz 0°C to +70°C P-44A
ADV7120KP50 50 MHz 0°C to +70°C P-44A
ADV7120KP30 30 MHz 0°C to +70°C P-44A
ADV7120KST50 50 MHz 0°C to +70°C ST-48
ADV7120KST30 30 MHz 0°C to +70°C ST-48

NOTES

1

Industrial temperature range (–40°C to +85°C) version available to special
request. Please consult your local Analog Device representative.

2

N = Plastic DIP; P = Plastic Leaded Chip Carrier.

Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . .220°C

IOR, IOB, IOG, I

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.

to GND2 . . . . . . . . . . . . . . 0 V to V

SYNC

AA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7120 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

Temperature Package

1

Option

WARNING!

ESD SENSITIVE DEVICE

2

R5

R6

B2

B1

PLCC

R4

3

2645

ADV7120

TOP VIEW

(Not to Scale)

21 24

22182019

B3

DIP

R4

1

R5

2

R6

3

R7

4

G0

5

G1

6

G2

7
833

G3 IOR

932

G4 IOG

ADV7120

10 31

G5 I

TOP VIEW

G6 V

1111

(Not to Scale)

G7 IOB

BLANK

SYNC

V

AA

B0 CLOCK
B1 REF WHITE
B2 B7
B3
B4 B5

NOTE
For the ADV7120 in TQFP package: The REF WHITE pin is not available.
The I

12 29
13
14 27
15 26
16 25
17 24
18 23
19
20 21

pin is not available and is internally connected to the IOG pin.

SYNC

40
39
38
37
36
35
34

30

28

22

R3
R2
R1
R0
FS ADJUST
V

REF

COMP

SYNC

AA

GND
GND
GND

B6

R7

7

G0

8

G1
G2

9

10

G3

11

G4

12

G5

13

G6

14

G7

15

BLANK

SYNC

V

16
17

AA

B0

PIN CONFIGURATIONS

REF

R2

R3

R1

1

44

23

B5

B4

B6

V

R0

FS ADJUST

41

42

43

25 28

26

27

B7

CLOCK

REF WHITE

40

COMP

GND

39

IOR

38

IOG

37

I

SYNC

36

V

AA

35

V

AA

34

V

AA

33

IOB

32

GND

31

GND

30

GND

29

GND

–4–

TQFP

REV. B

ADV7120

PIN FUNCTION DESCRIPTION

Pin
Mnemonic Function

BLANK Composite blank control input (TTL compatible). A logic zero on this control input drives the analog out-

puts, IOR, IOB and IOG, to the blanking level. The
While

BLANK is a logical zero, the R0–R7, G0–G7, R0–R7 and REF WHITE pixel and control inputs are

ignored.

SYNC Composite sync control input (TTL compatible). A logical zero on the SYNC input switches off a 40 IRE

current source on the I

output. SYNC does not override any other control or data input; therefore, it

SYNC

should only be asserted during the blanking interval.

BLANK signal is latched on the rising edge of CLOCK.

SYNC is latched on the rising edge of CLOCK.

CLOCK Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7,

SYNC,

BLANK and REF WHITE pixel and control inputs. It is typically the pixel clock rate of the video system.

CLOCK should be driven by a dedicated TTL buffer.

REF WHITE Reference white control input (TTL compatible). A logical one on this input forces the IOR, IOG and IOB

outputs to the white level, regardless of the pixel input data (R0–R7, G0–G7 and B0–B7). REF WHITE is
latched on the rising edge of clock.

R0–R7, Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK.
G0–G7, R0, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
B0–B7 regular PCB power or ground plane.

IOR, IOG, IOB Red, green, and blue current outputs. These high impedance current sources are capable of directly driving

a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether
or not they are all being used.

I

SYNC

FS ADJUST Full-scale adjust control. A resistor (R

Sync current output. This high impedance current source can be directly connected to the IOG output. This
allows sync information to be encoded onto the green channel. I
SYNC is at logical zero. The amount of current output at I

(mA) = 3,455 × V

I

SYNC

If sync information is not required on the green channel, I

) connected between this pin and GND, controls the magnitude of

SET

REF

SYNC

(V)/ R

SYNC

does not output any current while

SYNC

while SYNC is at logical one is given by:

(Ω)

SET

should be connected to AGND.

the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output
current.

The relationship between R

and the full-scale output current on IOG (assuming I

SET

is connected to

SYNC

IOG) is given by:

The relationship between R

SET

(Ω) = 12,082 × V

R

SET

and the full-scale output current on IOR and IOB is given by:

IOR, IOB (mA) = 8,628

(V)/IOG (mA)

REF

×

V

(V)/ R

REF

SET

(Ω)

COMP Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capaci-

tor must be connected between COMP and V

V

REF

Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. The use of an ex-

AA

.

ternal resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be con-
nected between V

V

AA

Analog power supply (5 V ± 5%). All VAA pins on the ADV7120 must be connected.

and VAA.

REF

GND Ground. All GND pins must be connected.

REV. B

–5–

ADV7120

TERMINOLOGY
Blanking Level

The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the pic­ture tube, resulting in the blackest possible picture.

Color Video (RGB)

This usually refers to the technique of combining the three pri­mary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.

Sync Signal (SYNC)

The position of the composite video signal which synchronizes
the scanning process.

Gray Scale

The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different lev­els while a 6-bit DAC contains 64.

CIRCUIT DESCRIPTION AND OPERATION

The ADV7120 contains three 8-bit D/A converters, with three
input channels each containing an 8-bit register. Also inte­grated on board the part is a reference amplifier and CRT con­trol functions

Digital Inputs

BLANK, SYNC and REF WHITE.

24-bits of pixel data (color information) R0–R7, G0–G7 and
B0–B7 are latched into the device on the rising edge of each
clock cycle. This data is presented to the three 8-bit DACs and
is then converted to three analog (RGB) output waveforms.
(See Figure 2.)

Three other digital control signals are latched to the analog
video outputs in a similar fashion.

BLANK, SYNC and REF
WHITE are each latched on the rising edge of CLOCK to
maintain synchronization with the pixel data stream.

The

BLANK and SYNC functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK and SYNC digital inputs. Figure 3 shows the analog
output, RGB video waveform of the ADV7120. The influence
of

SYNC and BLANK on the analog video waveform is

illustrated.

Raster Scan

The most basic method of sweeping a CRT one line at a time to
generate and display images.

Reference Black Level

The maximum negative polarity amplitude of the video signal.

Reference White Level

The maximum positive polarity amplitude of the video signal.

Sync Level

The peak level of the SYNC signal.

Video Signal

That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may be
visually observed.

The REF WHITE control input drives the RGB video outputs
to the white level. This function could be used to overlay a cur­sor or crosshair onto the RGB video output.

Table I details the resultant effect on the analog outputs of
BLANK, SYNC and REF WHITE.

All these digital inputs are specified to accept TTL logic levels.

Clock Input

The CLOCK input of the ADV7120 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and hence the required CLOCK frequency, will be determined
by the on-screen resolution, according to the following
equation:

Dot Rate = (Horiz: Res)

×

(Vert Res) × (Refresh Rate)/

(Retrace Factor)
Horiz Res = Number of pixels/line
Vert Res = Number of lines/frame
Refresh Rate = Horizontal scan rate. This is the rate at

which the screen must be refreshed, typi­cally 60 Hz for a noninterlaced system or
30 Hz for an interlaced system.

Retrace Factor = Total blank time factor. This takes into ac-

count that the display is blanked for a cer­tain fraction of the total duration of each
frame (e.g., 0.8).

CLOCK

DIGITAL INPUTS

(R0-R7, G0-G7, B0-B7;

SYNC, BLANK,

REF WHITE)

ANALOG OUTPUTS

(IOR, IOG, IOB, I

SYNC

DATA

)

Figure 2. Video Data Input/Output

–6–

REV. B

ADV7120

If we, therefore, have a graphics system with a 1024 × 1024
resolution, a noninterlaced 60 Hz refresh rate and a retrace fac­tor of 0.8, then:

Dot Rate = 1024 × 1024 × 60/0.8

= 78.6 MHz

RED, BLUE GREEN

mA V mA V

19.05 0.714 26.67 1.000

92.5 IRE

1.44 0.054 9.05 0.340

0 0 7.62 0.286

00

NOTES

1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD.

= 1.235V, R

2. V

REF

3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.

SET

= 560Ω, I

CONNECTED TO IOG.

SYNC

7.5 IRE

40 IRE

The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7120

on the rising edge of CLOCK, as previously described in the
“Digital Inputs” section. It is recommended that the CLOCK
input to the ADV7120 be driven by a TTL buffer (e.g.,
74F244).

WHITE LEVEL

BLACK LEVEL

BLANK LEVEL

SYNC LEVEL

Figure 3. RGB Video Output Waveform

Table I. Video Output Truth Table

IOG IOR, IOB REF DAC

Description (mA)

l

(mA) WHITE SYNC BLANK Input Data

WHITE LEVEL 26.67 19.05 1 1 1 xxH
WHITE LEVEL 26.67 19.05 0 1 1 FFH
VIDEO video + 9.05 video + 1.44 0 1 1 data
VIDEO to BLANK video + 1.44 video + 1.44 0 0 1 data
BLACK LEVEL 9.05 1.44 0 1 1 00H
BLACK to BLANK 1.44 1.44 0 0 1 00H
BLANK LEVEL 7.62 0 0 1 0 xxH
SYNC LEVEL 0 0 0 0 0 xxH

NOTE
Typical with full-scale IOG = 26.67 mA.
V

= 1.235 V, R

REF

= 560 Ω, I

SET

connected to IOG.

SYNC

Video Synchronization and Control

The ADV7120 has a single composite video sync (SYNC) input
control. Many graphics processors and CRT controllers have
the ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC) and composite

SYNC.

In a graphics system which does not automatically generate a
composite
circuitry will enable the generation of a composite

The I

SYNC signal, the inclusion of some additional logic

SYNC signal.

current output is typically connected directly to the

SYNC

IOG output, thus encoding video synchronization information
onto the green video channel. If it is not required to encode sync
information onto the ADV7120’s analog outputs, the
put should be tied to logic low and the I

should be con-

SYNC

SYNC in-

nected to analog ground.

Reference Input

An external 1.23 V voltage reference is required to drive
the ADV7120. The AD589 from Analog Devices is an
ideal choice of reference. It is a two-terminal, low cost,
temperature compensated bandgap voltage reference which
provides a fixed 1.23 V output voltage for input currents
between 50 µA and 5 mA. Figure 4 shows a typical refer-
ence circuit connection diagram. The voltage reference gets
its current drive from the ADV7120’s V
board 1 kΩ resistor to the V

pin. A 0.1 µF ceramic ca-

REF

pacitor is required between the COMP pin and V

through an on-

AA

AA

.
This is necessary so as to provide compensation for the
internal reference amplifier.

REV. B

–7–

ADV7120

TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs

DACs

IOR, IOG, IOB

(CABLE)

ZO = 75Ω

Z

S

= 75Ω

(SOURCE

TERMINATION)

ZL = 75Ω
(MONITOR)

A resistance R

connected between FS ADJUST and GND

SET

determines the amplitude of the output video level according to
the following equations:

IOG (mA) = 12,082
IOR, IOB (mA) = 8,628

SYNC is not being encoded onto the green channel, then

If

×

V

REF

×

(V)/R

V

REF

(Ω) (1)

SET

(V)/R

(Ω) (2)

SET

Equation 1 will be similar to Equation 2.
Using a variable value of R

, as shown in Figure 4, allows for

SET

accurate adjustment of the analog output video levels. Use of a
fixed 560 Ω R

resistor yields the analog output levels as

SET

quoted in the specification page. These values also correspond
to the RS-343A video waveform values as shown in Figure 3.

ANALOG POWER PLANE

+

AA

REF

FS ADJUST

R

SET

560Ω

GND

5V

I

≈ 4mA

REF

AD589

500Ω

100Ω

(1.235V
VOLTAGE
REFERENCE)

COMP

TO DACs

ADV7120*

0.1µF

V

1kΩ

V

as a doubly terminated 75 Ω coaxial cable. Figure 5a shows the
required configuration for each of the three RGB outputs con­nected into a doubly terminated 75 Ω load. This arrangement
will develop RS-343A video output voltage levels across a 75 Ω
monitor.

Figure 5a. Analog Output Termination for RS-343A

One suggested method of driving RS-170 video levels into a 75 Ω
monitor is shown in Figure 5b. The output current levels of the
DACs remain unchanged but the source termination resistance,
Z

, on each of the three DACs is increased from 75 Ω to 150 Ω.

S

DACs

Z

= 150Ω

S

(SOURCE

TERMINATION)

IOR, IOG, IOB

ZO = 75Ω

(CABLE)

= 75Ω

Z

L

(MONITOR)

*ADDITIONAL CIRCUITRY, INCLUDING
DECOUPLING COMPONENTS,
EXCLUDED FOR CLARITY

Figure 4. Reference Circuit

D/A Converters

The ADV7120 contains three matched 8-bit D/A converters.
The DACs are designed using an advanced, high speed, seg­mented architecture. The bit currents corresponding to each
digital input are routed to either the analog output (bit = “1”)
or GND (bit = “0”) by a sophisticated decoding scheme. As all
this circuitry is on one monolithic device, matching between the
three DACs is optimized. As well as matching, the use of identi­cal current sources in a monolithic design guarantees monoto­nicity and low glitch. The onboard operational amplifier
stabilizes the full-scale output current against temperature and
power supply variations.

Analog Outputs

The ADV7120 has three analog outputs, corresponding to the red,
green and blue video signals. A fourth analog output (I

SYNC

used if it is required to encode video synchronization information
onto the green signal. In this case, I

is connected to IOG .

SYNC

(See “Video Synchronization and Control” section.)
The red, green and blue analog outputs of the ADV7102 are

high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.5 Ω load, such

) can be

TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs

Figure 5b. Analog Output Termination for RS-170

More detailed information regarding load terminations for vari­ous output configurations, including RS-343A and RS-170, is
available in an application note entitled “Video Formats & Re­quired Load Terminations” available from Analog Devices,
publication number E1228-15-1/89.

Figure 3 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 Ω load of Figure
5a. As well as the gray scale levels, black level to white level, the
diagram also shows the contributions of

SYNC and BLANK.
These control inputs add appropriately weighted currents to the
analog outputs, producing the specific output level requirements
for video applications. Table I details how the

SYNC and

BLANK inputs modify the output levels.

Gray Scale Operation

The ADV7120 can be used for stand-alone, gray scale (mono­chrome) or composite video applications (i.e., only one channel
used for video information). Any one of the three channels, red,
green or blue, can be used to input the digital video data. The
two unused video data channels should be tied to logical zero.

–8–

REV. B

ADV7120

The unused analog outputs should be terminated with the same
load as that for the used channel. In other words, if the red
channel is used and IOR is terminated with a doubly terminated
75 Ω load (37.5 Ω), IOB and IOG should be terminated with

37.5 Ω resistors. (See Figure 6.)

37.5Ω

DOUBLY
TERMINATED
75Ω LOAD

VIDEO

INPUT

R0

R7

G0

G7

B0

B7

IOR

IOG

37.5Ω

IOB

ADV7120

GND

Figure 6. Input and Output Connections for Stand-Alone
Gray Scale or Composite Video

Z

2

Z

1

+V

S

0.1µF

Video Output Buffers

The ADV7120 is specified to drive transmission line loads,
which is what most monitors are rated as. The analog output
configurations to drive such loads are described in the Analog
Interface section and illustrated in Figure 5. However, in some
applications it may be required to drive long “transmission line”
cable lengths. Cable lengths greater than 10 meters can attenu­ate and distort high frequency analog output pulses. The inclu­sion of output buffers will compensate for some cable distortion.
Buffers with large full power bandwidths and gains between 2
and 4 will be required.

These buffers will also need to be able to supply sufficient cur­rent over the complete output voltage swing. Analog Devices
produces a range of suitable op amps for such applications.
These include the AD84X series of monolithic op amps. In very
high frequency applications (80 MHz), the AD9617 is recom­mended. More information on line driver buffering circuits is
given in the relevant op amp data sheets.

Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit will result in any desired
video level.

IOR, IOG, IOB

DACs

(SOURCE

TERMINATION)

Z

= 75Ω

S

2

3

AD848

4

–V

7

0.1µF

S

75Ω

6

GAIN (G) = 1 +

ZO = 75Ω

(CABLE)

Z

1

Z

2

Figure 7. AD848 As an Output Buffer

= 75Ω

Z

L

(MONITOR)

REV. B

–9–

ADV7120

PC BOARD LAYOUT CONSIDERATIONS

The ADV7120 is optimally designed for lowest noise perfor­mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7120, it is imperative
that great care be given to the PC board layout. Figure 8 shows
a recommended connection diagram for the ADV7120.

The layout should be optimized for lowest noise on the
ADV7120 power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling. The
lead length between groups of V

and GND pins should by

AA

minimized so as to minimize inductive ringing.

COMP

C6

R

SET

560Ω

0.1µF

ANALOG POWER PLANE

C3

0.1µF

R1

75ΩR275Ω

C4

0.1µF

VIDEO

DATA

INPUTS

R0
R7

G0
G7

B0
B7

ADV7120

V

V

REF

GND

AA

Ground Planes

The ADV7120 and associated analog circuitry, should have a
separate ground plane referred to as the analog ground plane.
This ground plane should connect to the regular PCB ground
plane at a single point through a ferrite bead, as illustrated in
Figure 8. This bead should be located as close as possible
(within 3 inches) to the ADV7120.

The analog ground plane should encompass all ADV7120
ground pins, voltage reference circuitry, power supply bypass
circuitry, the analog output traces and any output amplifiers.

The regular PCB ground plane area should encompass all the
digital signal traces, excluding the ground pins, leading up to
the ADV7120.

C5

0.1µF

Z1 (AD589)

ANALOG GROUND PLANE

R3

75Ω

L1 (FERRITE BEAD)

C2
10µF

L2 (FERRITE BEAD)

C1
33µF

+5V (VCC)

GROUND

VIDEO

CONTROL

INPUTS

CLOCK

REF WHITE

SYNC

BLANK

COMPONENT

FS ADJUST

C3, C4, C5, C6

L1, L2

R1, R2, R3

Rset

SET

SET

IOR

IOG

I

SYNC

IOB

DESCRIPTION

C1

33µF TANTALUM CAPACITOR

C2

10µF TANTALUM CAPACITOR

0.1µF CERAMIC CAPACITOR
FERRITE BEAD
75Ω 1% METAL FILM RESISTOR
560Ω 1% METAL FILM RESISTOR

Z1

1.235V VOLTAGE REFERENCE

VENDOR PART NUMBER

FAIR-RITE 274300111 OR MURATA BL01/02/03
DALE CMF-55C
DALE CMF-55C
ANALOG DEVICES AD589JH

Figure 8. ADV7120 Typical Connection Diagram and Component List

RGB
VIDEO
OUTPUT

–10–

REV. B

ADV7120

Power Planes

The PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. The analog
power plane should encompass the ADV7120 (V

) and all as-

AA

sociated analog circuitry. This power plane should be connected
to the regular PCB power plane (V

) at a single point through

CC

a ferrite bead, as illustrated in Figure 8. This bead should be lo­cated within three inches of the ADV7120.

The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7120 power pins, voltage reference circuitry
and any output amplifiers.

The PCB power and ground planes should not overlay portions
of the analog power plane. Keeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.

Supply Decoupling

Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors. (See Figure 8.)

Optimum performance is achieved by the use of 0.1 µF ceramic
capacitors. Each of the two groups of V

should be individually

AA

decoupled to ground. This should be done by placing the ca­pacitors as close as possible to the device with the capacitor
leads as short as possible, thus minimizing lead inductance.

It is important to note that while the ADV7120 contains cir­cuitry to reject power supply noise, this rejection decreases with
frequency. If a high frequency switching power supply is used,
the designer should pay close attention to reducing power sup­ply noise. A dc power supply filter (Murata BNX002) will pro­vide EMI suppression between the switching power supply and

the main PCB. Alternatively, consideration could be given to
using a three terminal voltage regulator.

Digital Signal Interconnect

The digital signal lines to the ADV7120 should be isolated as
much as possible from the analog outputs and other analog cir­cuitry. Digital signal lines should not overlay the analog power
plane.

Due to the high clock rates used, long clock lines to the
ADV7120 should be avoided so as to minimize noise pickup.

Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (V

CC

), and

not the analog power plane.

Analog Signal Interconnect

The ADV7120 should be located as close as possible to the out­put connectors thus minimizing noise pickup and reflections
due to impedance mismatch.

The video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high fre­quency power supply rejection.

For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75 Ω (doubly ter­minated 75 Ω configuration). This termination resistance should
be as close as possible to the ADV7120 so as to minimize
reflections.

Additional information on PCB design is available in an applica­tion note entitled “Design and Layout of a Video Graphics Sys­tem for Reduced EMI.” This application note is available from
Analog Devices, publication number E1309-15-10/89.

REV. B

–11–

ADV7120

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

44-Terminal Plastic Leaded Chip Carrier

(P-44A)

0.17

(4.32)

MAX

0.045
TYP

40

0.045 TYP

6

7

17

18

PIN 1

IDENTIFIER

TOP VIEW

(PINS DOWN)

0.656 (16.662)

0.650 (16.510)

0.695 (17.65)

0.685 (17.40)

1

0.021 (0.533)

0.015 (0.381)

LEAD NO. 1 IDENTIFIED BY DOT, NOTCH OR "1."
LEADS ARE SOLDER PLATED KOVAR OR ALLOY 42.

2.090 (53.0)

2.008 (51.0)

0.105 (2.67)

0.095 (2.42)

SQ

40

39

0.045
TYP

29

28

SQ

R.020 MAX

3 PLCS

40-Pin Plastic DIP

(N-40A)

0.052 (1.32)

0.048 (1.219)

0.045 TYP

21

0.545 (13.843)

0.535 (13.589)

20

0.175 (4.45)

0.125 (3.18)

0.050 ± 0.005
(1.27 ± 0.13)

0.021 (0.533)

0.013 (0.331)

0.032 (0.812)

0.026 (0.661)

0.020 MIN

0.120 (3.04)

0.090 (2.29)

0.180 (4.57)

0.165 (4.20)

0.630 (16.0)

0.590 (15.0)

0.012 (0.305)

0.008 (0.203)

15

°

0

°

0.630 (16.00)

0.590 (14.99)

0.155 (3.937)

0.145 (3.683)

C1379–24–4/90

0.059 +0.008 –0.004
(1.50 +0.2 –0.1)

0.02 ± 0.008
(0.5 ± 0.02)

SEATING

PLANE

0.004 ± 0.002
(0.1 ± 0.05)

(3.5° ± 3.5

°)

0.005 +0.002 –0.0008
(0.127 +0.05 –0.02)

48-Lead TQFP

(ST-48)

0.055 ± 0.002
(1.40 ± 0.05)

0° MIN

–12–

0.354 ± 0.008
(9.00 ± 0.2)

0.276 ± 0.004

48

1

TOP VIEW

(PINS DOWN)

12

13

0.02 ± 0.003

(0.50 ± 0.08)

(7.0 ± 0.1)

0.007 ± 0.003 –0.001
(0.18 ± 0.08 –0.03)

37

36

(7.0 ± 0.1)

(9.00 ± 0.2)

0.276 ± 0.004

0.354 ± 0.008

25

24

PRINTED IN U.S.A.

REV. B