ANALOG DEVICES ADV3228, ADV3229 Service Manual

750 MHz, 8 × 8 Analog Crosspoint

FEATURES

8 × 8 high speed, nonblocking switch array
Pinout and functionally equivalent to the AD8108/AD8109
Drop-in compatible with ADV3224/ADV3225 16 × 8 array
Complete solution

Buffered inputs
Programmable high impedance outputs
8 output amplifiers, G = +1 (ADV3228), G = +2 (ADV3229)

Drives 150 Ω loads
Operates on ±5 V supplies
Low power: 0.5 W
Excellent ac performance

−3 dB bandwidth
200 mV p-p: 1200 MHz (ADV3228), 900 MHz (ADV3229)
2 V p-p: 750 MHz (ADV3228), 850 MHz (ADV3229)

0.5 dB flatness (2 V p-p): 250 MHz (ADV3228), 235 MHz
(ADV3229)

Slew rate: 2500 V/μs
Serial or parallel programming of switch array
72-lead LFCSP (10 mm × 10 mm)

APPLICATIONS

Routing of high speed signals including

Video (NTSC, PAL, S, SECAM, YUV, RGB)

Compressed video (MPEG, wavelet)

3-level digital video (HDB3)
Data communications
Telecommunications

CLK

DATAIN

UPDATE

RESET

8

ADV3228/ADV3229

FUNCTIONAL BLOCK DIAGRAM

CE

INPUTS

SER/PAR

ADV3228/
ADV3229

D0 D1 D2 D3

40-BIT SHIFT REGISTER

WITH 4-BIT

PARALLEL LOADING

32 8

PARALLEL LATCH

32

DECODE

8 × 4:8 DECODERS

OUTPUT
BUFFER

64

SWITCH

Figure 1.

(RESERVED)

SET INDIVIDUAL

OR RESET ALL

OUTPUTS TO OFF

8

G = +1,

G = +2

Switch

A0
A1
A2

DATAOUT

8

ENABLED/DISABLED

OUTPUTS

09318-001

GENERAL DESCRIPTION

The ADV3228/ADV3229 are high speed 8 × 8 analog crosspoint
switch matrices. They offer a −3 dB large signal bandwidth of
750 MHz (ADV3228) and a slew rate of 2500 V/µs.

The ADV3228/ADV3229 include eight independent output buffers
that can be placed into a high impedance state for paralleling
crosspoint outputs to prevent off channels from loading the output
bus. The ADV3228 has a gain of +1, the ADV3229 has a gain of
+2, and they both operate on voltage supplies of ±5 V. Channel

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

switching is performed via a serial digital control that can
accommodate daisy chaining of several devices or via a parallel
control to allow updating of an individual output without
reprogramming the entire array.

The ADV3228/ADV3229 are available in the 72-lead LFCSP
package over the extended industrial temperature range of

−40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

ADV3228/ADV3229

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics (Serial) .................................................. 5

Logic Levels ................................................................................... 5

Timing Characteristics (Parallel) ............................................... 6

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

Power Dissipation ......................................................................... 7

ESD Caution .................................................................................. 7

REVISION HISTORY

11/10—Revision 0: Initial Version

Pin Configuration and Function Descriptions ..............................8

Truth Table and Logic Diagram ............................................... 10

Typical Performance Characteristics ........................................... 11

Circuit Diagrams ............................................................................ 20

Theory of Operation ...................................................................... 21

Applications Information .............................................................. 22

Serial Programming ................................................................... 22

Parallel Programming ................................................................ 22

Power-On Reset .......................................................................... 23

Gain Selection ............................................................................. 23

Creating Larger Crosspoint Arrays .......................................... 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

Rev. 0 | Page 2 of 24

ADV3228/ADV3229

SPECIFICATIONS

VS = ±5 V, TA = 25°C, RL = 150 Ω, unless otherwise noted.

Table 1.

ADV3228 ADV3229
Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth 200 mV p-p 1200 900 MHz

2 V p-p 750 850 MHz

Gain Flatness 0.1 dB, 2 V p-p 55 50 MHz

0.5 dB, 2 V p-p 250 235 MHz

Propagation Delay 2 V p-p 0.6 0.6 ns

Settling Time 1%, 2 V step 3 3 ns

Slew Rate 2 V step, peak 2500 2500 V/μs

NOISE/DISTORTION PERFORMANCE

Differential Gain Error NTSC or PAL 0.01 0.02 %

Differential Phase Error NTSC or PAL 0.01 0.02 Degrees

Crosstalk, All Hostile, RTO f = 100 MHz −45 −45 dB

f = 5 MHz −87 −70 dB

Off Isolation, Input to Output f = 100 MHz, one channel −80 −87 dB

OIP2 f = 100 MHz, RL = 100 Ω 38 dBm

f = 500 MHz, RL = 100 Ω 15 dBm

OIP3 f = 100 MHz, RL = 100 Ω 32 dBm

f = 500 MHz, RL = 100 Ω 7 dBm

Output 1 dB Compression Point f = 100 MHz, RL = 100 Ω 19 dBm

f = 500 MHz, RL = 100 Ω 10 dBm

Input Voltage Noise Density 50 MHz 18 18 nV/√Hz

DC PERFORMANCE

Gain Error 0.1 0.5 0.2 1.5 %

Gain Matching Channel-to-channel 0.5 1.5 %

Gain Temperature Coefficient 0.5 5 ppm/°C

OUTPUT CHARACTERISTICS

Output Resistance DC, enabled 0.2 0.2 Ω

DC, disabled 15 8 MΩ

Output Disabled Capacitance 2.2 2.6 pF

Output Leakage Current Output disabled 0.5 0.5 μA

Output Voltage Range No load ±3 ±3 V

R

Short-Circuit Current 55 55 mA

INPUT CHARACTERISTICS

Input Offset Voltage Worst case (all configurations) ±5 ±5 mV

Input Offset Voltage Drift 5 5 μV/°C

Input Voltage Range ±3 ±1.5 V

Input Capacitance Any switch configuration 1.8 1.8 pF

Input Resistance 2 2 MΩ

Input Bias Current Any switch configuration ±1 ±1 μA

SWITCHING CHARACTERISTICS

Enable/Disable Time

Switching Time, 2 V Step

Switching Transient (Glitch) 25 50 mV p-p

= 150 Ω ±2.8 ±2.8 V

L

50% UPDATE
50% UPDATE

to 1% settling
to 1% settling

20 20 ns
20 20 ns

Rev. 0 | Page 3 of 24

ADV3228/ADV3229

ADV3228 ADV3229
Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit

POWER SUPPLIES

Supply Current AVCC, outputs enabled, no load 52 70 58 70 mA
AVCC, outputs disabled 12 18 13 18 mA
AVEE, outputs enabled, no load 52 70 58 70 mA
AVEE, outputs disabled 12 18 14 18 mA
DVCC, outputs enabled, no load 6 6 mA

Supply Voltage Range ±4.5 ±5 ±5.5 ±4.5 ±5 ±5.5 V

PSRR DC to 50 kHz, AVCC, AVEE <−60 <−60 dB
f = 100 kHz, AVCC, AVEE −60 −60 dB
f = 10 MHz, AVCC −48 −35 dB
f = 10 MHz, AVEE −35 −55 dB
f = 100 MHz, AVCC −25 −15 dB
f = 100 MHz, AVEE −15 −15 dB
f = 100 kHz, DVCC −90 −90 dB
OPERATING TEMPERATURE RANGE

Temperature Range Operating (still air) −40 +85 −40 +85 °C

θJA Operating (still air) 29 29 °C/W

Rev. 0 | Page 4 of 24

ADV3228/ADV3229

0

TIMING CHARACTERISTICS (SERIAL)

Table 2.

Parameter Symbol Min Typ Max Unit

Serial Data Setup Time t1 10 ns
CLK Pulse Width t2 10 ns
Serial Data Hold Time t3 10 ns
CLK Pulse Separation, Serial Mode t4 10 ns

t

CLK to UPDATE Delay
UPDATE Pulse Width
CLK to DATAOUT Valid, Serial Mode t7 50 ns
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode 8 μs
CLK, UPDATE Rise and Fall Times
RESET Time

Timing Diagram—Serial Mode

CLK

DATAIN

1 = LATCHED

UPDATE

= TRANSPARENT

t

1

0

1

0

t1t

OUT07 (D3) OUT07 (RESERVED) OUT00 (D0)

2

3

t

7

t

4

10 ns

5

t

10 ns

6

20 ns

50 ns
30 ns

LOAD DATA INT O
SERIAL REGI STER
ON FALLING EDGE

t

5

TRANSFER DATA FROM SERIAL

REGISTE R T O PARALLEL

LATCHES DURING LOW LEVEL

t

6

DATAOUT

09318-002

Figure 2. Timing Diagram, Serial Mode

LOGIC LEVELS

Table 3. Logic Levels

VIH V

RESET,

/PAR, CLK,

SER
DATA IN, CE
UPDATE

2.0 V min 0.8 V max 2.4 V min 0.4 V max 2 μA max 2 μA max 2 μA max 300 μA max 3 mA min 1 mA min

V

IL

RESET

,

/PAR, CLK,

SER

,

DATA IN, CE
UPDATE

,

V

OH

I

OL

DATA OUT DATA OUT

I

IH

/PAR,

SER
CLK, DATA IN,
CE

, UPDATE

I

IL

/PAR,

SER
CLK, DATA IN,
CE

, UPDATE

I

IH

RESET

I

IL

RESET

I

OH

OL

DATA OUT DATA OUT

Rev. 0 | Page 5 of 24

ADV3228/ADV3229

TIMING CHARACTERISTICS (PARALLEL)

Table 4.

Parameter Symbol Min Typ Max Unit

Parallel Data Setup Time t1d 10 ns
Address Setup Time t1a 10 ns
CLK Pulse Width t2 10 ns
Parallel Data Hold Time t3d 10 ns
Address Hold Time t3a 10 ns
CLK Pulse Separation t4 20 ns

t

UPDATE Pulse Width
CLK, UPDATE Rise and Fall Times
RESET Time

Timing Diagram—Parallel Mode

CLK

A0 TO A2

D0 TO D3

1 = LATCHED

UPDATE

0 = TRANSPARENT

1
0
1
0
1
0

t

1a

10 ns

5

50 ns
30 ns

t

2

t

1d

Figure 3. Timing Diagram, Parallel Mode

t

4

t

3a

t

3d

t

5

09318-003

Rev. 0 | Page 6 of 24

ADV3228/ADV3229

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Supply Voltage (AVCC to AVEE) 11 V
Digital Supply Voltage (DVCC to DGND) 6 V
Supply Potential Difference (AVCC to DVCC) ±0.5 V
Ground Potential Difference

±0.5 V

(AGND to DGND)

Maximum Potential Difference

6 V

(DVCC to AVEE)
Analog Input Voltage AVEE < VIN < AVCC
Digital Input Voltage DGND < DIN < DVCC
Exposed Paddle Voltage AGND
Output Voltage (Disabled Analog Output) AVEE < V

< AVCC

OUT

Output Short-Circuit

Duration Momentary

Current

Internally limited
to 55 mA

Temperature

Storage Temperature Range −65°C to +125°C

Operating Temperature Range −40°C to +85°C

Junction Temperature 150°C

Lead Temperature

300°C

(Soldering, 10 sec)

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA θ

72-Lead LFCSP_VQ 29 0.5 °C/W

Unit

JC

POWER DISSIPATION

The ADV3228/ADV3229 operate with ±5 V supplies and can
drive loads down to 100 Ω, resulting in a wide range of possible
power dissipations. For this reason, extra care must be taken when
derating the operating conditions based on ambient temperature.

Packaged in the 72-lead LFCSP, the ADV3228/ADV3229 junction­to-ambient thermal impedance (θ

) is 29°C/W. For long-term

JA

reliability, the maximum allowed junction temperature of the
die should not exceed 125°C; even temporarily exceeding this
limit can cause a shift in parametric performance due to a change
in stresses exerted on the die by the package. Exceeding a junction
temperature of 150°C for an extended period can result in device
failure. In Figure 4, the curve shows the range of allowed internal
die power dissipation that meets these conditions over the −40°C
to +85°C ambient temperature range. When using Figure 4, do
not include the external load power in the maximum power
calculation, but do include the load current dropped on the die
output transistors.

7

6

5

4

3

2

MAXIMUM PO WER DISSIPATION (W)

1

0

–40 –20 0 20 40 60 80

AMBIENT TEMPERATURE (°C)

Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature

T

= 150°C

J

9318-004

ESD CAUTION

Rev. 0 | Page 7 of 24

ADV3228/ADV3229

2

F

L

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGNDNCAVEENCAVCCNCAVEE
7271706968676665646362616059585756

AVCC

1

IN0

2

AVEE

3

IN1

4

AVCC

5

IN2

6

AVEE

7

IN3

8

AVCC

9

10

IN4

11

AVEE

12

IN5

13

AVCC

14

IN6

15

AVEE

16

IN7

17

AGND

18

AVEE

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
. EXPOSED PADDLE. THE EXPOSED METAL PADDLE ON THE BOTTOM O

THE LFCSP PACKAGE MUST BE SOLDERED TO THE PCB AGND FOR
PROPER HEAT DISSIPATI ON AND FOR NOI S E AND M E CHANI CA
STRENGTH BENEFITS.

PIN 1
INDICATOR

ADV3228/ADV3229

1920212223242526272829303132333435

OUT7

OUT6

AVEE

AVCC

AVCCNCAVEENCAVCCNCAVEENCAGND

NC

TOP VIEW

(Not to S cale)

OUT4

OUT5

AVEE

AVCC

AVCC

DVCC
55

54

DGND

53

RESET

52

CE

51

DATAOUT

50

CLK

49

DATAIN

48

UPDATE

47

SER/PAR

46

A0

45

A1

44

A2

43

D0

42

D1

41

D2

40

D3

39

NC

38

DGND

37

DVCC

36

OUT3

OUT2

OUT1

AVEE

OUT0

AVEE

AVCC

AVEE

AVCC

09318-005

Figure 5. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1, 5, 9, 13, 19, 23, 27, 31, 35, 60, 64, 68 AVCC Analog Positive Supply.
2 IN0 Input Number 0.
3, 7, 11, 15, 18, 21, 25, 29, 33, 36, 58, 62, 66, 70 AVEE Analog Negative Supply.
4 IN1 Input Number 1.
6 IN2 Input Number 2.
8 IN3 Input Number 3.
10 IN4 Input Number 4.
12 IN5 Input Number 5.
14 IN6 Input Number 6.
16 IN7 Input Number 7.
17, 56, 72 AGND Analog Ground.
20 OUT7 Output Number 7.
22 OUT6 Output Number 6.
24 OUT5 Output Number 5.
26 OUT4 Output Number 4.
28 OUT3 Output Number 3.
30 OUT2 Output Number 2.
32 OUT1 Output Number 1.
34 OUT0 Output Number 0.
37, 55 DVCC Digital Positive Supply.
38, 54 DGND Digital Ground.
39, 57, 59, 61, 63, 65, 67, 69, 71 NC No Internal Connection.

Rev. 0 | Page 8 of 24