ANALOG DEVICES ADV3226, ADV3227 Service Manual

750 MHz, 16 × 16

FEATURES

16 × 16 high speed, nonblocking switch array
Pinout and functionally equivalent to the AD8114/AD8115
Complete solution

Buffered inputs
Programmable high impedance outputs
16 output amplifiers, G = +1 (ADV3226), G = +2 (ADV3227)

Drives 150 Ω loads
Operates on ±5 V supplies
Low power: 1.3 W
Excellent ac performance

−3 dB bandwidth
200 mV p-p: 820 MHz (ADV3226), 750 MHz (ADV3227)
2 V p-p: 600 MHz (ADV3226), 750 MHz (ADV3227)

Slew rate: 2150 V/μs (ADV3226), 2950 V/μs (ADV3227)
Serial or parallel programming of switch array
100-lead LFCSP (12 mm × 12 mm)

APPLICATIONS

Routing of high speed signals including

Video (NTSC, PAL, S, SECAM, YUV, RGB)

Compressed video (MPEG, wavelet)

3-level digital video (HDB3)
Data communications
Telecommunications

GENERAL DESCRIPTION

The ADV3226/ADV3227 are high speed 16 × 16 analog crosspoint
switch matrices. They offer a −3 dB signal bandwidth greater
than 750 MHz and channel switch times of less than 20 ns with
1% settling.

The ADV3226/ADV3227 include 16 independent output buffers
that can be placed into a high impedance state for paralleling
crosspoint outputs to prevent off channels from loading the
output bus. The ADV3226 has a gain of +1 and the ADV3227
has a gain of +2. They both operate on voltage supplies of ±5 V

Analog Crosspoint Switch

ADV3226/ADV3227

FUNCTIONAL BLOCK DIAGRAM

SER/PAR

CLK

DATAIN

UPDATE

CE

RESET

ADV3226/
ADV3227

16

INPUTS

while consuming only 118 mA (ADV3226) and 133 mA
(ADV3227) of idle current. Channel switching is performed via
a serial digital control that can accommodate daisy chaining of
several devices or via a parallel control to allow updating of an
individual output without reprogramming the entire array.

The ADV3226/ADV3227 are available in the 100-lead LFCSP
package over the extended industrial temperature range of

−40°C to +85°C.

D0 D1 D2 D3

80-BIT SHIFT REGISTER

PARALLEL L OADING

PARALLEL L ATCH

DECODE

16 × 5:16 DECODERS

SWITCH
MATRIX

D4

WITH 5-BIT

80

80

256

Figure 1.

SET INDIVIDUAL
OR RESET ALL
OUTPUTS TO OFF

16

OUTPUT
BUFFER

G = +1,

G = +2

A0

A1

A2
A3

DATAOUT

16

OUTPUTS

08653-001

Rev. 0

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ADV3226/ADV3227

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics (Serial) .................................................. 5

Logic Levels ................................................................................... 5

Timing Characteristics (Parallel) ............................................... 6

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

Power Dissipation ......................................................................... 7

REVISION HISTORY

4/10—Revision 0: Initial Version

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions ..............................8

Truth Table and Logic Diagram ............................................... 10

Typical Performance Characteristics ............................................ 11

Circuit Diagrams ............................................................................ 20

Theory of Operation ...................................................................... 21

Applications Information .......................................................... 21

Power-On Reset .......................................................................... 22

Gain Selection ............................................................................. 22

Creating Larger Crosspoint Arrays .......................................... 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

Rev. 0 | Page 2 of 24

ADV3226/ADV3227

SPECIFICATIONS

VS = ±5 V, TA = +25°C, RL = 150 Ω, unless otherwise noted.

Table 1.

ADV3226 ADV3227

Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth 200 mV p-p 820 750 MHz

2 V p-p 600 750 MHz

Gain Flatness 0.1 dB, 2 V p-p 130 60 MHz

0.5 dB, 2 V p-p, CL = 2.2 pF 400 200 MHz

Propagation Delay 2 V p-p 0.6 0.6 ns

Settling Time 1%, 2 V step 3 3 ns

Slew Rate 2 V step, peak 2150 2950 V/μs

NOISE/DISTORTION PERFORMANCE

Differential Gain Error NTSC or PAL 0.04 0.02 %

Differential Phase Error NTSC or PAL 0.01 0.01 Degrees

Crosstalk, All Hostile f = 100 MHz −45 −35 dB

f = 5 MHz −75 −60 dB

Off Isolation, Input to Output f = 100 MHz, one channel −80 −75 dB

IMD2 f = 100 MHz, RL = 100 Ω 47 dBm

f = 500 MHz, RL = 100 Ω 22 dBm

IMD3 f = 100 MHz, RL = 100 Ω 42 dBm

f = 500 MHz, RL = 100 Ω 14 dBm

Output 1 dB Compression Point f = 100 MHz, RL = 100 Ω 18 dBm

f = 500 MHz, RL = 100 Ω 9 dBm

Input Voltage Noise 0.01 MHz to 50 MHz 16 16 nV/√Hz

DC PERFORMANCE

Gain Error 0.1 1.0 0.4 1.5 %

Gain Matching Channel-to-channel 1.0 1.5 %

Gain Temperature Coefficient 0.8 16 ppm/°C

OUTPUT CHARACTERISTICS

Output Resistance DC, enabled 0.2 0.2 Ω

DC, disabled 10 5 MΩ

Output Disabled Capacitance 2.7 2.7 pF

Output Leakage Current Output disabled 1 1 μA

Output Voltage Range No load ±3 ±3 V

R
Short-circuit current 55 55 mA
INPUT CHARACTERISTICS

Input Offset Voltage Worst case (all configurations) ±5 ±5 mV

Input Offset Voltage Drift 8 8 μV/°C

Input Voltage Range No load ±3 ±1.5 V

R

Input Capacitance Any switch configuration 2.1 2.1 pF

Input Resistance 2 2 MΩ

Input Bias Current Any switch configuration 1 1 μA

= 150 Ω ±2.8 ±2.8 V

L

= 150 Ω ±3 ±1.5 V

L

Rev. 0 | Page 3 of 24

ADV3226/ADV3227

ADV3226 ADV3227

Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit

SWITCHING CHARACTERISTICS

Enable/Disable Time
Switching Time, 2 V Step
Switching Transient (Glitch) 40 65 mV p-p

POWER SUPPLIES

Supply Current AVCC, outputs enabled, no load 110 130 125 140 mA
AVCC, outputs disabled 25 35 25 35 mA
AVEE, outputs enabled, no load 110 130 125 140 mA
AVEE, outputs disabled 25 35 25 35 mA
DVCC, outputs enabled, no load 8 10 8 10 mA

Supply Voltage Range ±4.5 ±5 ±5.5 ±4.5 ±5 ±5.5 V

PSRR DC to 50 kHz, AVCC, AVEE >60 >60 dB
f = 100 kHz, AVCC, AVEE 55 60 dB
f = 10 MHz, AVCC 45 40 dB
f = 10 MHz, AVEE 35 55 dB
f = 100 kHz, DVCC 90 80 dB
OPERATING TEMPERATURE RANGE

Temperature Range Operating (still air) −40 +85 −40 +85 °C

θJA Operating (still air) 26 26 °C/W

50%
50%

UPDATE
UPDATE

to 1% settling
to 1% settling

20 20 ns
20 20 ns

Rev. 0 | Page 4 of 24

ADV3226/ADV3227

0

T

TIMING CHARACTERISTICS (SERIAL)

Table 2.

Parameter Symbol Min Typ Max Unit

Serial Data Setup Time t1 10 ns
CLK Pulse Width t2 10 ns
Serial Data Hold Time t3 10 ns
CLK Pulse Separation, Serial Mode t4 10 ns

t

CLK to
UPDATE

UPDATE

Delay

Pulse Width

CLK to DATAOUT Valid, Serial Mode t7 50 ns
Propagation Delay,

UPDATE

to Switch On or Off

Data Load Time, CLK = 5 MHz, Serial Mode 1.6 μs
CLK,

RESET

UPDATE

Rise and Fall Times

Time

Timing Diagram—Serial Mode

CLK

DATAIN

1 = LATCHED

UPDATE

= TRANSPAREN

t

1

0

1

0

t1t

OUT07 (D4) O UT07 (D3) OUT00 (D0)

2

3

t

7

t

4

10 ns

5

t

10 ns

6

20 ns

50 ns
30 ns

LOAD DATA INT O

SERIAL REGISTER

ON FALLING EDGE

t

5

TRANSFER DATA F ROM SERIAL

REGISTER TO PARALLEL

LATCHES DURING LOW LEVEL

t

6

DATAOUT

08653-002

Figure 2. Timing Diagram, Serial Mode

LOGIC LEVELS

Table 3. Logic Levels

VIH V

,

/PAR,

SER

RESET
CLK, DATAIN,
CE

,

UPDATE

2.0 V min 0.8 V max 2.4 V min 0.4 V max 2 μA max 2 μA max 2 μA max 300 μA max 3 mA min 1 mA min

V

IL

,

/PAR,

SER

RESET

V

OH

DATAOUT DATAOUT

CLK, DATAIN,
CE

,

UPDATE

I

OL

I

IH

/PAR,

SER
CLK, DATAIN,

,

CE

UPDATE

I

IL

/PAR, CLK,

SER
DATAIN,
UPDATE

CE

IH

RESET

,

I

I

IL

RESET

I

OH

OL

DATAOUT DATAOUT

Rev. 0 | Page 5 of 24

ADV3226/ADV3227

TIMING CHARACTERISTICS (PARALLEL)

Table 4.

Parameter Symbol Min Typ Max Unit

Parallel Data Setup Time t1d 10 ns
Address Setup Time t1a 10 ns
CLK Pulse Width t2 10 ns
Parallel Data Hold Time t3d 10 ns
Address Hold Time t3a 10 ns
CLK Pulse Separation t4 20 ns

t

UPDATE
CLK,
RESET

Pulse Width

UPDATE

Time

Rise and Fall Times

Timing Diagram—Parallel Mode

CLK

A0 TO A3

D0 TO D4

1 = LATCHED

0 = TRANSPARENT

UPDATE

1

0

1

0

1

0

t

1a

10 ns

5

50 ns
30 ns

t

2

t

1d

Figure 3. Timing Diagram, Parallel Mode

t

4

t

3a

t

3d

t

5

08653-003

Rev. 0 | Page 6 of 24

ADV3226/ADV3227

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Supply Voltage (AVCC − AVEE) 11 V
Digital Supply Voltage (DVCC − DGND) 6 V
Supply Potential Difference

±0.5 V

(AVCC − DVCC)

Ground Potential Difference

±0.5 V

(AGND − DGND)

Maximum Potential Difference

6 V

(DVCC − AVEE)
Analog Input Voltage AVEE < VIN < AVCC
Digital Input Voltage DGND < DIN < DVCC
Exposed Paddle Voltage AVEE < VIN < AVCC
Output Voltage (Disabled Analog

AVEE < V

< AVCC

OUT

Output)
Output Short-Circuit

Duration Momentary

Current Internally limited to 55 mA
Temperature

Storage Temperature Range −65°C to +125°C

Operating Temperature Range −40°C to +85°C

Junction Temperature 150°C

Lead Temperature (Soldering,

300°C

10 sec)

POWER DISSIPATION

The ADV3226/ADV3227 operate with ±5 V supplies and can
drive loads down to 100 Ω, resulting in a wide range of possible
power dissipations. For this reason, extra care must be taken
when derating the operating conditions based on ambient
temperature.

Packaged in the 100-lead LFCSP, the ADV3226/ADV3227
junction-to-ambient thermal impedance (θ
For long-term reliability, the maximum allowed junction
temperature of the die should not exceed 125°C; even
temporarily exceeding this limit can cause a shift in parametric
performance due to a change in stresses exerted on the die by
the package. Exceeding a junction temperature of 150°C for an
extended period can result in device failure. In Figure 4, the
curve shows the range of allowed internal die power dissipation
that meets these conditions over the −40°C to +85°C ambient
temperature range. When using Figure 4, do not include the
external load power in the maximum power calculation, but do
include the load current dropped on the die output transistors.

6

5

) is 26°C/W.

JA

TJ = 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA θJC θJB ψJT ψJB Unit

100-Lead LFCSP 26 2.56 9.5 0.2 8.9 °C/W

4

MAXIMUM POWER (W)

3

2

15 25 35 45 55 65 75 85

Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature

AMBIENT TEMPERATURE (°C)

ESD CAUTION

08653-004

Rev. 0 | Page 7 of 24

ADV3226/ADV3227

T

O

O

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RESETCEDATAOU

CLK

DATAIN

UPDATE

SER/PARNCNCNCNCNCNCNCNCNCA0A1A2A3D0D1D2D3D4

100

99

98

95

97

93

96

94

898887

92

91

90

84

86

85

82

81

83

787776

80

79

1

DVCC

2

DGND

3

AGND

4

IN08

5

AGND

6

IN09

7

AGND

8

IN10

9

AGND

10

IN11

11

AGND

12

IN12

13

AGND

14

IN13

15

AGND

16

IN14

17

AGND

18

IN15

19

AGND

20

AVEE

21

AVCC

22

AVCC

23

UT15

24

AVEE

25

UT14

NOTES

1. NC = NO CONNECT.

2. T HE EXPOSE D METAL PADDL E ON THE BOT TOM O F THE LF CSP PACKAGE MUST BE SOLDERED TO PCB
GROUND FOR PRO PER HEAT DISSIPATIO N AND ALSO FO R NOISE AND MECHANI CAL STRENGT H BENEFITS.

PIN 1

26

AVCC

ADV3226/ADV3227

TOP VIEW

(Not to Scale)

27

28

OUT13

31

29

AVEE

OUT12

33

30

32

AVEE

AVCC

OUT10

OUT11

34

AVCC

37

38

39

42

44

35

36

AVEE

OUT09

OUT08

40

41

AVEE

AVCC

OUT06

OUT07

45

43

AVEE

AVCC

OUT05

48

49

46

AVCC

OUT04

50

47

AVEE

AVCC

OUT03

OUT02

Figure 5. Pin Configuration

75

DVCC

74

DGND

73

AGND

72

IN07

71

AGND

70

IN06

69

AGND

68

IN05

67

AGND

66

IN04

65

AGND

64

IN03

63

AGND

62

IN02

61

AGND

60

IN01

59

AGND

58

IN00

57

AGND

56

AVEE

55

AVCC

54

AVCC

53

OUT00

52

AVEE

51

OUT01

08653-005

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 DVCC Digital Positive Power Supply.
2 DGND Digital Ground.
3 AGND Analog Ground.
4 IN08 Input Number 8.
5 AGND Analog Ground.
6 IN09 Input Number 9.
7 AGND Analog Ground.
8 IN10 Input Number 10.
9 AGND Analog Ground.
10 IN11 Input Nu mbe r 11.
11 AGND Analog Ground.
12 IN12 Input Number 12.
13 AGND Analog Ground.
14 IN13 Input Number 13.
15 AGND Analog Ground.
16 IN14 Input Number 14.

Rev. 0 | Page 8 of 24

Pin No. Mnemonic Description

17 AGND Analog Ground.
18 IN15 Input Number 15.
19 AGND Analog Ground.
20 AVEE Analog Negative Supply.
21 AVCC Analog Positive Supply
22 AVCC Analog Positive Supply.
23 OUT15 Output Number 15.
24 AVEE Analog Negative Supply.
25 OUT14 Output Number 14.
26 AVCC Analog Positive Supply.
27 OUT13 Output Number 13.
28 AVEE Analog Negative Supply.
29 OUT12 Output Number 12.
30 AVCC Analog Positive Supply.
31 OUT11 Output Number 11.
32 AVEE Analog Negative Supply.