ANALOG DEVICES ADV3201 Service Manual

300 MHz, 32 × 32 Buffered

V

FEATURES

Large, 32 × 32, nonblocking switch array G = +1 (ADV3200) or G = +2 (ADV3201) operation Pin-compatible 32 × 16 versions available

(ADV3202/ADV3203)

Single 5 V supply, dual ±2.5 V supply, or

dual ±3.3 V supply (G = +2) Serial programming of switch array 2:1 OSD insertion mux per output Input sync-tip clamp High impedance output disable allows connection of

multiple devices with minimal output bus load Excellent video performance

60 MHz, 0.1 dB gain flatness

0.1% differential gain error (R

0.1° differential phase error (R

Excellent ac performance

Bandwidth: >300 MHz

Slew rate: >400 V/μs Low power: 1.25 W Low all hostile crosstalk of −48 dB @ 5 MHz Reset pin allows disabling of all outputs

Connected through a capacitor to ground, provides

power-on reset capability 176-lead exposed pad LQFP (24 mm × 24 mm)

APPLICATIONS

CCTV sur veillance Routing of high speed signals including

Composite video (NTSC, PAL, S, SECAM)

RGB and component video routing

Compressed video (MPEG, Wavelet) Video conferencing

= 150 Ω)

L

= 150 Ω)

L

DATA IN

UPDATE

RESET

INPUTS

Analog Crosspoint Switch

ADV3200/ADV3201

FUNCTIONAL BLOCK DIAGRAM

DGNDDVCC

ADV3200

(ADV3201)

32

ENABLE/ DISABLE

OUTPUT BUFFER

G = +1

(G = +2)

. . .

3232

OSD

. . .

CLK

CS

ENABLE/

BYPASS

SYNC-TIP

CLAMP

. .

32

.

VCLAMP VREFOSD

193-BIT SHI FT REGISTER

PARALLEL L ATCH

32 × 5:32

DECODERS

SWITCH

.

MATRIX

. .

REFERENCE

POS

193

192

1024

INPUTS

Figure 1.

NEG

OSD MUX

SWITCHES

DATA OUT

32 OUTPUTS

07176-001

GENERAL DESCRIPTION

The ADV3200/ADV3201 are 32 × 32 analog crosspoint switch matrices. They feature a selectable sync-tip clamp input for ac-coupled applications and an on-screen display (OSD) insertion mux. With −48 dB of crosstalk and −80 dB isolation at 5 MHz, the ADV3200/ADV3201 are useful in many high density routing applications. The 0.1 dB flatness out to 60 MHz makes the ADV3200/ADV3201 ideal for composite video switching.

The 32 independent output buffers of the ADV3200/ADV3201 can be placed into a high impedance state for paralleling crosspoint outputs so that off channels present minimal loading to

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

an output bus if building a larger array. The part is available in a gain of +1 (ADV3200) or +2 (ADV3201) for ease of use in back-terminated load applications. A single 5 V supply, dual ±2.5 V supplies, or dual ±3.3 V supplies (G = +2) can be used while consuming only 250 mA of idle current with all outputs enabled. The channel switching is performed via a double buffered, serial digital control, which can accommodate daisy chaining of several devices.

The ADV3200/ADV3201 are packaged in a 176-lead exposed pad LQFP (24 mm × 24 mm) and are available over the extended industrial temperature range of −40°C to +85°C.

ADV3200/ADV3201

REVISION HISTORY

10/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

ADV3200/ADV3201

SPECIFICATIONS

OSD DISABLED

VS = ±2.5 V (ADV3200), VS = ±3.3 V (ADV3201) at TA = 25°C, G = +1 (ADV3200), G = +2 (ADV3201), RL = 150 Ω, all configurations, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth 200 mV p-p

2 V p-p 120 MHz

Gain Flatness 0.1 dB, 200 mV p-p 60 MHz

0.1 dB, 2 V p-p 40 MHz

Settling Time 1%, 2 V step 6 ns

Slew Rate 2 V step, peak 400 V/μs

NOISE/DISTORTION PERFORMANCE

Differential Gain Error NTSC or PAL

ADV3200 0.06 % ADV3201 0.1 %

Differential Phase Error NTSC or PAL

ADV3200 0.06 Degrees

ADV3201 0.03 Degrees Crosstalk, All Hostile, RTI f = 5 MHz, RL = 150 Ω −48 dB f = 5 MHz, RL = 1 kΩ −65 dB f = 100 MHz, RL = 150 Ω −23 dB f = 100 MHz, RL = 1 kΩ −30 dB Off Isolation, Input-to-Output, RTI f = 5 MHz, one channel −80 dB Input Voltage Noise 0.1 MHz to 50 MHz

ADV3200 25 nV/√Hz

ADV3201 22 nV/√Hz

DC PERFORMANCE

Gain Error

ADV3200 No load (broadcast mode) ±0.5 ±1.75 % Broadcast mode ±0.5 ±2.2 %

ADV3201 No load (broadcast mode) ±0.5 ±2.2 % Broadcast mode ±0.5 ±2.7 % Gain Matching No load, channel-to-channel ±0.5 ±2.8 % Channel-to-channel ±0.8 ±3.4 %

OUTPUT CHARACTERISTICS

Output Impedance DC, enabled 0.15 Ω

ADV3200 DC, disabled 900 1000 kΩ

ADV3201 DC, disabled 3.2 4 kΩ Output Capacitance Disabled 3.7 pF Output Voltage Range

ADV3200 −1.1 to +1.1 −1.2 to +1.2 V

ADV3201 −1.5 to +1.5 −1.6 to +2.0 V No output load −1.5 to +1.5 −2.0 to +2.0 V

INPUT CHARACTERISTICS

Input Offset Voltage ±5 ±30 mV Input Voltage Range

ADV3200 −1.1 to +1.1 −1.2 to +1.2 V

ADV3201 −0.75 to +0.75 −0.8 to +1.0 V No output load −0.75 to +0.75 −1.0 to +1.0 V

300 MHz

Rev. 0 | Page 3 of 36

ADV3200/ADV3201

Parameter Test Conditions/Comments Min Typ Max Unit

Input Capacitance 3 pF Input Resistance 1 4 MΩ Input Bias Current

Sync-tip clamp disabled −10 −3 μA

SWITCHING CHARACTERISTICS

Enable On Time 50% update to 1% settling 50 ns Switching Time, 2 V Step 50% update to 1% settling 40 ns Switching Transient (Glitch) IN00 to IN31, RTI 300 mV p-p

POWER SUPPLIES

Supply Current

ADV3200 VPOS or VNEG, outputs enabled, no load 250 300 mA VPOS or VNEG, outputs disabled 120 155 mA ADV3201 VPOS or VNEG, outputs enabled, no load 260 310 mA VPOS or VNEG, outputs disabled 130 165 mA DVCC 2.5 3.5 mA

Supply Voltage Range VPOS − VNEG

PSR VNEG, VPOS, f = 1 MHz

ADV3200 −50 dB ADV3201 −45 dB

OPERATING TEMPERATURE RANGE

Temperature Range Operating (still air) −40 to +85 °C θJA Operating (still air) 16 °C/W

Sync-tip clamp enabled,

= VCLAMP + 0.1 V

V

IN

Sync-tip clamp enabled, VIN = VCLAMP − 0.1 V

0.1 3 12 μA

−2.9 −1 −0.25 mA

5 ± 10% to

6.6 ± 10%

V

OSD ENABLED

VS = ±2.5 V (ADV3200), VS = ±3.3 V (ADV3201) at TA = 25°C, G = +1 (ADV3200), G = +2 (ADV3201), RL = 150 Ω, all configurations, unless otherwise noted.

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

OSD DYNAMIC PERFORMANCE

−3 dB Bandwidth ADV3200 200 mV p-p 2 V p-p 135 MHz ADV3201 200 mV p-p 2 V p-p 130 MHz

Gain Flatness 0.1 dB, 200 mV p-p 35 MHz

0.1 dB, 2 V p-p 35 MHz

Settling Time 1%, 2 V step 6 ns Slew Rate 2 V step, peak 400 V/μs

OSD NOISE/DISTORTION PERFORMANCE

Differential Gain Error NTSC or PAL

ADV3200 0.12 % ADV3201 0.35 %

Differential Phase Error NTSC or PAL

ADV3200 0.06 Degrees ADV3201 0.04 Degrees

Input Voltage Noise 0.5 MHz to 50 MHz

ADV3200 27 nV/√Hz ADV3201 25 nV/√Hz

170 MHz

150 MHz

Rev. 0 | Page 4 of 36

ADV3200/ADV3201

Parameter Test Conditions/Comments Min Typ Max Unit

OSD DC PERFORMANCE

Gain Error

ADV3200 No load ±0.1 ±2.3 % ±0.1 ±2.7 % ADV3201 No load ±0.1 ±2.2 % ±0.1 ±2.7 %

OSD INPUT CHARACTERISTICS

Input Offset Voltage ±5 ±30 mV Input Bias Current −10 −4 μA

OSD SWITCHING CHARACTERISTICS

OSD Switch Delay, 2 V Step 50% OSD switch to 1% settling 20 ns OSD Switching Transient (Glitch)

ADV3200 15 mV p-p ADV3201 40 mV p-p

TIMING CHARACTERISTICS (SERIAL MODE)

Table 3.

Limit Parameter Symbol Min Typ Max Unit

Serial Data Setup Time t1 40 ns CLK Pulse Width t2 50 ns Serial Data Hold Time t3 50 ns CLK Pulse Separation t4 150 ns

t

CLK to UPDATE Delay UPDATE Pulse Width CLK to DATA OUT Valid t7 130 ns Propagation Delay, UPDATE to Switch On or Off Data Load Time, CLK = 5 MHz, Serial Mode 38.6 μs RESET Time

50 160 ns

5

t

40 ns

6

50 ns

160 ns

CS

CLK

DATA IN

1 = LATCHED

UPDATE

0 = TRANSPARENT

DATA OUT

1

0

t

1

0

t

1t3

1

0

CLAMP

ON/OFF

2

t

7

t

4

Figure 2. Timing Diagram, Serial Mode

Rev. 0 | Page 5 of 36

LOAD DATA INTO

SERIAL REGISTER

ON RISING EDGE

TRANSFER DATA FROM SERIAL

LATCHES DURING LOW LEVEL

OUT00 (D0)OUT31 (D5)

t

5

REGISTER TO PARALLEL

t

6

07176-002

ADV3200/ADV3201

DATA IN

UPDATE

0 1 2 3 4 5 6 7 8 9 10 11 1213 19 25 31 36

CLK

T = 0

IN00

CONNECT TO

ENABLE OUT31

ENABLE SYNC-TIP CLAMP

IN01

CONNECT TO

ENABLE OUT30

DON’T CARE

DISABLE O UT29

INCREASING TIME

IN31

CONNECT TO

ENABLE OUT28

ENABLE OUT27

187 192

IN07

CONNECT TO

IN00

CONNECT TO

ENABLE OUT00

07176-105

Figure 3. Programming Example

Table 4. Logic Levels, DVCC = 3.3 V

VIH VIL V

RESET, CS, CLK, DATA IN,

UPDATE

, OSDS

RESET

, CS,

CLK, DATA IN, UPDATE

, OSDS

V

OH

I

OL

DATA OUT DATA OUT

I

IH

, CS,

RESET CLK, DATA IN,

UPDATE

, OSDS

I

IL

RESET

, CS,

CLK, DATA IN, UPDATE

, OSDS

I

OH

OL

DATA OUT DATA OUT

2.5 V min 0.8 V max 2.7 V min 0.5 V max 0.5 μA typ −0.5 μA typ 3 mA typ −3 mA typ

Rev. 0 | Page 6 of 36

ADV3200/ADV3201

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Supply Voltage

7.5 V

(VPOS − VNEG)

Digital Supply Voltage

6 V

(DVCC − DGND)

Ground Potential Difference

+0.5 V to −4 V

(VNEG − DGND)

Maximum Potential Difference

DVCC − VNEG 9.4 V Disabled Outputs

ADV3200 (|V ADV3201

(|V

OSD

|VCLAMP − V

− V

OSD

|) <3 V

OUT

<3 V

− (V

+ VREF)/2|)

OUT

| 6 V

INxx

VREF Input Voltage

ADV3200 VPOS − 3.5 V to VNEG + 3.5 V

ADV3201 VPOS − 4 V to VNEG + 4 V Analog Input Voltage VNEG to VPOS Digital Input Voltage DVCC Output Voltage

(VPOS − 1 V) to (VNEG + 1 V)

(Disabled Analog Output) Output Short-Circuit Duration Momentary Output Short-Circuit Current 45 mA Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature

300°C

(Soldering 10 sec) Junction Temperature 150°C

POWER DISSIPATION

The ADV3200/ADV3201 are operated with ±2.5 V, 5 V, or ±3.3 V supplies and can drive loads down to 150 , resulting in a large range of possible power dissipations. For this reason, extra care must be taken to derate the operating conditions based on ambient temperature.

The ADV3200/ADV3201 are packaged in a 176-lead exposed pad LQFP. The junction-to-ambient thermal impedance (θ the ADV3200/ADV3201 is 16°C/W. For long-term reliability, the maximum allowed junction temperature of the die should not exceed 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. Figure 4 shows the range of allowed internal die power dissipations that meet these conditions over the −40°C to +85°C ambient temperature range. When using Figure 4, do not include external load power in the maximum power calculation, but do include load current dropped on the die output transistors.

9

TJ = 150°C

8

7

6

JA

) of

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA Unit

176-Lead LQFP_EP 16 °C/W

Rev. 0 | Page 7 of 36

5

MAXIMUM POWER (W)

4

3

15 25 35 45 55 65 75 85

AMBIENT TEMPERATURE (°C)

Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature

ESD CAUTION

07176-003

ADV3200/ADV3201

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OSD10

OSD09

OSD08

VPOS

OUT15

VNEG

OUT14

VPOS

OUT13

VNEG

OUT12

VPOS

OUT11

VNEG

OUT10

VPOS

OUT09

VNEG

OUT08

VPOS

OUT07

VNEG

OUT06

VPOS

OUT05

VNEG

OUT04

VPOS

OUT03

VNEG

OUT02

VPOS

OUT01

VNEG

OUT00

VPOS

OSD07

OSD06

OSD05

OSD04

OSD03

OSD02

OSD01

DGND

148

150

151

152

153

155

156

157

158

159

160

161

ADV3200/ADV3201

TOP VIEW

(Not to Scale)

154

149

146

139

136

135

132

VNEG

131

OSD11

130

OSD12

129

OSD13

128

OSD14

127

OSD15

126

OSDS16

125

IN16

124

OSDS17

123

IN17

122

OSDS18

121

IN18

120

OSDS19

119

IN19

118

OSDS20

117

IN20

116

OSDS21

115

IN21

114

OSDS22

113

IN22

112

OSDS23

111

IN23

110

OSDS24

109

IN24

108

OSDS25

107

IN25

106

OSDS26

105

IN26

104

OSDS27

103

IN27

102

OSDS28

101

IN28

100

OSDS29

99

IN29

98

OSDS30

97

IN30

96

OSDS31

95

IN31

94

VPOS

93

OSD16

92

OSD17

91

OSD18

90

OSD19

89

VNEG

133

134

137

138

140

141

142

143

144

145

147

DVCC OSD00 RESET

CLK

DATA IN

DATA OUT

UPDATE

OSDS15

IN00

OSDS14

IN01

OSDS13

IN02

OSDS12

IN03

OSDS11

IN04

OSDS10

IN05

OSDS09

IN06

OSDS08

IN07

OSDS07

IN08

OSDS06

IN09

OSDS05

IN10

OSDS04

IN11

OSDS03

IN12

OSDS02

IN13

OSDS01

IN14

OSDS00

IN15

VNEG

VREF

VCLAMP

OSD31

CS

172

171

170

169

166

167

165

164

163

162

173

176

174

175

1

PIN 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

168

45

OSD3046OSD2947OSD2848OSD2749OSD2650OSD2551OSD24

NOTES

1. OSDSxx: OS D SELECT F OR OUTxx OSDxx: OSD VIDEO INPUT FOR OUTxx

2. THE EXPOSED PAD SHOULD BE CONNECTED TO ANALOG GRO UND.

52

VPOS

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

VPOS

VNEG

OUT31

OUT30

VPOS

VNEG

OUT29

OUT28

VPOS

VNEG

OUT27

OUT26

VPOS

VNEG

OUT25

OUT24

VPOS

VNEG

OUT23

OUT22

VPOS

VNEG

OUT21

OUT20

VPOS

VNEG

OUT19

OUT18

VPOS

VNEG

OUT17

OUT16

OSD2386OSD2287OSD2188OSD20

07176-004

Figure 5. Pin Configuration

Rev. 0 | Page 8 of 36

ADV3200/ADV3201

Table 7. Pin Function Descriptions

Pin Mnemonic Description 1 DVCC Digital Positive Power Supply. 2 OSD00 OSD Input Number 0. 3

RESET

Control Pin: First and Second Rank Reset.

4 CLK Control Pin: Serial Data Clock. 5 DATA IN Control Pin: Serial Data In. 6 DATA OUT Control Pin: Serial Data Out. 7

8

UPDATE CS

Control Pin: Second Rank Write Strobe.

Control Pin: Chip Select. 9 OSDS15 Control Pin: OSD Select Number 15. 10 IN00 Input Number 0. 11 OSDS14 Control Pin: OSD Select Number 14. 12 IN01 Input Number 1. 13 OSDS13 Control Pin: OSD Select Number 13. 14 IN02 Input Number 2. 15 OSDS12 Control Pin: OSD Select Number 12. 16 IN03 Input Number 3. 17 OSDS11 Control Pin: OSD Select Number 11. 18 IN04 Input Number 4. 19 OSDS10 Control Pin: OSD Select Number 10. 20 IN05 Input Number 5. 21 OSDS09 Control Pin: OSD Select Number 9. 22 IN06 Input Number 6. 23 OSDS08 Control Pin: OSD Select Number 8. 24 IN07 Input Number 7. 25 OSDS07 Control Pin: OSD Select Number 7. 26 IN08 Input Number 8. 27 OSDS06 Control Pin: OSD Select Number 6. 28 IN09 Input Number 9. 29 OSDS05 Control Pin: OSD Select Number 5. 30 IN10 Input Number 10. 31 OSDS04 Control Pin: OSD Select Number 4. 32 IN11 Input Number 11. 33 OSDS03 Control Pin: OSD Select Number 3. 34 IN12 Input Number 12. 35 OSDS02 Control Pin: OSD Select Number 2. 36 IN13 Input Number 13. 37 OSDS01 Control Pin: OSD Select Number 1. 38 IN14 Input Number 14. 39 OSDS00 Control Pin: OSD Select Number 0. 40 IN15 Input Number 15. 41 VNEG Analog Negative Power Supply. 42 VREF

Reference Voltage. See the Theory of

Operation section for details. 43 VCLAMP

Sync-Tip Clamp Voltage. See the

Theory of Operation section for details. 44 OSD31 OSD Input Number 31. 45 OSD30 OSD Input Number 30. 46 OSD29 OSD Input Number 29. 47 OSD28 OSD Input Number 28. 48 OSD27 OSD Input Number 27. 49 OSD26 OSD Input Number 26.

Pin Mnemonic Description 50 OSD25 OSD Input Number 25. 51 OSD24 OSD Input Number 24. 52 VPOS Analog Positive Power Supply. 53 OUT31 Output Number 31. 54 VNEG Analog Negative Power Supply. 55 OUT30 Output Number 30. 56 VPOS Analog Positive Power Supply. 57 OUT29 Output Number 29. 58 VNEG Analog Negative Power Supply. 59 OUT28 Output Number 28. 60 VPOS Analog Positive Power Supply. 61 OUT27 Output Number 27. 62 VNEG Analog Negative Power Supply. 63 OUT26 Output Number 26. 64 VPOS Analog Positive Power Supply. 65 OUT25 Output Number 25. 66 VNEG Analog Negative Power Supply. 67 OUT24 Output Number 24. 68 VPOS Analog Positive Power Supply. 69 OUT23 Output Number 23. 70 VNEG Analog Negative Power Supply. 71 OUT22 Output Number 22. 72 VPOS Analog Positive Power Supply. 73 OUT21 Output Number 21. 74 VNEG Analog Negative Power Supply. 75 OUT20 Output Number 20. 76 VPOS Analog Positive Power Supply. 77 OUT19 Output Number 19. 78 VNEG Analog Negative Power Supply. 79 OUT18 Output Number 18. 80 VPOS Analog Positive Power Supply. 81 OUT17 Output Number 17. 82 VNEG Analog Negative Power Supply. 83 OUT16 Output Number 16. 84 VPOS Analog Positive Power Supply. 85 OSD23 OSD Input Number 23. 86 OSD22 OSD Input Number 22. 87 OSD21 OSD Input Number 21. 88 OSD20 OSD Input Number 20. 89 VNEG Analog Negative Power Supply. 90 OSD19 OSD Input Number 19. 91 OSD18 OSD Input Number 18. 92 OSD17 OSD Input Number 17. 93 OSD16 OSD Input Number 16. 94 VPOS Analog Positive Power Supply. 95 IN31 Input Number 31. 96 OSDS31 Control Pin: OSD Select Number 31. 97 IN30 Input Number 30. 98 OSDS30 Control Pin: OSD Select Number 30. 99 IN29 Input Number 29. 100 OSDS29 Control Pin: OSD Select Number 29.

Rev. 0 | Page 9 of 36

ADV3200/ADV3201

Pin Mnemonic Description 101 IN28 Input Number 28. 102 OSDS28 Control Pin: OSD Select Number 28. 103 IN27 Input Number 27. 104 OSDS27 Control Pin: OSD Select Number 27. 105 IN26 Input Number 26. 106 OSDS26 Control Pin: OSD Select Number 26. 107 IN25 Input Number 25. 108 OSDS25 Control Pin: OSD Select Number 25. 109 IN24 Input Number 24. 110 OSDS24 Control Pin: OSD Select Number 24. 111 IN23 Input Number 23. 112 OSDS23 Control Pin: OSD Select Number 23. 113 IN22 Input Number 22. 114 OSDS22 Control Pin: OSD Select Number 22. 115 IN21 Input Number 21. 116 OSDS21 Control Pin: OSD Select Number 21. 117 IN20 Input Number 20. 118 OSDS20 Control Pin: OSD Select Number 20. 119 IN19 Input Number 19. 120 OSDS19 Control Pin: OSD Select Number 19. 121 IN18 Input Number 18. 122 OSDS18 Control Pin: OSD Select Number 18. 123 IN17 Input Number 17. 124 OSDS17 Control Pin: OSD Select Number 17. 125 IN16 Input Number 16. 126 OSDS16 Control Pin: OSD Select Number 16. 127 OSD15 OSD Input Number 15. 128 OSD14 OSD Input Number 14. 129 OSD13 OSD Input Number 13. 130 OSD12 OSD Input Number 12. 131 OSD11 OSD Input Number 11. 132 VNEG Analog Negative Power Supply. 133 OSD10 OSD Input Number 10. 134 OSD09 OSD Input Number 9. 135 OSD08 OSD Input Number 8. 136 VPOS Analog Positive Power Supply. 137 OUT15 Output Number 15. 138 VNEG Analog Negative Power Supply. 139 OUT14 Output Number 14.

Pin Mnemonic Description 140 VPOS Analog Positive Power Supply. 141 OUT13 Output Number 13. 142 VNEG Analog Negative Power Supply. 143 OUT12 Output Number 12. 144 VPOS Analog Positive Power Supply. 145 OUT11 Output Number 11. 146 VNEG Analog Negative Power Supply. 147 OUT10 Output Number 10. 148 VPOS Analog Positive Power Supply. 149 OUT09 Output Number 9. 150 VNEG Analog Negative Power Supply. 151 OUT08 Output Number 8. 152 VPOS Analog Positive Power Supply. 153 OUT07 Output Number 7. 154 VNEG Analog Negative Power Supply. 155 OUT06 Output Number 6. 156 VPOS Analog Positive Power Supply. 157 OUT05 Output Number 5. 158 VNEG Analog Negative Power Supply. 159 OUT04 Output Number 4. 160 VPOS Analog Positive Power Supply. 161 OUT03 Output Number 3. 162 VNEG Analog Negative Power Supply. 163 OUT02 Output Number 2. 164 VPOS Analog Positive Power Supply. 165 OUT01 Output Number 1. 166 VNEG Analog Negative Power Supply. 167 OUT00 Output Number 0. 168 VPOS Analog Positive Power Supply. 169 OSD07 OSD Input Number 7. 170 OSD06 OSD Input Number 6. 171 OSD05 OSD Input Number 5. 172 OSD04 OSD Input Number 4. 173 OSD03 OSD Input Number 3. 174 OSD02 OSD Input Number 2. 175 OSD01 OSD Input Number 1. 176 DGND Digital Negative Power Supply. Exposed Pad Connect to analog ground.

Rev. 0 | Page 10 of 36

ADV3200/ADV3201

TRUTH TABLE AND LOGIC DIAGRAM

Table 8. Operation Truth Table

CS

X

UPDATE

1

X X X X 0

0 1

0 0 X X X 1

1 X X X X 1 Chip is not selected. No change in logic.

1

X = don’t care.

2

Datai: serial data.

DATA

IN

R

ESE

CLK

CS

CLK DATA IN DATA OUT

2

Data

DQ

CLK

i

DQ

D

Q

DQ

CLR CLR CLR CL R CLR CLR CLR CLR CL R CLR CL R CLR CL R CLR

CLR

T

CLK

Data

DQ

CLK

1

i-193

DQ

CLK

RESET

Operation/Comment

Asynchronous reset. All outputs are disabled. The 193-bit shift register is reset to all 0s.

The data on the serial DATA IN line is loaded into the serial register. The first bit clocked into the serial register appears at DATA OUT 193 clock cycles later.

Switch matrix update. Data in the 193-bit shift register is transferred into the parallel latches that control the switch array and sync-tip clamps.

DQ

. . .

CLK

DQ

CLK

DATA OUT

UPDATE

RESET

LE D

OUT00

0 LSB 192

CLR Q

LE D

OUT00

1

LSB

191

CLR Q

LE D

OUT00

2

LSB

190

CLR Q

LE D

OUT00

3

LSB

189

CLR Q

LE D

OUT00

4

LSB

188

CLR Q

LE D

OUT00

OUT01

EN

187

0

LSB

186

CLR Q

SWITCH MATRIX

MSB

CLR Q

Figure 6. Logic Diagram

LE D

OUT30

OUT31

EN

. . .

MSB

CLR Q

DECODE

1024 32

0

LSB

7

6

CLR Q

1

LSB

5

CLR Q

OUT31

2

LSB

4

CLR Q

OUT31

3

LSB

3

CLR Q

LE D

OUT31

4

LSB

2

CLR Q

LE D

OUT31

EN

MSB

1

CLR Q

LE D

OUT31

SYNC

CLR Q

TIP

EN

0

OUTPUT ENABLE

07176-053

Rev. 0 | Page 11 of 36

ANALOG DEVICES ADV3201 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

OSD DISABLED

OSD ENABLED

TIMING CHARACTERISTICS (SERIAL MODE)

ABSOLUTE MAXIMUM RATINGS

POWER DISSIPATION

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TRUTH TABLE AND LOGIC DIAGRAM