ANALOG DEVICES ADV202 Service Manual

www.BDTIC.com/ADI

JPEG2000 Video Codec

FEATURES

Complete single-chip JPEG2000 compression and

decompression solution for video and still images

Patented SURF® (spatial ultra-efficient recursive filtering)

echnology enables low power and low cost wavelet-

t
based compression

Supports both 9/7 and 5/3 wavelet transforms with up to

vels of transform

6 le

Programmable tile/image size with widths up to 2048 pixels in

component 4:2:2 interleaved mode, and up to 4096 pixels

3-

in single-component mode
Maximum tile/image width: 4096 pixels
Video interface directly supporting ITU.R-BT656,

SMPTE125M P

ITU.R-BT1358 (625p) or any video format with a maximum

input rate of 65 MSPS for irreversible mode or 40 MSPS for

reversible mode
Two or more ADV202s can be combined to support full-

fr

ame SMPTE274M HDTV (1080i) or SMPTE296M (720p)

Flexible asynchronous SRAM-style host interface allows

glueless

and ASICs

2.5 V to 3.3 V I/O and 1.5 V core supply
12 mm × 12 mm 121-lead CSPBGA, speed grade 115 MHz, or
13 mm × 13 mm 144-lead CSPBGA, speed grade 135 MHz, or
13 mm × 13 mm 144-lead CSPBGA, speed grade 150 MHz

AL/ NTSC, SMPTE274M, SMPTE293M (525p),

connection to most 16-/32-bit microcontrollers

ADV202

APPLICATIONS

Networked video and image distribution systems
Wireless video and image distribution
Image archival/retrieval
Digital CCTV and surveillance systems
Digital cinema systems
Professional video editing and recording
Digital still cameras
Digital camcorders

GENERAL DESCRIPTION

The ADV202 is a single-chip JPEG2000 codec targeted for
video and high bandwidth image compression applications that
can benefit from the enhanced quality and feature set provided
by the JPEG2000 (J2K)—ISO/IEC15444-1 image compression
standard. The part implements the computationally intensive
operations of the JPEG2000 image compression standard as well
as providing fully compliant code-stream generation for most
applications.

The ADV202’s dedicated video port provides glueless connection

o common digital video standards such as ITU.R-BT656,

t
SMPTE125M, SMPTE293M (525p), ITU.R-BT1358 (625p),
SMPTE274M (1080i), or SMPTE296M (720p). A variety of other
high speed, synchronous pixel and video formats can also be sup­ported using the programmable framing and validation signals.

(continued on Page 4)

FUNCTIONAL BLOCK DIAGRAM

PIXEL I/F

HOST I/F

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

PIXEL I/F

EXTERNAL
DMA CTRL

PIXEL FIFO
CODE FIF O

ATTR FIFO

ADV202

WAVELET

ENGINE

INTERNAL BUS AND DM A ENGINE

EMBEDDED

RISC

PROCESSOR

SYSTEM

Figure 1.

EC1 EC2

RAM ROM

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

EC3

04723-001

ADV202

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

General Description ......................................................................... 4

JPEG2000 Feature Support.......................................................... 4

Specifications..................................................................................... 5

Supply Voltages and Current ...................................................... 5

Input/Output Specifications........................................................ 5

Clock and

Normal Host Mode—Read Operation ...................................... 7

Normal Host Mode—Write Operation ..................................... 8

DREQ

DREQ

External DMA Mode—FIFO Write, Burst Mode .................. 13

External DMA Mode—FIFO Read, Burst Mode ................... 14

Streaming Mode (JDATA)—FIFO Read/Write...................... 16

VDATA Mode Timing............................................................... 17

Raw Pixel Mode Timing............................................................ 18

Absolute Maximum Ratings.......................................................... 19

Thermal Resistance .................................................................... 19

ESD Caution................................................................................ 19

Pin BGA Assignments and Function Descriptions ................... 20

Pin BGA Assignments ...............................................................20

Pin Function Descriptions ........................................................ 23

Theory of Operation ...................................................................... 26

Wavelet Engine ...........................................................................26

Entropy Codecs........................................................................... 26

RESET

Specifications................................................ 6

DACK

/

DMA Mode—Single FIFO Write Operation.. 9

/

DMA Mode—Single FIFO Read Operation. 11

DACK

Embedded Processor System.................................................... 26

Memory System.......................................................................... 26

Internal DMA Engine................................................................ 26

ADV202 Interface .......................................................................... 27

Video Interface (VDATA Bus).................................................. 27

Host Interface (HDATA Bus) ................................................... 27

Direct and Indirect Registers.................................................... 27

Control Access Registers........................................................... 27

Pin Configuration and Bus Sizes/Modes ................................ 28

Stage Register.............................................................................. 28

JDATA Mode............................................................................... 28

External DMA Engine ............................................................... 28

Internal Registers............................................................................ 29

Direct Registers........................................................................... 29

Indirect Registers........................................................................ 30

PLL ............................................................................................... 31

Hardware Boot............................................................................ 31

Video Input Formats...................................................................... 32

Applications..................................................................................... 34

Encode—Multichip Mode......................................................... 34

Decode—Multichip Master/Slave ............................................ 35

Digital Still Camera/Camcorder .............................................. 35

Encode/Decode SDTV Video Application............................. 36

ASIC Application (32-Bit Host/32-Bit ASIC)......................... 37

HIPI (Host Interface—Pixel Interface) ................................... 38

JDATA Interface ......................................................................... 38

Outline Dimensions....................................................................... 39

Ordering Guide .......................................................................... 40

Rev. C | Page 2 of 40

ADV202

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REVISION HISTORY

11/06—Rev. B to Rev. C

Deleted ANC FIFO References ........................................Universal

Changes to Features..........................................................................1

Changes to Figure 1...........................................................................1

Changes to JPEG2000 Feature Support Section............................4

Changes to Figure 8.........................................................................10

Changes to Figure 10 ......................................................................11

Changes to Figure 12 ......................................................................12

Changes to External DMA Mode—FIFO Write,

Burst Mode Section.........................................................................13

Changes to External DMA Mode—FIFO Read,

Burst Mode Section.........................................................................13

Changes to Table 11 ........................................................................17

Changes to Figure 22 ......................................................................18

Deleted SPI Port Timing Section ..................................................18

Added Absolute Maximum Ratings Section ...............................19

Changes to Pin BGA Assignments and Function

Descriptions Section .......................................................................20

Changes to ADV202 Interface Section.........................................27

Changes to Table 19........................................................................29

Changes to Indirect Registers Section..........................................30

Changes to PLL Section..................................................................31

Changes to Table 23........................................................................31

Changes to Video Input Formats Section .................................... 32

Changes to Figure 24 ......................................................................34

Changes to Figure 26 ......................................................................35

Changes to Ordering Guide...........................................................40

1/05—Rev. A to Rev. B

U

pdated Outline Dimensions........................................................39

12/04—Rev. 0 to Rev. A

hanges to Features .......................................................................... 1

C

Changes to Table 2............................................................................ 4

Changes to Table 16........................................................................24

Changes to Table 23........................................................................32

7/04—Revision 0: Initial Version

Rev. C | Page 3 of 40

ADV202

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GENERAL DESCRIPTION

(continued from Page 1)

The ADV202 can process images at a rate of 40 MSPS in
r

eversible mode and at higher rates when used in irreversible
mode. The ADV202 contains a dedicated wavelet transform
engine, three entropy codecs, an on-board memory system, and
an embedded RISC processor that can provide a complete
JPEG2000 compression/decompression solution.

The wavelet processor supports the 9/7 irreversible wavelet
t

ransform and the 5/3 wavelet transform in reversible and
irreversible modes. The entropy codecs support all features in
the JPEG2000 Part 1 specification, except Maxshift ROI.

The ADV202 operates on a rectangular array of pixel samples
cal

led a tile. A tile can contain a complete image, up to the
maximum supported size, or some portion of an image. The
maximum horizontal tile size supported depends on the wavelet
transform selected and the number of samples in the tile.
Images larger than the ADV202’s maximum tile size can be
broken into individual tiles and then sent sequentially to the
chip while still maintaining a single, fully compliant JPEG2000
code stream for the entire image.

JPEG2000 FEATURE SUPPORT

The ADV202 supports a broad set of features that are included
in Part 1 of the JPEG2000 standard (ISO/IEC 15444). See

Getting Started with ADV202 for information on the JPEG2000

eatures that the ADV202 currently supports.

f

Depending on the particular application requirements, the
AD

V202 can provide varying levels of JPEG2000 compression
support. It can provide raw code-block and attribute data
output, which allow the host software to have complete control
over the generation of the JPEG2000 code stream and other
aspects of the compression process such as bit-rate control.
Otherwise, the ADV202 can create a complete, fully compliant
JPEG2000 code stream (.j2c) and enhanced file formats such as
.jp2 and .j2c. See
on the formats that the ADV202 currently supports.

Application notes and other ADV202 support documents can
be ac

cessed over the ADV202 product page at:

• http://www.analog.com/ADV202Notes or from

• ftp://ftp.analog.com/pub/Digital_Imaging/ADV202_FTP_s

te_contents_3.html

i

Getting Started with ADV202 fo

r information

Rev. C | Page 4 of 40

ADV202

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SPECIFICATIONS

SUPPLY VOLTAGES AND CURRENT

Table 1.

Parameter Description Min Typ Max Unit

VDD DC Supply Voltage, Core 1.425 1.5 1.575 V
IOVDD DC Supply Voltage, I/O 2.375 3.3 3.63 V
PLLVDD DC Supply Voltage, PLL 1.425 1.5 1.575 V
V

Input Range −0.3 V

INPUT

Temp Operating Ambient Temperature Range in Free Air −40 +25 +85 °C
IDD Static Current
Dynamic Current, Core (JCLK Frequency = 150 MHz)

1

2

300 mA

570 mA
Dynamic Current, Core (JCLK Frequency = 108 MHz) 420 mA
Dynamic Current, Core (JCLK Frequency = 81 MHz) 325 mA
Dynamic Current, I/O 20 mA
Dynamic Current, PLL 2.6 mA

1

No clock or I/O activity.

2

ADV202-150 only.

INPUT/OUTPUT SPECIFICATIONS

+ 0.3 V

DDI/O

Table 2.

Parameter Description Test Conditions Min Typ Max Unit

V

High Level Input Voltage VDD = max 2.2 V

IH (3.3 V)

V

High Level Input Voltage VDD = max 1.9 V

IH (2.5 V)

V

IL (3.3 V, 2.5 V)

V

OH (3.3 V)

V

OH (2.5 V)

V

OL (3.3 V, 2.5 V)

Low Level Input Voltage VDD = min 0.6 V

High Level Output Voltage VDD = min, IOH = −0.5 mA 2.4 V

High Level Output Voltage VDD = min, IOH = −0.5 mA 2.0 V

Low Level Output Voltage VDD = min, IOL = 2 mA 0.4 V
IIH High Level Input Current VDD = max, VIN = VDD 1.0 μA
IIL Low Level Input Current VDD = max, VIN = 0 V 1 μA
I

High Level Three-State Leakage Current VDD = max, VIN = VDD 1.0 μA

OZH

I

Low Level Three-State Leakage Current VDD = max, VIN = 0 V 1.0 μA

OZL

CI Input Pin Capacitance 8 pF
CO Output Pin Capacitance 8 pF

Rev. C | Page 5 of 40

ADV202

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CLOCK AND RESET SPECIFICATIONS

Table 3.

Parameter Description Min Typ Max Unit

t

MCLK1 Period 13.3 100 ns

MCLK

t

MCLK Width Low 6 ns

MCLKL

t

MCLK Width High 6 ns

MCLKH

t

VCLK Period 13.4 50 ns

VCLK

t

VCLK Width Low 5 ns

VCLKL

t

VCLK Width High 5 ns

VCLKH

t

RST

1

For a definition of MCLK, see the PLL section.

MCLK

RESET

Width Low

t

MCLKL

t

VCLKL

t

MCLK

t

VCLK

5 MCLK cycles

t

MCLKH

t

VCLKH

VCLK

Figure 2. Input Clock

04723-010

Rev. C | Page 6 of 40

ADV202

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NORMAL HOST MODE—READ OPERATION

Table 4.

Parameter Description Min Typ Max Unit

t

[dir]

ACK

t

[indir]

ACK

t

[dir] Read Access Time, Direct Registers 5 1.5 × JCLK + 7.0 ns

DRD

t

[indir] Read Access Time, Indirect Registers 10.5 × JCLK 15.5 × JCLK + 7.0 ns

DRD

t

Data Hold 2 8.5 ns

HZRD

tSC

to ACK, Direct Registers and FIFO Accesses

RD

to ACK, Indirect Registers

RD

to RD Setup

CS

5 1.5 × JCLK

10.5 × JCLK 15.5 × JCLK + 7.0 ns

0 ns

tSA Address Setup 2 ns
tHC

CS

Hold

0 ns
tHA Address Hold 2 ns
tRH Read Inactive Pulse Width 2.5 JCLK
tRL Read Active Pulse Width 2.5 JCLK
t

Read Cycle Time, Direct Registers 5.0 JCLK

RCYC

1

For a definition of JCLK, see the PLL section.

1

+ 7.0 ns

ADDR

CS

RD

ACK

HDATA

t

SA

t

SC

t

RL

t

ACK

t

DRD

VALID

t

HA

t

HC

t

RCYC

t

RH

t

HZRD

04723-011

Figure 3. Normal Host Mode—Read Operation

Rev. C | Page 7 of 40

ADV202

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NORMAL HOST MODE—WRITE OPERATION

Table 5.

Parameter Description Min Typ Max Unit

t

(Direct)

ACK

t

(Indirect)

ACK

to ACK, Direct Registers and FIFO Accesses

WE

to ACK, Indirect Registers

WE

5 1.5 × JCLK

5 2.5 × JCLK + 7.0 ns

tSD Data Setup 3.0 ns
tHD Data Hold 1.5 ns
tSA Address Setup 2 ns
tHA Address Hold 2 ns
tSC

tHC
t

WH

to WE Setup

CS

Hold

CS
Write Inactive Pulse Width (Minimum Time Until Next WE

Pulse)

0 ns
0 ns

2.5 JCLK

tWL Write Active Pulse Width 2.5 JCLK
t

Write Cycle Time 5 JCLK

WCYC

1

For a definition of JCLK, see the PLL section.

ADDR

t

SA

t

HA

1

+ 7.0 ns

CS

WE

ACK

HDATA

t

SC

t

WL

t

ACK

t

SD

Figure 4. Normal Host Mode—Write Operation

VALID

t

HC

t

WCYC

t

WH

t

HD

04723-012

Rev. C | Page 8 of 40

ADV202

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DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION

Table 6.

Parameter Description Min Typ Max Unit

DREQ
t

DREQ

t

WE

tSU
tHD

1

DREQ Pulse Width

PULSE

DACK Assert to Subsequent DREQ Delay

SU

WE

Data to DACK
Data to DACK

to DACK Setup

Deassert Setup

Deassert Hold
DACKLO DACK Assert Pulse Width
DACKHI DACK Deassert Pulse Width
t

HD

WE

Hold After DACK Deassert

WE

WFSRQ WE Assert to FSRQ Deassert (FIFO Full)
t

RTN

DREQ

1

Applies to assigned DMA channel, if EDMOD0 or EDMOD1[14:11] is programmed to a value that is not 0. Pulse width depends on the value programmed

2

For a definition of JCLK, see the PLL section.

to DREQ Deassert (DR × PULS = 0)

DACK

1 15 JCLK cycles

2.5 3.5 × JCLK + 7.5 ns JCLK cycles

0 ns

2 ns
2 ns
2 JCLK cycles
2 JCLK cycles
0 ns

1.5 2.5 × JCLK + 7.5 ns JCLK cycles

2.5 3.5 × JCLK + 7.5 ns JCLK cycles

DREQ

DREQ

DACK

WE

HDATA

PULSE

t

WESU

Figure 5. Single Write for

DACK

t

t

DREQ

LO

SU

DACK

t

HD

HI

DREQ

DACK

/

DMA Mode for Assigned DMA Channel

t

WEHD

3210

04723-013

(EDMOD0/EDMOD1[14:11] NOT Programmed to a Value of 0000)

t

DREQRTN

DREQ

DACK

HI

t

HD

0 1 2

DACK

DREQ

/

DMA Mode for Assigned DMA Channel

t

WEHD

04723-014

DACK

WE

HDATA

DACK

LO

t

WESU

t

SU

Figure 6. Single Write for

(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)

2

Rev. C | Page 9 of 40

ADV202

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DREQ

DREQ

DACK

WEFB

HDATA

PULSE

t

WESU

Figure 7. Fly-By DMA Mode—Single Write Cycle (

t

DREQ

DACK

DACK

LO

t

SU

HI

t

HD

0 1 2

DREQ

t

WEHD

Pulse Width Is Programmable)

04723-015

FSC0

WE

WFSRQ

FSRQ0

HDATA

FIFO NOT FULL

0 1 2

t

HD

t

SU

Figure 8. DCS DMA Mode—Single Write Access (Rev. 0.1 and Higher)

FIFO FULL

NOT WRITTENTO FIFO

04723-016

Rev. C | Page 10 of 40

ADV202

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/

DREQ

Table 7.

Parameter Description Min Typ Max Unit

DREQ

PULSE

t

DREQ

t

SU

RD

tRD

t

Data Hold 1.5 ns

HD

DACKLO DACK Assert Pulse Width
DACKHI DACK Deassert Pulse Width
t

HD

RD

FSRQ RD Assert to FSRQ Deassert (FIFO Empty)

RD

RTN

DREQ

1

Applies to assigned DMA channel, if EDMOD0 or EDMOD1[14:11] is programmed to a nonzero value.

2

For a definition of JCLK, see the PLL section.

DMA MODE—SINGLE FIFO READ OPERATION

DACK

DREQ Pulse Width

1

DACK Assert to Subsequent DREQ Delay

RD to DACK Setup

DACK to Data Valid

RD Hold After DACK Deassert

DACK to DREQ Deassert (DR × PULS = 0)

DREQ

PULSE

DREQ

DACK

t

DREQ

LO

DACK

1 15 JCLK cycles

2.5 3.5 × JCLK + 7.5 ns JCLK cycles

0 ns

2.5 11 ns

2 JCLK cycles
2 JCLK cycles
0 ns

1.5 2.5 × JCLK + 7.5 ns JCLK cycles

2.5 3.5 × JCLK + 7.5 ns JCLK cycles t

HI

2

DACK

t

RDSU

RD

t

RD

HDATA 0 1 2

Figure 9. Single Read for

t

HD

DREQ

DACK

/

DMA Mode for Assigned DMA Channel

t

RDHD

04723-018

(EDMOD0/EDMOD1[14:11] Not Programmed to a Value of 0000)

t

DREQRTN

DREQ

DACK

DACK

LO

DACK

t

RDSU

RD

t

RD

HDATA 0 1 2

Figure 10. Single Read for

(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)

HI

t

HD

DREQ

DACK

/

DMA Mode for Assigned DMA Channel

t

RDHD

4723-019

Rev. C | Page 11 of 40

ADV202

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DREQ

DACK

RDFB

HDATA

DREQ

t

RDSU

PULSE

t

DREQ

DACK

DACK

LO

t

RD

HI

t

HD

0 1 2

t

RDHD

04723-020

Figure 11. Fly-By DMA Mode—Single Read Cycle

DREQ

(

Pulse Width Is Programmable)

FCS0

RD

RDFSRQ

FSRQ0

HDATA

FIFO NOT EMPTY

t

t

RD

HD

0 1

Figure 12. DCS DMA Mode—Single Read Access (Rev. 0.1 and Higher)

FIFO EMPTY

04723-021

Rev. C | Page 12 of 40