Complete suite of level shifters
Eight inverting and three complementary level shifters for
LCD timing
High voltage edge detector
Integrated low offset buffer for VCOM drives high capacitive
loads
MUXed input, low offset buffer for 2-level precharge drives
high capacitive loads
High current buffer for precharge provides high current
drive into large capacitive loads
Low power dissipation: 576 mW
Available in 48-lead 7 mm × 7 mm LFCSP E-pad
PRODUCT DESCRIPTION
The ADSY8401 provides fast, 3 V to 15 V level shifters for LCD
panel timing signals. An integrated low offset analog buffer is
capable of driving the high capacitive loads. A 2:1 MUX input,
low offset buffer simplifies application of 2-level precharge
signals. A high current buffer provides high slew rates for large
capacitive loads.
The ADSY8401 is fabricated on ADI’s fast, 26 V XFHV process,
providing fast input logic, high voltage level shifters, and
precision drive amplifiers on the same chip.
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DI9
DI10
DI11
DTCTI
AMPI
SEL
MUXA
MUXB
ADSY8401
FUNCTIONAL BLOCK DIAGRAM
DVCCAVCCLAVCC
ADSY8401
8
3
R
S
+1
+1
8
3
3
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DO9T
DO10T
DO11T
DO9C
DO10C
DO11C
DTCTO
AMPO
MUXO
The ADSY8401 dissipates 576 mW nominal static power.
The ADSY8401 is offered in a 48-lead 7 mm × 7 mm LFCSP
E-pad package and operates over the commercial temperature
range of 0°C to 85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.
At 25°C, AVCC = AVCCL = 15.5 V, DVCC = 3.3 V, TA min = 0°C, TA max = 85°C, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
Amp Section
INPUT/OUTPUT CHARACTERISTICS
Voltage Range
V
H
V
L
Output Voltage Grounded Mode GSW = LOW 45 mV
Input Current 100 nA
Output Current 20 mA
Output Offset Voltage VAMPI = 6 V, TA = 25°C 1.5 8 mV
Output Offset Voltage VAMPI = 6 V, TA min to TA max 11 mV
PSRR AVCC ± 10%, TA min to TA max 0.1 mV/V
Gain Error
OUTPUT DYNAMIC PERFORMANCE
−3 dB Bandwidth (Small Signal) VO = 0.25 V p-p 5.2 MHz
Slew Rate 13 V/µs
Settling Time to 0.5% TA min to TA max 0.5 1 µs
Overshoot 0.05 %
MUX Section
INPUT/OUTPUT CHARACTERISTICS
Voltage Range
V
H
V
L
Output Voltage Grounded Mode GSW = LOW 45 mV
Input Current
II MUXA, MUXB 100 nA
Output Current 20 mA
Output Offset Voltage VMUXA, B = 7.5 V, TA = 25°C 1.5 8 mV
Output Offset Voltage VMUXA, B = 7.5 V, TA min to TA max 11 mV
PSRR AVCC ± 10%, TA min to TA max 0.1 mV/V
Gain Error
SEL INPUT CHARACTERISTICS
IIH SEL 0.05 µA
IIL SEL −0.7 µA
VTH SEL 1.65 V
VIH SEL 2 V
VIL SEL 0.8 V
OUTPUT DYNAMIC PERFORMANCE VO = 5 V step, CL = 1 nF
−3 dB Bandwidth (Small Signal) VO = 0.25 V p-p 5.2 MHz
Slew Rate 13 V/µs
Settling Time to 0.5% TA min to TA max 0.5 1 µs
Overshoot 0.05 %
OUTPUT DYNAMIC PERFORMANCE VO = 5 V step, CL = 15 pF
−3 dB Bandwidth (Small Signal) VO = 0.25 V p-p 27 MHz
Slew Rate 13 V/µs
Settling Time to 0.5% TA min to TA max 0.4 0.7 µs
Overshoot
AVCC − V
H
1.5 2.5 V
VL − AGND 1.1 1.5 V
VAMPI = 3 V to 10 V, TA min to TA max
TA min to TA max, VO = 5 V step, CL = 1 nF
0.07 0.12 %
AVCC − V
H
1.5 2.5 V
VL − AGND 1.1 1.5 V
VMUXA, B 1.5 V to 12 V, TA min to TA max
0.07 0.12 %
0.1
%
Rev. 0 | Page 3 of 16
ADSY8401
Parameter Conditions Min Typ Max Unit
BFR Section
INPUT/OUTPUT CHARACTERISTICS
Voltage Range
V
H
V
L
Output Voltage Grounded Mode GSW = LOW 90 mV
Input Current 0.3 µA
Output Current 100 mA
Output Offset Voltage BFRI = 7.5 V, TA = 25°C 6 20 mV
Output Offset Voltage BFRI = 7.5 V, TA min to TA max 30 mV
PSRR, TA min to TA max AVCC ± 10% 1 mV/V
Gain Error, TA min to TA max BFRI = 1.5 V to 12 V 0.5 0.65 %
OUTPUT DYNAMIC PERFORMANCE VO = 6 V step, CL = 10 nF
−3 dB Bandwidth (Small Signal) VO = 0.25 V p-p 1.3 MHz
Slew Rate 12 V/µs
Settling Time to 0.5% TA min to TA max 0.7 1 µs
Overshoot 0.3 %
MUX and BFR Sections as NRS Buffer
Settling Time to 0.5% CL = 10 nF 0.9 1.5 µs
Level Shifter Section
LEVEL SHIFTER LOGIC INPUTS
C
IN
I
IH
I
IL
V
IH
V
IL
V
TH
LEVEL SHIFTER OUTPUTS
V
OH
V
OL
LEVEL SHIFTER DYNAMIC PERFORMANCE TA min to TA max