ANALOG DEVICES ADSP-TS203S Service Manual

TigerSHARC

OUT

HOST

MULTI-

PROC

C-BUS

ARB

DATA

LINK PORTS

JTAG PORT

EXTERNAL

PORT

ADDR

SOC BUS

DMA

JTAG

SDRAM

CTRL

EXT DMA

REQ

J-BUS DATA

IAB

BTB

ADDR

FETCH

PROGRAM

SEQUEN CER

COMPUTATIONAL BLOCKS

J-BUS ADDR

K-BUS DATA

K-BUS ADDR

I-BUS DATA

I-BUS ADDR

S-BUS DATA

S-BUS ADDR

INTEGER

KALU

INTEGER

JALU

32-BIT × 32-BIT

DATA ADDRESS GENERATION

FILE

32-BIT × 32-BIT

MULALUSHIFT

DAB

128

DAB

128

MEMORY BLOCKS

4M BITS INTERNAL MEMORY

4 × CROSSBAR CONNECT

(PAGE CACHE)

ADADA

SOC

I/F

FILE

32-BIT × 32-BIT

MUL ALU SHIFT

OUT

CTRL

128

32-BIT × 32-BIT

Embedded Processor

ADSP-TS203S

KEY FEATURES

500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory 25 mm × 25 mm (576-ball) thermally enhanced ball grid array

package

Dual-computation blocks—each containing an ALU, a multi-

plier, a shifter, and a register file

Dual-integer ALUs, providing data addressing and pointer

manipulation

Single-precision IEEE 32-bit and extended-precision 40-bit

floating-point data formats and 8-, 16-, 32-, and 64-bit fixed-point data formats

Integrated I/O includes 10-channel DMA controller, external

port, two link ports, SDRAM controller, programmable flag pins, two timers, and timer expired pin for system integration

1149.1 IEEE-compliant JTAG test access port for on-chip emulation

On-chip arbitration for glueless multiprocessing

KEY BENEFITS

Provides high performance static superscalar DSP

operations, optimized for large, demanding multiprocessor DSP applications

Performs exceptionally well on DSP algorithm and I/O

benchmarks (see benchmarks in Table 1)

Supports low overhead DMA transfers between internal

memory, external memory, memory-mapped peripherals, link ports, host processors, and other (multiprocessor) DSPs

Eases programming through extremely flexible instruction

set and high-level-language-friendly architecture

Enables scalable multiprocessing systems with low commu-

nications overhead

TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.

Figure 1. Functional Block Diagram

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADSP-TS203S

Key Features ........................................................... 1

Key Benefits ........................................................... 1

General Description ................................................. 3

Dual Compute Blocks ............................................ 4

Data Alignment Buffer (DAB) .................................. 4

Dual Integer ALU (IALU) ....................................... 4

Program Sequencer ............................................... 4

Memory ............................................................. 5

External Port (Off-Chip Memory/Peripherals Interface) . 5

DMA Controller ................................................... 7

Link Ports (LVDS) ................................................ 7

Timer and General-Purpose I/O ............................... 8

Reset and Booting ................................................. 8

Clock Domains .................................................... 8

Filtering Reference Voltage and Clocks ...................... 8

Power Domains .................................................... 9

Development Tools ............................................... 9

Related Signal Chains .......................................... 10

Additional Information ........................................ 10

Pin Function Descriptions ........................................ 11

Strap Pin Function Descriptions ................................ 18

Specifications ........................................................ 20

Operating Conditions ........................................... 20

Electrical Characteristics ....................................... 21

Package Information ............................................ 22

Absolute Maximum Ratings ................................... 22

ESD Sensitivity ................................................... 22

Timing Specifications ........................................... 23

Output Drive Currents ......................................... 34

Test Conditions .................................................. 35

Environmental Conditions .................................... 38

576-Ball BGA_ED Pin Configurations ......................... 39

Outline Dimensions ................................................ 46

Surface Mount Design .......................................... 46

Ordering Guide ..................................................... 47

REVISION HISTORY

5/12—Rev. C to Rev. D

Added model to Ordering Guide ................................ 47

Rev. D | Page 2 of 48 | May 2012

GENERAL DESCRIPTION

ADSP-TS203S

The ADSP-TS203S TigerSHARC processor is an ultrahigh performance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. The processor combines very wide memory widths with dual computation blocks—supporting floating-point (IEEE 32-bit and extended precision 40-bit) and fixed-point (8-, 16-, 32-, and 64-bit) processing—to set a new standard of performance for digital signal processors. The TigerSHARC static superscalar architecture lets the processor execute up to four instructions each cycle, performing 24 fixed-point (16-bit) operations or six floating-point operations.

Four independent 128-bit wide internal data buses, each connecting to the four 1M bit memory banks, enable quad-word data, instruction, and I/O access and provide 28G bytes per second of internal memory bandwidth. Operating at 500 MHz, the ADSP-TS203S processor’s core has a 2.0 ns instruction cycle time. Using its single-instruction, multiple-data (SIMD) features, the processor can perform four billion 40-bit MACS or one billion 80-bit MACS per second. Table 1 shows the processor’s performance benchmarks.

Table 1. General-Purpose Algorithm Benchmarks at 500 MHz

Clock

Benchmark Speed

32-bit algorithm, 1 billion MACS/s peak performance 1K point complex FFT1(Radix2)

64K point complex FFT1(Radix2) 2.8 ms FIR filter (per real tap) 1 ns 0.5 [8 × 8][8 × 8] matrix multiply

(complex, floating-point) 2.8 µs 1399 16-bit algorithm, 4 billion MACS/s peak performance 256 point complex FFT1 (Radix 2) 1.9 µs 928 I/O DMA transfer rate External port 500M bytes/s n/a Link ports (each) 500M bytes/s n/a

Cache preloaded.

18.8 µs 9419

Cycles

13975 44

The ADSP-TS203S processor is code compatible with the other TigerSHARC processors.

The Functional Block Diagram on Page 1 shows the processor’s architectural blocks. These blocks include

• Dual compute blocks, each consisting of an ALU, multiplier, 64-bit shifter, and 32-word register file and associated data alignment buffers (DABs)

• Dual integer ALUs (IALUs), each with its own 31-word register file for data addressing and a status register

• A program sequencer with instruction alignment buffer (IAB) and branch target buffer (BTB)

• An interrupt controller that supports hardware and software interrupts, supports level- or edge-triggers, and supports prioritized, nested interrupts

• Four 128-bit internal data buses, each connecting to the four 1M-bit memory banks

•On-chip DRAM (4M-bit)

• An external port that provides the interface to host processors, multiprocessing space (DSPs), off-chip memorymapped peripherals, and external SRAM and SDRAM

• A 10-channel DMA controller

• Two full-duplex LVDS link ports

• Two 64-bit interval timers and timer expired pin

• An 1149.1 IEEE-compliant JTAG test access port for onchip emulation

The TigerSHARC uses a Static Superscalar

architecture. This architecture is superscalar in that the ADSP-TS203S processor’s core can execute simultaneously from one to four 32-bit instructions encoded in a very large instruction word (VLIW) instruction line using the processor’s dual compute blocks. Because the processor does not perform instruction reordering at runtime—the programmer selects which operations will execute in parallel prior to runtime—the order of instructions is static.

With few exceptions, an instruction line, whether it contains one, two, three, or four 32-bit instructions, executes with a throughput of one cycle in a 10-deep processor pipeline.

For optimal processor program execution, programmers must follow the processor’s set of instruction parallelism rules when encoding an instruction line. In general, the selection of instructions that the processor can execute in parallel each cycle depends both on the instruction line resources each instruction requires and on the source and destination registers used in the instructions. The programmer has direct control of three core components—the IALUs, the compute blocks, and the program sequencer.

The ADSP-TS203S processor, in most cases, has a two-cycle execution pipeline that is fully interlocked, so—whenever a computation result is unavailable for another operation dependent on it—the processor automatically inserts one or more stall cycles as needed. Efficient programming with dependency-free instructions can eliminate most computational and memory transfer data dependencies.

In addition, the processor supports SIMD operations two ways—SIMD compute blocks and SIMD computations. The programmer can load both compute blocks with the same data (broadcast distribution) or different data (merged distribution).

Static Superscalar is a trademark of Analog Devices, Inc.

Rev. D | Page 3 of 48 | May 2012

ADSP-TS203S

DUAL COMPUTE BLOCKS

The ADSP-TS203S processor has compute blocks that can execute computations either independently or together as a single-instruction, multiple-data (SIMD) engine. The processor can issue up to two compute instructions per compute block each cycle, instructing the ALU, multiplier, or shifter to perform independent, simultaneous operations. Each compute block can execute eight 8-bit, four 16-bit, two 32-bit, or one 64-bit SIMD computations in parallel with the operation in the other block. These computation units support IEEE 32-bit single-precision floating-point, extended-precision 40-bit floating point, and 8-, 16-, 32-, and 64-bit fixed-point processing.

The compute blocks are referred to as X and Y in assembly syntax, and each block contains three computational units—an ALU, a multiplier, a 64-bit shifter—and a 32-word register file.

• Register File—each compute block has a multiported 32-word, fully orthogonal register file used for transferring data between the computation units and data buses and for storing intermediate results. Instructions can access the registers in the register file individually (word-aligned), in sets of two (dual-aligned), or in sets of four (quad-aligned).

• ALU—the ALU performs a standard set of arithmetic operations in both fixed- and floating-point formats. It also performs logic and permute operations.

• Multiplier—the multiplier performs both fixed- and floating-point multiplication and fixed-point multiply and accumulate.

• Shifter—the 64-bit shifter performs logical and arithmetic shifts, bit and bit stream manipulation, and field deposit and extraction operations.

Using these features, the compute blocks can

• Provide 8 MACS per cycle peak and 7.1 MACS per cycle sustained 16-bit performance and provide 2 MACS per cycle peak and 1.8 MACS per cycle sustained 32-bit performance (based on FIR)

• Execute six single-precision floating-point or execute 24 fixed-point (16-bit) operations per cycle, providing 3G FLOPS or 12.0G/s regular operations performance at 500 MHz

• Perform two complex 16-bit MACS per cycle

DATA ALIGNMENT BUFFER (DAB)

The DAB is a quad-word FIFO that enables loading of quadword data from nonaligned addresses. Normally, load instructions must be aligned to their data size so that quad words are loaded from a quad-aligned address. Using the DAB significantly improves the efficiency of some applications, such as FIR filters.

DUAL INTEGER ALU (IALU)

The processor has two IALUs that provide powerful address generation capabilities and perform many general-purpose integer operations. The IALUs are referred to as J and K in assembly syntax and have the following features:

• Provide memory addresses for data and update pointers

• Support circular buffering and bit-reverse addressing

• Perform general-purpose integer operations, increasing programming flexibility

• Include a 31-word register file for each IALU

As address generators, the IALUs perform immediate or indirect (pre- and post-modify) addressing. They perform modulus and bit-reverse operations with no constraints placed on memory addresses for the modulus data buffer placement. Each IALU can specify either a single-, dual-, or quad-word access from memory.

The IALUs have hardware support for circular buffers, bit reverse, and zero-overhead looping. Circular buffers facilitate efficient programming of delay lines and other data structures required in digital signal processing, and they are commonly used in digital filters and Fourier transforms. Each IALU provides registers for four circular buffers, so applications can set up a total of eight circular buffers. The IALUs handle address pointer wraparound automatically, reducing overhead, increasing performance, and simplifying implementation. Circular buffers can start and end at any memory location.

Because the IALU’s computational pipeline is one cycle deep, in most cases integer results are available in the next cycle. Hardware (register dependency check) causes a stall if a result is unavailable in a given cycle.

PROGRAM SEQUENCER

The ADSP-TS203S processor’s program sequencer supports:

• A fully interruptible programming model with flexible programming in assembly and C/C++ languages; handles hardware interrupts with high throughput and no aborted instruction cycles

• A 10-cycle instruction pipeline—four-cycle fetch pipe and six-cycle execution pipe—computation results available two cycles after operands are available

• Supply of instruction fetch memory addresses; the sequencer’s instruction alignment buffer (IAB) caches up to five fetched instruction lines waiting to execute; the program sequencer extracts an instruction line from the IAB and distributes it to the appropriate core component for execution

• Management of program structures and program flow determined according to JUMP, CALL, RTI, RTS instructions, loop structures, conditions, interrupts, and software exceptions

• Branch prediction and a 128-entry branch target buffer (BTB) to reduce branch delays for efficient execution of conditional and unconditional branch instructions and zero-overhead looping; correctly predicted branches occur with zero overhead cycles, overcoming the five-to-nine stage branch penalty

• Compact code without the requirement to align code in memory; the IAB handles alignment

Rev. D | Page 4 of 48 | May 2012

ADSP-TS203S

Interrupt Controller

The processor supports nested and nonnested interrupts. Each interrupt type has a register in the interrupt vector table. Also, each has a bit in both the interrupt latch register and the interrupt mask register. All interrupts are fixed as either levelsensitive or edge-sensitive, except the IRQ3–0 rupts, which are programmable.

The processor distinguishes between hardware interrupts and software exceptions, handling them differently. When a software exception occurs, the processor aborts all other instructions in the instruction pipe. When a hardware interrupt occurs, the processor continues to execute instructions already in the instruction pipe.

hardware inter-

Flexible Instruction Set

The 128-bit instruction line, which can contain up to four 32-bit instructions, accommodates a variety of parallel operations for concise programming. For example, one instruction line can direct the processor to conditionally execute a multiply, an add, and a subtract in both computation blocks while it also branches to another location in the program. Some key features of the instruction set include:

• Algebraic assembly language syntax

• Direct support for all DSP, imaging, and video arithmetic types

• Eliminates toggling hardware modes because modes are supported as options (for example, rounding, saturation, and others) within instructions

• Branch prediction encoded in instruction; enables zerooverhead loops

• Parallelism encoded in instruction line

• Conditional execution optional for all instructions

• User-defined partitioning between program and data memory

MEMORY

The processor’s internal and external memory is organized into a unified memory map, which defines the location (address) of all elements in the system, as shown in Figure 2.

The memory map is divided into four memory areas—host space, external memory, multiprocessor space, and internal memory—and each memory space, except host memory, is subdivided into smaller memory spaces.

The ADSP-TS203S processor internal memory has 4M bits of on-chip DRAM memory, divided into four blocks of 1M bits (32K words × 32 bits). Each block—M0, M2, M4, and M6—can store program instructions, data, or both, so applications can configure memory to suit specific needs. Placing program instructions and data in different memory blocks, however, enables the processor to access data while performing an instruction fetch. Each memory segment contains a 128K bit cache to enable single-cycle accesses to internal DRAM.

The four internal memory blocks connect to the four 128-bit wide internal buses through a crossbar connection, enabling the processor to perform four memory transfers in the same cycle. The processor’s internal bus architecture provides a total memory bandwidth of 28G bytes per second, allowing the core and I/O to access eight 32-bit data-words and four 32-bit instructions each cycle. Additional features are:

• Processor core and I/O access to different memory blocks in the same cycle

• Processor core access to three memory blocks in parallel— one instruction and two data accesses

• Programmable partitioning of program and data memory

• Program access of all memory as 32-, 64-, or 128-bit words—16-bit words with the DAB

EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE)

The ADSP-TS203S processor’s external port provides the processor’s interface to off-chip memory and peripherals. The 4G word address space is included in the processor’s unified address space. The separate on-chip buses—four 128-bit data buses and four 32-bit address buses—are multiplexed at the SOC interface and transferred to the external port over the SOC bus to create an external system bus transaction. The external system bus provides a single 32-bit data bus and a single 32-bit address bus. The external port supports data transfer rates of 500M bytes per second over the external bus.

The external bus is configured for 32-bit, little-endian operations. Unlike the ADSP-TS201, the ADSP-TS203S processor’s external port cannot support 64-bit operations; the external bus width control bits (Bits 21-19) must = 0 in the SYSCON register—all other values are illegal for the ADSP-TS203S. Because the external port is restricted to 32 bits on the ADSP-TS203S processor, there are a number of pinout differences between the ADSP-TS203S and the ADSP-TS201 processors.

The external port supports pipelined, slow, and SDRAM protocols. Addressing of external memory devices and memorymapped peripherals is facilitated by on-chip decoding of high order address lines to generate memory bank select signals.

The ADSP-TS203S processor provides programmable memory, pipeline depth, and idle cycle for synchronous accesses, and external acknowledge controls to interface to pipelined or slow devices, host processors, and other memory-mapped peripherals with variable access, hold, and disable time requirements.

Host Interface

The ADSP-TS203S processor provides an easy and configurable interface between its external bus and host processors through the external port. To accommodate a variety of host processors, the host interface supports pipelined or slow protocols for processor access of the host as slave or pipelined for host access of the ADSP-TS203S processor as slave. Each protocol has programmable transmission parameters, such as idle cycles, pipe depth, and internal wait cycles.

Rev. D | Page 5 of 48 | May 2012

ADSP-TS203S

RESERVED

INTERNAL REGISTERS(UREGS)

INTERNAL MEMORYBLOCK 4

INTERNAL MEMORY BLO CK 2

INTERNAL MEMORY BLO CK 0

0x0 3FFF FFF

0x001E0000

0x001E03FF

0x000C7FFF

0x0 00C 0000

0x 00087 FFF

0x00080000

0x 00047 FFF

0x00040000

0x 00007 FFF

0 x000 00000

INTERNAL SPACE

PROCESSOR ID 7

PROCESSOR ID 6

PROCESSOR ID 5

PROCESSOR ID 4

PROCESSOR ID 3

PROCESSOR ID 2

PROCESSOR ID 1

PROCESSOR ID 0

BROADCAS T

HOST (MS H )

BANK1(MS1)

BANK0(MS0)

MSSD BANK 0 (MS S D0)

INTE RNAL MEMORY

0x50000000

0 x4000 0000

0x38000000

0x30000000

0x2C000000

0x28000000

0x24000000

0x20000000

0x1C000000

0x18000000

0x14000000

0x10000000

0x0C000000

0x03FFFFFF

0x00000000

0xFFFFFFFF

EACH IS A COPY

OF INTERNAL SPACE

RESERVED

INTERNAL MEMORYBLOCK 6

RESERVED

SOC REGISTERS (UREGS)

0x 001F00 00

0 x001F03 FF

MSSD BANK 1 (MS S D1)

MSS D BANK 2 (MS SD2)

MSSD BANK 3 (MS S D3)

0x60000000

0x70000000

0x80000000

RE SE RV E D

0x54000000

0 x4400 0000

0x64000000

0x74000000

RESERVED

The host interface supports burst transactions initiated by a host processor. After the host issues the starting address of the burst and asserts the BRST address internally while the host continues to assert BRST

signal, the processor increments the

The host interface provides a deadlock recovery mechanism that enables a host to recover from deadlock situations involving the processor. The BOFF mechanism. When the host asserts BOFF off the current transaction and asserts HBG

signal provides the deadlock recovery

, the processor backs

and relinquishes the

external bus.

The host can directly read or write the internal memory of the ADSP-TS203S processor, and it can access most of the processor registers, including DMA control (TCB) registers. Vector interrupts support efficient execution of host commands.

Multiprocessor Interface

The processor offers powerful features tailored to multiprocessing processor systems through the external port and link ports. This multiprocessing capability provides the highest bandwidth for interprocessor communication, including

• Up to eight DSPs on a common bus

• On-chip arbitration for glueless multiprocessing

• Link ports for point-to-point communication

The external port and link ports provide integrated, glueless multiprocessing support.

GLOBAL SPACE

Figure 2. ADSP-TS203S Memory Map

Rev. D | Page 6 of 48 | May 2012

ADSP-TS203S

The external port supports a unified address space (see Figure 2) that enables direct interprocessor accesses of each ADSPTS203S processor’s internal memory and registers. The processor’s on-chip distributed bus arbitration logic provides simple, glueless connection for systems containing up to eight ADSP-TS203S processors and a host processor. Bus arbitration has a rotating priority. Bus lock supports indivisible readmodify-write sequences for semaphores. A bus fairness feature prevents one processor from holding the external bus too long.

The processor’s two link ports provide a second path for interprocessor communications with throughput of 1G byte per second. The cluster bus provides 500M bytes per second throughput—with a total of 1.5G bytes per second interprocessor bandwidth.

SDRAM Controller

The SDRAM controller controls the processor’s transfers of data to and from external synchronous DRAM (SDRAM) at a throughput of 32 bits per SCLK cycle using the external port and SDRAM control pins.

The SDRAM interface provides a glueless interface with standard SDRAMs—16M bits, 64M bits, 128M bits, 256M bits and 512M bits. The processor supports directly a maximum of four banks of 64M words × 32 bits of SDRAM. The SDRAM interface is mapped in external memory in each processor’s unified memory map.

• External port block transfers. Four dedicated bidirectional DMA channels transfer blocks of data between the processor’s internal memory and any external memory or memory-mapped peripheral on the external bus. Master mode and handshake mode protocols are supported.

• Link port transfers. Four dedicated DMA channels (two transmit and two receive) transfer quad-word data only between link ports and between a link port and internal or external memory. These transfers only use handshake mode protocol. DMA priority rotates between the two receive channels.

• AutoDMA transfers. Two dedicated unidirectional DMA channels transfer data received from an external bus master to internal memory or to link port I/O. These transfers only use slave mode protocol, and an external bus master must initiate the transfer.

The DMA controller provides these additional features:

• Flyby transfers. Flyby operations only occur through the external port (DMA channel 0) and do not involve the processor’s core. The DMA controller acts as a conduit to transfer data from an external I/O device to external SDRAM memory. During a transaction, the processor relinquishes the external data bus; outputs addresses and memory selects (MSSD3–0 IOEN

, and RD/WR strobes; and responds to ACK.

); outputs the IORD, IOWR,

EPROM Interface

The processor can be configured to boot from an external 8-bit EPROM at reset through the external port. An automatic process (which follows reset) loads a program from the EPROM into internal memory. This process uses 16 wait cycles for each read access. During booting, the BMS EPROM chip select signal. The EPROM boot procedure uses DMA Channel 0, which packs the bytes into 32-bit instructions. Applications can also access the EPROM (write flash memories) during normal operation through DMA.

The EPROM or flash memory interface is not mapped in the processor’s unified memory map. It is a byte address space limited to a maximum of 16M bytes (24 address bits). The EPROM or flash memory interface can be used after boot via a DMA.

pin functions as the

DMA CONTROLLER

The ADSP-TS203S processor’s on-chip DMA controller, with 10 DMA channels, provides zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor’s core, enabling DMA operations to occur while the processor’s core continues to execute program instructions.

The DMA controller performs DMA transfers between internal memory, external memory, and memory-mapped peripherals; the internal memory of other DSPs on a common bus, a host processor, or link port I/O; between external memory and external peripherals or link port I/O; and between an external bus master and internal memory or link port I/O. The DMA controller performs the following DMA operations:

• DMA chaining. DMA chaining operations enable applications to automatically link one DMA transfer sequence to another for continuous transmission. The sequences can occur over different DMA channels and have different transmission attributes.

• Two-dimensional transfers. The DMA controller can access and transfer two-dimensional memory arrays on any DMA transmit or receive channel. These transfers are implemented with index, count, and modify registers for both the X and Y dimensions.

LINK PORTS (LVDS)

The processor’s two full-duplex link ports each provide additional four-bit receive and four-bit transmit I/O capability, using low-voltage, differential-signal (LVDS) technology. With the ability to operate at a double data rate—latching data on both the rising and falling edges of the clock—running at 250 MHz, each link port can support up to 250M bytes per second per direction, for a combined maximum throughput of 1G byte per second.

The link ports provide an optional communications channel that is useful in multiprocessor systems for implementing pointto-point interprocessor communications. Applications can also use the link ports for booting.

Each link port has its own triple-buffered quad-word input and double-buffered quad-word output registers. The processor’s core can write directly to a link port’s transmit register and read

Rev. D | Page 7 of 48 | May 2012

ADSP-TS203S

SCLKRATx

SCLK

SPD BI TS,

LCTLx REGISTER

PLL

/CR

CCLK (INSTRUCTION RA TE)

SOCCLK (PERIPHERAL BUS RATE)

LxCLKOUT (LINK OUTPUT RATE)

EXTERNAL INTERFACE

DD_IO

REF

R2 C1 C2

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from a receive register, or the DMA controller can perform DMA transfers through four (two transmit and two receive) dedicated link port DMA channels.

Each link port direction has three signals that control its operation. For the transmitter, LxCLKOUT is the output transmit clock, LxACKI is the handshake input to control the data flow, and the LxBCMPO

output indicates that the block transfer is complete. For the receiver, LxCLKIN is the input receive clock, LxACKO is the handshake output to control the data flow, and the LxBCMPI

input indicates that the block transfer is complete. The LxDATO3–0 pins are the data output bus for the transmitter, and the LxDATI3–0 pins are the input data bus for the receiver.

Applications can program separate error detection mechanisms for transmit and receive operations (applications can use the checksum mechanism to implement consecutive link port transfers), the size of data packets, and the speed at which bytes are transmitted.

TIMER AND GENERAL-PURPOSE I/O

The ADSP-TS203S processor has a timer pin (TMR0E) that generates output when a programmed timer counter has expired, and four programmable general-purpose I/O pins (FLAG3–0) that can function as either single-bit input or output. As outputs, these pins can signal peripheral devices; as inputs, they can provide the test for conditional branching.

Table 2. No Boot, Run from Memory Addresses

Interrupt Address

IRQ0 IRQ1 IRQ2 IRQ3

0x3000 0000 (External Memory) 0x3800 0000 (External Memory) 0x8000 0000 (External Memory) 0x0000 0000 (Internal Memory)

For more information on boot options, see the EE-200: ADSP-TS20x TigerSHARC Processor Boot Loader Kernels Operation on the Analog Devices website (www.analog.com)

CLOCK DOMAINS

The processor uses calculated ratios of the SCLK clock to operate, as shown in Figure 3. The instruction execution rate is equal to CCLK. A PLL from SCLK generates CCLK which is phaselocked. The SCLKRATx pins define the clock multiplication of SCLK to CCLK (see Table 4 on Page 11). The link port clock is generated from CCLK via a software programmable divisor, and the SOC bus operates at 1/2 CCLK. Memory transfers to external and link port buffers operate at the SOCCLK rate. SCLK also provides clock input for the external bus interface and defines the ac specification reference for the external bus signals. The external bus interface runs at the SCLK frequency. The maximum SCLK frequency is one quarter the internal processor clock (CCLK) frequency.

RESET AND BOOTING

The processor has three levels of reset:

• Power-up reset – after power-up of the system (SCLK, all static inputs, and strap pins are stable), the RST_IN must be asserted (low).

• Normal reset – for any chip reset following the power-up reset, the RST_IN

• Processor-core reset – when setting the SWRST bit in EMUCTL, the processor core is reset, but not the external port or I/O.

For normal operations, tie the RST_OUT POR_IN

pin.

After reset, the processor has four boot options for beginning operation:

•Boot from EPROM.

• Boot by an external master (host or another ADSP-TS203S processor).

•Boot by link port.

• No boot—start running from memory address selected with one of the IRQ3–0 Using the this option, the processor must start running from memory when one of the interrupts is asserted.

The processor core always exits from reset in the idle state and waits for an interrupt. Some of the interrupts in the interrupt vector table are initialized and enabled after reset.

pin must be asserted (low).

pin to the

interrupt signals. See Table 2.

Rev. D | Page 8 of 48 | May 2012

Figure 3. Clock Domains

FILTERING REFERENCE VOLTAGE AND CLOCKS

Figure 4 and Figure 5 show possible circuits for filtering V

and SCLK_V

. These circuits provide the reference voltages

REF

for the switching voltage reference and system clock reference.

Figure 4. V

Filtering Scheme

REF

CLOCK DRIVER

VOLTAGE OR

DD_IO

SCLK_V

REF

R2 C1 C2

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*IF CLOCK DRIVER VOLTAGE > V

DD_IO

Figure 5. SCLK_V

Filtering Scheme

REF

POWER DOMAINS

The ADSP-TS203S processor has separate power supply connections for internal logic (V buffer (V

), and internal DRAM (V

DD_IO

), analog circuits (V

DD_DRAM

DD_A

) power

), I/O

supply.

Note that the analog (V

) supply powers the clock generator

DD_A

PLLs. To produce a stable clock, systems must provide a clean power supply to power input V attention to bypassing the V

DD_A

. Designs must pay critical

DD_A

supply.

DEVELOPMENT TOOLS

The ADSP-TS203S processor is supported with a complete set of CROSSCORE including Analog Devices emulators and VisualDSP++ opment environment. The same emulator hardware that supports other TigerSHARC processors also fully emulates the ADSP-TS203S processor.

The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that includes DSP and mathematical functions. A key point for theses tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The processor has architectural features that improve the efficiency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the

software and hardware development tools,

devel-

ADSP-TS203S

program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action.

Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory, and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the TigerSHARC processor development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and generate outputs

• Maintain a one-to-one correspondence with the tool’s command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK.

VCSE is Analog Devices’ technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. It is also used for downloading components from the Web, dropping them into the application, and publish component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.

Rev. D | Page 9 of 48 | May 2012

ADSP-TS203S

Use the expert linker to visually manipulate the placement of code and data on the embedded system, view memory use in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with a drag of the mouse, and examine runtime stack and heap usage. The expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments.

Analog Devices emulators use the IEEE 1149.1 JTAG test access port of the ADSP-TS203S processor to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing.

In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the TigerSHARC processor family. Hardware tools include TigerSHARC processor PC plug-in cards. Third party software tools include DSP libraries, realtime operating systems, and block diagram design tools.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite® evaluation platforms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standalone unit, without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom-defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation.

processor must be halted to send data and commands, but once an operation has been completed by the emulator, the system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)— use the string “EE-68” in site search. This document is updated regularly to keep pace with improvements to emulator support.

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the

www.analog.com website.

The Circuits from the Lab provides:

• Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection guides and application information

• Reference designs applying best practice design techniques

site (www.analog.com/circuits)

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-TS203S processor’s architecture and functionality. For detailed information on the ADSP-TS203S processor’s core architecture and instruction set, see the ADSP-TS201 Tiger-

SHARC Processor Hardware Reference and the ADSP-TS201 TigerSHARC Processor Programming Reference. For detailed

information on the development tools for this processor, see the

VisualDSP++ User’s Guide for TigerSHARC Processors.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every developer needs to in order test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG processor. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The

Rev. D | Page 10 of 48 | May 2012

PIN FUNCTION DESCRIPTIONS

ADSP-TS203S

While most of the ADSP-TS203S processor’s input pins are normally synchronous—tied to a specific clock—a few are asynchronous. For these asynchronous signals, an on-chip synchronization circuit prevents metastability problems. Use the ac specification for asynchronous signals when the system design requires predictable, cycle-by-cycle behavior for these signals.

The output pins can be three-stated during normal operation. The processor three-states all output during reset, allowing these pins to get to their internal pull-up or pull-down state. Some pins have an internal pull-up or pull-down resistor (±30% tolerance) that maintains a known value during transitions between different drivers.

Table 3. Pin Definitions—Clocks and Reset

Signal Type Term Description

SCLKRAT2–0 I (pd) na Core Clock Ratio. The processor’s core clock (CCLK) rate = n × SCLK, where n is user-

programmable using the SCLKRATx pins to the values shown in Tabl e 4. These pins may change only during reset; connect these pins to V cations in Tab le 25 , Tab le 2 6, and Tab le 2 7 must be satisfied. The core clock rate (CCLK) is the instruction cycle rate.

SCLK I na System Clock Input. The processor’s system input clock for cluster bus. The core

clock rate is user-programmable using the SCLKRATx pins. For more information,

see Clock Domains on Page 8.

RST_IN

RST_OUT POR_IN I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

I/A na Reset. Sets the processor to a known state and causes program to be in idle state.

RST_IN must be asserted a specified time according to the type of reset operation. For details, see Reset and Booting on Page 8, Table 27 on Page 26, and Figure 12 on

Page 26.

O na Reset Output. Indicates that the processor reset is complete. Connect to POR_IN. I/A na Power-On Reset for internal DRAM. Connect to RST_OUT.

, nc = not connected; na = not applicable (always used); V

DD_IO

= connect directly to V

DD_IO

or VSS. All reset specifi-

DD_IO

; epu = external pull-up

; VSS = connect

DD_IO

Table 4. SCLK Ratio

SCLKRAT2–0 Ratio

000 (default) 4 001 5 010 6 011 7 100 8 101 10 110 12 111 Reserved

Rev. D | Page 11 of 48 | May 2012

ADSP-TS203S

Table 5. Pin Definitions—External Port Bus Controls

Signal Type Term Description

ADDR31–0 I/O/T

(pu_ad)

DATA31–0 I/O/T

(pu_ad)

I/O/T (pu_0)

WRL

I/O/T (pu_0)

ACK I/O/T/OD

(pu_od_0)

BMS O/T

(pu_0)

MS1–0

O/T (pu_0)

MSH

O/T (pu_0)

BRST

I/O/T (pu_0)

TM4 I/O/T epu Test Mode 4. Must be pulled up to V I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

This external pull-up may be omitted for the ID = 000 TigerSHARC processor.

, nc = not connected; na = not applicable (always used); V

DD_IO

nc Address Bus. The processor issues addresses for accessing memory and peripherals

on these pins. In a multiprocessor system, the bus master drives addresses for accessing internal memory or I/O processor registers of other ADSP-TS203S processors. The processor inputs addresses when a host or another processor accesses its internal memory or I/O processor registers.

nc External Data Bus. The processor drives and receives data and instructions on these

pins. Pull-up or pull-down resistors on unused DATA pins are unnecessary.

epu

Memory Read. RD is asserted whenever the processor reads from any slave in the system, excluding SDRAM. When the processor is a slave, RD

is an input and indicates read transactions that access its internal memory or universal registers. In a multiprocessor system, the bus master drives RD. RD changes concurrently with ADDR pins.

epu

Write Low. WRL is asserted when the ADSP-TS203S processor writes to the external bus (host, memory, or processor). An external master (host or processor) asserts WRL for writing to a processor’s internal memory. In a multiprocessor system, the bus master drives WRL is a slave, WRL

. WRL changes concurrently with ADDR pins. When the processor

is an input and indicates write transactions that access its internal

memory or universal registers.

epu

Acknowledge. External slave devices can deassert ACK to add wait states to external memory accesses. ACK is used by I/O devices, memory controllers, and other peripherals on the data phase. The processor can deassert ACK to add wait states to read and write accesses of its internal memory. The pull-up is 50  on low-to-high transactions and is 500  on all other transactions.

na Boot Memory S elect. BMS is the chip select for boot EPROM or flash memory. During

reset, the processor uses BMS as a strap pin (EBOOT) for EPROM boot mode. In a multiprocessor system, the processor bus master drives BMS

. For details, see Reset

and Booting on Page 8 and the EBOOT signal description in Table 16 on Page 18.

nc Memory Select. MS0 or MS1 is asserted whenever the processor accesses memory

banks 0 or 1, respectively. MS1–0 are decoded memory address pins that change concurrently with ADDR pins. When ADDR31:27 = 0b00110, MS0

is asserted. When ADDR31:27 = 0b00111, MS1 is asserted. In multiprocessor systems, the master processor drives MS1–0.

nc Memory Select Host. MSH is asserted whenever the processor accesses the host

address space (ADDR31 = 0b1). MSH

is a decoded memory address pin that changes concurrently with ADDR pins. In a multiprocessor system, the bus master processor drives MSH.

epu

Burst. The current bus master (processor or host) asserts this pin to indicate that it is reading or writing data associated with consecutive addresses. A slave device can ignore addresses after the first one and increment an internal address counter after each transfer. For host-to-processor burst accesses, the processor increments the address automatically while BRST

is asserted.

with a 5 k resistor.

DD_IO

= connect directly to V

DD_IO

; epu = external pull-up

; VSS = connect

DD_IO

Rev. D | Page 12 of 48 | May 2012

Table 6. Pin Definitions—External Port Arbitration

ADSP-TS203S

Signal Type Term Description

BR7–0

I/O V

DD_IO

Multiprocessing Bus Request Pins. Used by the processors in a multiprocessor system to arbitrate for bus mastership. Each processor drives its own BRx line (corresponding to the value of its ID2–0 inputs) and monitors all others. In systems with fewer than eight processors, set the unused BRx

pins high (V

DD_IO

ID2–0 I (pd) na Multiprocessor ID. Indicates the processor’s ID, from which the processor deter-

mines its order in a multiprocessor system. These pins also indicate to the processor which bus request (BR0 001 = BR1

, 010 = BR2, 011 = BR3, 100 = BR4, 101 = BR5, 110 = BR6, or 111 = BR7.

–BR7) to assert when requesting the bus: 000 = BR0,

ID2–0 must have a constant value during system operation and can change during reset only.

O na Bus Master. The current bus master processor asserts BM. For debugging only. At

reset this is a strap pin. For more information, see Table 16 on Page 18.

BOFF

I epu Back Off. A deadlock situation can occur when the host and a processor try to read

from each other’s bus at the same time. When deadlock occurs, the host can assert

to force the processor to relinquish the bus before completing its outstanding

BOFF transaction.

BUSLOCK

HBR

O/T (pu_0)

na Bus Lock Indication. Provides an indication that the current bus master has locked

the bus. At reset, this is a strap pin. For more information, see Table 16 on Page 18.

I epu Host Bus Request. A host must assert HBR to request control of the processor’s

external bus. When HBR

is asserted in a multiprocessing system, the bus master

relinquishes the bus and asserts HBG once the outstanding transaction is finished.

HBG

I/O/T (pu_0)

epu

Host Bus Grant. Acknowledges HBR and indicates that the host can take control of the external bus. When relinquishing the bus, the master processor three-states the ADDR31–0, DATA31–0, MSH

, MSSD3–0, MS1–0, RD, WRL, BMS, BRST, IORD, IOWR, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM, and TM4 pins, and the processor puts the SDRAM in self-refresh mode. The processor asserts HBG until the host deasserts

. In multiprocessor systems, the current bus master processor drives HBG, and

HBR all slave processors monitor it.

CPA

I/O/OD (pu_od_0)

epu

Core Priority Access. Asserted while the processor’s core accesses external memory. This pin enables a slave processor to interrupt a master processor’s background DMA transfers and gain control of the external bus for core-initiated transactions.

is an open-drain output, connected to all DSPs in the system. If not required in

CPA the system, leave CPA unconnected (external pull-ups will be required for processor ID = 1 through ID = 7).

DPA

I/O/OD (pu_od_0)

epu

DMA Priority Access. Asserted while a high priority processor DMA channel accesses external memory. This pin enables a high priority DMA channel on a slave processor to interrupt transfers of a normal priority DMA channel on a master processor and gain control of the external bus for DMA-initiated transactions. DPA

is an open-drain output, connected to all DSPs in the system. If not required in the system, leave DPA unconnected (external pull-ups will be required for processor ID = 1 through ID = 7).

I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down 5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0; pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up 5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to VSS; epu = external pull-up approximately 5 k to V directly to V

The BRx pin matching the ID2–0 input selection for the processor should be left nc if unused. For example, the processor with ID = 000 has BR0 = nc and BR7–1 = V

This external pull-up resistor may be omitted for the ID = 000 TigerSHARC processor.

, nc = not connected; na = not applicable (always used); V

DD_IO

= connect directly to V

DD_IO

; VSS = connect

DD_IO

Rev. D | Page 13 of 48 | May 2012

ADSP-TS203S

Table 7. Pin Definitions—External Port DMA/Flyby

Signal Type Term Description

DMAR3–0

IOWR O/T

IORD

IOEN

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

I/A epu DMA Request Pins. Enable external I/O devices to request DMA services from the

processor. In response to DMARx, the processor performs DMA transfers according to the DMA channel’s initialization. The processor ignores DMA requests from uninitialized channels.

nc I/O Write. When a processor DMA channel initiates a flyby mode read transaction,

(pu_0)

the processor asserts the IOWR signal during the data cycles. This assertion makes the I/O device sample the data instead of the TigerSHARC.

O/T (pu_0)

nc I/O Read. When a processor DMA channel initiates a flyby mode write transaction,

the processor asserts the IORD

signal during the data cycle. This assertion with the

IOEN makes the I/O device drive the data instead of the TigerSHARC.

O/T (pu_0)

nc I/O Device Output Enable. Enables the output buffers of an external I/O device for

fly-by transactions between the device and external memory. Active on flyby transactions.

; epu = external pull-up

, nc = not connected; na = not applicable (always used); V

DD_IO

= connect directly to V

DD_IO

; VSS = connect

DD_IO

Table 8. Pin Definitions—External Port SDRAM Controller

Signal Type Term Description

MSSD3–0

I/O/T (pu_0)

nc Memor y Select SDRAM. MSSD0, MSSD1, MSSD2, or MSSD3 is asserted whenever the

processor accesses SDRAM memory space. MSSD3–0

are decoded memory address pins that are asserted whenever the processor issues an SDRAM command cycle (access to ADDR31:30 = 0b01—except reserved spaces shown in Figure 2 on

RAS

I/O/T (pu_0)

Page 6). In a multiprocessor system, the master processor drives MSSD3–0

nc Row Address Select. When sampled low, RAS indicates that a row address is valid in

a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation to execute according to SDRAM specification.

CAS

I/O/T (pu_0)

nc Column Address Select. When sampled low, CAS indicates that a column address is

valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation to execute according to the SDRAM specification.

LDQM O/T

(pu_0)

nc Low Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ

buffers. LDQM is valid on SDRAM transactions when CAS

is asserted, and inactive

on read transactions.

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

, nc = not connected; na = not applicable (always used); V

DD_IO

= connect directly to V

DD_IO

; epu = external pull-up

; VSS = connect

DD_IO

Rev. D | Page 14 of 48 | May 2012

ADSP-TS203S

Table 8. Pin Definitions—External Port SDRAM Controller (Continued)

Signal Type Term Description

SDA10 O/T

(pu_0)

SDCKE I/O/T

(pu_m/ pd_m)

SDWE I/O/T

(pu_0)

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

, nc = not connected; na = not applicable (always used); V

DD_IO

nc SDRAM Address Bit 10. Separate A10 signals enable SDRAM refresh operation while

the processor executes non-SDRAM transactions.

nc SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend

modes. A slave processor in a multiprocessor system does not have the pull-up or pull-down. A master processor (or ID = 0 in a single processor system) has a pull-up before granting the bus to the host, except when the SDRAM is put in self refresh mode. In self refresh mode, the master has a pull-down before granting the bus to the host.

nc SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an

SDRAM write access. When sampled high while CAS is active, SDWE indicates an SDRAM read access. In other SDRAM accesses, SDWE defines the type of operation to execute according to SDRAM specification.

; epu = external pull-up

= connect directly to V

DD_IO

; VSS = connect

DD_IO

Table 9. Pin Definitions—JTAG Port

Signal Type Term Description

EMU

O/OD nc

Emulation. Connected to the processor’s JTAG emulator target board connector

only. TCK I epd or epu1Test Clock (JTAG). Provides an asynchronous clock for JTAG scan. TDI I

Test Data Input (JTAG). A serial data input of the scan path.

(pu_ad)

Test Data Output (JTAG). A serial data output of the scan path.

Test Mode Select (JTAG). Used to control the test state machine.

TDO O/T nc

TMS I

(pu_ad)

TRST

I/A (pu_ad)

na Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed

low after power-up for proper device operation. For more information, see Reset

and Booting on Page 8.

on Page 21.

Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V approximately 5 k to V directly to V

See the reference on Page 10 to the JTAG emulation technical reference EE-68.

, nc = not connected; na = not applicable (always used); V

DD_IO

= connect directly to V

DD_IO

; epu = external pull-up

; VSS = connect

DD_IO

Rev. D | Page 15 of 48 | May 2012

+ 33 hidden pages

ANALOG DEVICES ADSP-TS203S Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

KEY FEATURES

KEY BENEFITS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

DUAL COMPUTE BLOCKS

DATA ALIGNMENT BUFFER (DAB)

DUAL INTEGER ALU (IALU)

PROGRAM SEQUENCER

Interrupt Controller

Flexible Instruction Set

MEMORY

EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE)

Host Interface

Multiprocessor Interface

SDRAM Controller

EPROM Interface

DMA CONTROLLER

LINK PORTS (LVDS)

TIMER AND GENERAL-PURPOSE I/O

CLOCK DOMAINS

RESET AND BOOTING

FILTERING REFERENCE VOLTAGE AND CLOCKS

POWER DOMAINS

DEVELOPMENT TOOLS

Evaluation Kit

RELATED SIGNAL CHAINS

ADDITIONAL INFORMATION

Designing an Emulator-Compatible DSP Board (Target)

PIN FUNCTION DESCRIPTIONS