ANALOG DEVICES ADSP-TS201 Service Manual

ADSP-TS201 TigerSHARC® Processor

Hardware Reference

Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Revision 1.1, December 2004

Part Number

82-000815-01

a

Copyright Information

© 2004 Analog Devices, Inc., ALL RIGHTS RESERVED. This
document may not be reproduced in any form without prior, express
written consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by
implication or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, EZ-ICE, SHARC, TigerSHARC, the
TigerSHARC logo, and VisualDSP++, and are registered trademarks of
Analog Devices, Inc.

Static Superscalar is a trademark of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of
their respective owners.

CONTENTS

CONTENTS

PREFACE

Purpose of This Manual ................................................................. xxi

Intended Audience ......................................................................... xxi

Manual Contents .......................................................................... xxii

What’s New in This Manual ......................................................... xxiv

Technical or Customer Support ..................................................... xxv

Supported Processors .................................................................... xxvi

Product Information ................................................................... xxvii

MyAnalog.com ...................................................................... xxvii

Processor Product Information ............................................... xxvii

Related Documents .............................................................. xxviii

Online Technical Documentation ........................................... xxix

Accessing Documentation From VisualDSP++ ..................... xxx

Accessing Documentation From Windows ........................... xxx

Accessing Documentation From the Web ............................ xxxi

Printed Manuals ..................................................................... xxxi

ADSP-TS201 TigerSHARC Processor Hardware Reference iii

CONTENTS

VisualDSP++ Documentation Set ...................................... xxxi

Hardware Tools Manuals .................................................. xxxii

Processor Manuals ............................................................ xxxii

Data Sheets ...................................................................... xxxii

Conventions .............................................................................. xxxiii

PROCESSOR ARCHITECTURE

Processor Core .............................................................................. 1-8

Compute Blocks ................................................................... 1-10

Arithmetic Logic Unit (ALU) ............................................ 1-12

Communications Logic Unit (CLU) .................................. 1-12

Multiply Accumulator (Multiplier) .................................... 1-12

Bit Wise Barrel Shifter (Shifter) ........................................ 1-13

Integer Arithmetic Logic Unit (IALU) ................................... 1-13

Program Sequencer ............................................................... 1-15

Processor Core Controls ........................................................ 1-17

Clock Domains ................................................................ 1-17

Operation Modes ............................................................. 1-18

User Mode ................................................................... 1-19

Supervisor Mode ........................................................... 1-20

Emulator Mode ............................................................ 1-20

Boot Modes ...................................................................... 1-22

Memory, Registers, and Buses ..................................................... 1-22

Internal Buses ....................................................................... 1-23

Internal Registers .................................................................. 1-23

iv ADSP-TS201 TigerSHARC Processor Hardware Reference

CONTENTS

SOC Interface ............................................................................. 1-24

Timers ........................................................................................ 1-24

Flags ........................................................................................... 1-25

Interrupts ................................................................................... 1-26

Direct Memory Access ................................................................. 1-26

External (Address and Data) Port ................................................. 1-28

External Bus and Host Interface ............................................. 1-28

External Memory .............................................................. 1-29

Multiprocessing ................................................................ 1-30

Host Interface ................................................................... 1-31

Link Ports ................................................................................... 1-32

JTAG Port and Debug Interface .................................................. 1-32

Programming Information ........................................................... 1-33

MEMORY AND REGISTERS

Host Address Space ....................................................................... 2-4

External Memory Bank Space ........................................................ 2-4

Multiprocessor Space ..................................................................... 2-6

Internal Address Space .................................................................. 2-7

Universal (Ureg) Register Space ..................................................... 2-8

Compute Block Register Groups ............................................ 2-14

Unmapped Compute Block Registers ................................. 2-19

IALU Register Groups ........................................................... 2-22

IALU Status (J31/JSTAT and K31/KSTAT) Registers ......... 2-26

Sequencer Register Groups .................................................... 2-27

ADSP-TS201 TigerSHARC Processor Hardware Reference v

CONTENTS

Flag Control (FLAGREG) Register ................................... 2-28

Sequencer Control (SQCTL) Register ............................... 2-29

Static Flags (SFREG) Register ........................................... 2-30

Sequencer Control Set Bits (SQCTLST) Register .............. 2-31

Sequencer Control Clear Bits (SQCTLCL) Register ........... 2-31

Sequencer Status (SQSTAT) Register ................................ 2-31

Cache Register Groups .......................................................... 2-34

Cache/Memory System Command/Status

(CACMDx, CCAIRx, and CASTATx) Registers ............. 2-36

Interrupt Register Groups ..................................................... 2-41

Interrupt Vector Table Register Groups ............................. 2-41

Interrupt Control (INTCTL) Register ............................... 2-45

Interrupt Latch (ILATL/ILATH) Registers ........................ 2-46

Interrupt Pointer Mask (PMASKL/PMASKH) Registers .... 2-47

Interrupt Mask (IMASKL/IMASKH) Registers .................. 2-47

Timer Interrupt (TIMERxH/L) Registers .......................... 2-50

Timer Initial Value (TMRINxH/L) Registers ..................... 2-50

DMA Control and Status Register Group .............................. 2-51

DMA Control (DCNT) Register ....................................... 2-51

DMA Status (DSTAT) Register ......................................... 2-53

External Port DMA TCB Register Group ............................... 2-56

Link Port Transmit DMA TCB Register Group ...................... 2-57

Link Port Receive DMA TCB Register Group ........................ 2-58

AutoDMA Register Group .................................................... 2-60

vi ADSP-TS201 TigerSHARC Processor Hardware Reference

CONTENTS

DMA Index (DI), X-Dimension (DX),

Y-Dimension (DY), and Pointer (DP) TCB Registers ........... 2-61

Link Port Register Groups ..................................................... 2-65

Link Receive Control (LRCTLx) Registers ......................... 2-68

Link Transmit Control (LTCTLx) Registers ....................... 2-69

Link Receive Status (LRSTATx) Registers .......................... 2-70

Link Transmit Status (LTSTATx) Registers ........................ 2-71

External Bus Interface Register Groups .................................. 2-72

System Configuration (SYSCON) Register ........................ 2-73

Bus Lock (BUSLOCK) System Control Register ................ 2-76

SDRAM Configuration (SDRCON) Register .................... 2-76

System Status (SYSTAT) Register ...................................... 2-77

Bus Master Maximum (BMAX) Register ............................ 2-80

Bus Master Maximum Current Count (BMAXC) Register .. 2-80

JTAG Test and Emulation Register Groups ............................ 2-81

Emulation Control (EMUCTL) Register ........................... 2-82

Emulation Status (EMUSTAT) Register ............................. 2-83

Silicon Version and ID Code (IDCODE) Register ............. 2-83

Debug Register Groups .......................................................... 2-84

Watchpoint Control (WPxCTL) Registers ......................... 2-86

Watchpoint Status (WPxSTAT) Registers ........................... 2-89

Watchpoint Address Pointer (WPxL/WPxH) Registers ....... 2-89

Performance Monitor Mask (PRFM) Register .................... 2-89

Performance Monitor Counter (PRFCNT) Register ........... 2-92

Cycle Counter (CCNTx) Registers .................................... 2-92

ADSP-TS201 TigerSHARC Processor Hardware Reference vii

CONTENTS

Trace Buffers and Pointer (TRCBx/TRCBPTR) Registers .. 2-93

SOC INTERFACE

SOC Interface Operations ............................................................ 3-5

SOC OFIFO Transactions ....................................................... 3-5

SOC IFIFO/OBUF Transactions ............................................. 3-7

SOC Interface Programming ......................................................... 3-8

TIMERS

Timer Operations ......................................................................... 4-2

Timer Programming ..................................................................... 4-4

Timer Expired (TMR0E) Pin and Signal Timing ........................... 4-8

FLAGS

Flag Operations ............................................................................ 5-1

Flag Programming ........................................................................ 5-3

Flag (FLAG3-0) Pin and Signal Timing ....................................... 5-10

INTERRUPTS

Interrupt Operations .................................................................... 6-5

Interrupt Service Routines ....................................................... 6-8

Handling Interrupts .......................................................... 6-13

Returning From an Interrupt ............................................ 6-14

Handling Exceptions ........................................................ 6-15

Interrupt Vector Table ........................................................... 6-17

Timer Expired Interrupts .................................................. 6-19

viii ADSP-TS201 TigerSHARC Processor Hardware Reference

CONTENTS

Link Port Service Request Interrupts .................................. 6-20

DMA Complete Interrupts ................................................ 6-20

External (IRQ3–0) Input Interrupts .................................. 6-20

Vector Interrupt ................................................................ 6-21

Bus Lock Interrupt Register ............................................... 6-21

Hardware Error Interrupt .................................................. 6-22

Software Exception Interrupts ........................................... 6-23

Emulation Exception Interrupt .......................................... 6-24

Interrupt Programming ............................................................... 6-25

Interrupt (IRQ3-0) Pin and Signal Timing .................................. 6-32

DIRECT MEMORY ACCESS

DMA Controller Features .............................................................. 7-8

Cluster Bus Transfers ............................................................... 7-8

AutoDMA Transfers .............................................................. 7-10

Link Port Transfers ................................................................ 7-10

Two-Dimensional DMA ........................................................ 7-11

Chained DMA ...................................................................... 7-11

DMA Architecture ...................................................................... 7-12

DMA Request (DMAR3-0) Pins ............................................ 7-13

Terminology .......................................................................... 7-14

Setting Up DMA Transfers .......................................................... 7-15

DMA Transfer Control Block Registers ........................................ 7-15

DMA Channel Control ......................................................... 7-16

Transfer Control Block (TCB) Registers ............................ 7-16

ADSP-TS201 TigerSHARC Processor Hardware Reference ix

CONTENTS

DIx Register ................................................................. 7-18

DXx Register ................................................................ 7-18

DYx Register ................................................................ 7-19

DPx Register ................................................................ 7-19

DMA Control and Status Registers ............................................. 7-23

DMA Status Register (DSTAT/DSTATC) .............................. 7-23

DMA Control Registers ........................................................ 7-26

DCNT Register ................................................................ 7-26

DCNTST Register ........................................................... 7-27

DCNTCL Register ........................................................... 7-27

DMA Control Register Restrictions ................................... 7-27

DMA Controller Operations ....................................................... 7-31

Link Port DMA Control ....................................................... 7-31

External Port DMA Control .................................................. 7-32

AutoDMA Register Control .................................................. 7-32

DMA Transfers ..................................................................... 7-33

Internal Memory Buses ..................................................... 7-33

DMA Channels ................................................................ 7-34

DMA Memory Addressing .................................................... 7-34

DMA Channel Prioritization ................................................. 7-36

Internal Memory Bus Priority ........................................... 7-36

DMA Channel Priority ..................................................... 7-36

Rotating Priority .............................................................. 7-38

DMA Chaining ..................................................................... 7-40

x ADSP-TS201 TigerSHARC Processor Hardware Reference

CONTENTS

Enabling and Disabling Chaining ...................................... 7-42

Generating a DMA Complete Interrupt While Chaining .... 7-42

Transfer Control Blocks and Chain Loading ...................... 7-42

Setting Up and Starting the Chain ..................................... 7-43

Chain Insertion ................................................................. 7-43

Two-Dimensional DMA ........................................................ 7-44

Two-Dimensional DMA Channel Organization ................. 7-45

Two-Dimensional DMA Operation ................................... 7-46

Examples of Two Dimensional DMA Transfers .................. 7-48

DMA Interrupts .................................................................... 7-49

Starting and Stopping DMA Sequences .................................. 7-51

Starting a DMA Sequence ................................................. 7-51

Ending a DMA Sequence .................................................. 7-52

Suspending a DMA Sequence ............................................ 7-52

Resuming a DMA Sequence .............................................. 7-52

External Port DMA ..................................................................... 7-52

Internal and External Address Generation .............................. 7-53

External Port DMA Transfer Types ........................................ 7-54

External to Internal Memory ............................................. 7-54

Internal to External Memory ............................................. 7-57

External I/O Device to External Memory (Flyby) ............... 7-60

External Memory to External I/O Device (Flyby) ............... 7-62

DMA Semaphores ............................................................. 7-63

Handshake Mode .............................................................. 7-64

ADSP-TS201 TigerSHARC Processor Hardware Reference xi

CONTENTS

Flyby Mode ...................................................................... 7-65

Link Port DMA .......................................................................... 7-66

Link Ports DMA Transfer Types ............................................ 7-66

Link Port to Internal/External Memory ............................. 7-66

Internal/External Memory to Link .................................... 7-68

Receiving Link Port to Link Port ....................................... 7-69

DMA Throughput ...................................................................... 7-71

Internal Memory DMA ......................................................... 7-71

External Memory DMA ........................................................ 7-71

DMA Operation on Boot ............................................................ 7-72

DMA Examples .......................................................................... 7-73

EXTERNAL PORT AND SDRAM INTERFACE

External Bus Features .................................................................... 8-2

Bus Interface I/O Pins .................................................................. 8-3

Processor Microarchitecture .......................................................... 8-5

SYSCON Register Programming ................................................. 8-13

Bus Width ............................................................................ 8-13

Slow Device Protocol for Bus ................................................ 8-14

Pipelined Protocol for Bus ..................................................... 8-14

Initial Value for Bus Operation .............................................. 8-15

Pipelined Protocol Interface ........................................................ 8-15

Control Signals for Pipelined Transactions ............................. 8-16

Using Basic Pipelined Transactions ........................................ 8-16

Using Burst Pipelined Transactions ........................................ 8-18

xii ADSP-TS201 TigerSHARC Processor Hardware Reference

CONTENTS

Wait Cycles ........................................................................... 8-23

Slow Device Protocol Interface .................................................... 8-26

EPROM Interface ....................................................................... 8-32

Multiprocessing Interface ............................................................ 8-34

Bus Arbitration Protocol ........................................................ 8-38

Core Priority Access (CPA) Pin ......................................... 8-40

DMA Priority Access (DPA) Pin ........................................ 8-42

Bus Fairness (BMAX) Register ........................................... 8-44

Bus Lock (BUSLOCK) Register ......................................... 8-44

Software (Processor Core) Reset Operation ........................ 8-45

Host Processor Interface .............................................................. 8-46

Back Off (BOFF) Pin ............................................................ 8-48

SDRAM Interface ....................................................................... 8-50

SDRAM Interface I/O Pins .................................................... 8-55

SDRAM Physical Connection ................................................ 8-56

Bank Select Pins ................................................................ 8-59

Internal Address and SDRAM Physical Connection ........... 8-60

SDRAM Programming .......................................................... 8-67

Enabling SDRAM ............................................................. 8-68

Selecting the CAS Latency Value – CAS ............................ 8-69

Setting the SDRAM Buffering Option – Pipeline Depth .... 8-69

Selecting the SDRAM Page Size – Page Boundary .............. 8-70

Setting the Refresh Counter Value – Refresh Rate .............. 8-70

Selecting the Precharge to RAS Delay ................................ 8-72

ADSP-TS201 TigerSHARC Processor Hardware Reference xiii

CONTENTS

Selecting the RAS to Precharge Delay ................................ 8-72

Setting the SDRAM Power-Up Mode

– Initialization Sequence ................................................ 8-73

Enabling the Extended Mode (EMR) Register ................... 8-73

Flyby Transactions ................................................................ 8-74

SDRAM Interface Throughput .............................................. 8-77

Multiprocessing Operation .................................................... 8-78

Understanding DQM Operation ........................................... 8-79

Powering Up After Reset ....................................................... 8-79

SDRAM Controller Commands ............................................ 8-80

Mode Register Set (MRS) Command ................................ 8-81

Precharge (PRE) Command .............................................. 8-83

Terminating Read/Write Cycles ..................................... 8-83

Precharging .................................................................. 8-83

Bank Active (ACT) Command .......................................... 8-84

Read Command ............................................................... 8-85

Bus Width = 64 ............................................................ 8-87

Bus Width = 32 ............................................................ 8-88

Write Command ............................................................... 8-89

Bus Width = 64 ............................................................ 8-91

Bus Width = 32 ............................................................ 8-92

Refresh (REF) Command ................................................. 8-93

Self-Refresh (SREF) Command ......................................... 8-93

Programming Example .......................................................... 8-94

xiv ADSP-TS201 TigerSHARC Processor Hardware Reference

CONTENTS

LINK PORTS

Link Architecture .......................................................................... 9-2

Link I/O Pins .......................................................................... 9-4

Link Transmit and Receive Data .............................................. 9-7

Link DMA .............................................................................. 9-9

Link Block Completion ........................................................... 9-9

Link Interrupts ...................................................................... 9-10

Link Reset Initialization and Boot .......................................... 9-10

Link Alternate (Software) Initialization .................................. 9-11

Link Port Communication Protocol ............................................. 9-12

Link Port Transmission Delays .................................................... 9-17

Link Port Error Detection Mechanisms ........................................ 9-19

Link Transmitter Timeout ..................................................... 9-20

Link Receiver Timeout .......................................................... 9-20

Link Verification Error .......................................................... 9-20

Link Transmit/Receive Write Error ........................................ 9-21

Link Port Control Registers ......................................................... 9-21

Link Port Status Registers ............................................................ 9-26

JTAG PORT AND

TEST/DEBUG INTERFACE

Operating Modes ........................................................................ 10-4

Debug Resources ......................................................................... 10-5

Special Instructions ............................................................... 10-5

Watchpoints .......................................................................... 10-5

ADSP-TS201 TigerSHARC Processor Hardware Reference xv

CONTENTS

Programming – Control and Address Pointer Registers ...... 10-5

Watchpoint Operation ...................................................... 10-6

Watchpoint Status (WPiSTAT) ......................................... 10-7

Instruction Address Trace Buffer (TBUF) .............................. 10-8

Performance Monitors ................................................................ 10-8

Cycle Counter (CCNT1–0) .................................................. 10-9

Performance Monitor Mask – PRFM ..................................... 10-9

Performance Monitor Counter ............................................ 10-10

JTAG Functionality .................................................................. 10-11

JTAG Port I/O Pins ............................................................ 10-11

JTAG Instruction Register ................................................... 10-13

Data Registers ..................................................................... 10-13

SYSTEM DESIGN

Processor Booting Methods ......................................................... 11-2

Using Boot Modes and Boot Loader Kernels .......................... 11-3

Executing a Processor Boot Operation ................................... 11-3

EPROM Boot ................................................................... 11-4

Host Boot ........................................................................ 11-5

Link Port Boot ................................................................. 11-6

No Boot ........................................................................... 11-6

Booting References ................................................................ 11-8

Hardware System Design Guidelines ........................................... 11-8

Power Supplies ...................................................................... 11-9

System Clock (SCLK) Pin ................................................... 11-10

xvi ADSP-TS201 TigerSHARC Processor Hardware Reference

CONTENTS

Considerations for SCLK Design ..................................... 11-10

Considerations for SCLK Distribution ............................ 11-11

Boundary Scan and Emulator Pins ....................................... 11-15

External Ports Pins .............................................................. 11-15

Link Ports Pins .................................................................... 11-17

Hardware Design References ................................................ 11-17

Processor Thermal Relief Methods ............................................. 11-18

Thermal Overview ............................................................... 11-19

Thermal Calculations .......................................................... 11-21

Heat Sink Basics .................................................................. 11-23

Pin Fins versus Rectangular Fins .......................................... 11-23

PCB Design for Thermal Dissipation ................................... 11-24

Thermal Simulations ........................................................... 11-25

Thermal Design Terminology .............................................. 11-26

Thermal Design References .................................................. 11-27

Other Design and Test References ............................................. 11-28

ADSP-TS201 Processor EZ-KIT Lite ................................... 11-28

ADSP-TS201S MP System Simulation and Analysis

Cluster Bus Topology – Signal Integrity and PCB Design

Considerations ................................................................. 11-29

IBIS Models ........................................................................ 11-29

FPGA Link Port Support ..................................................... 11-30

Recommended Reading References ............................................ 11-31

INDEX

ADSP-TS201 TigerSHARC Processor Hardware Reference xvii

CONTENTS

xviii ADSP-TS201 TigerSHARC Processor Hardware Reference

ADSP-TS201 TigerSHARC Processor Hardware Reference xix

xx ADSP-TS201 TigerSHARC Processor Hardware Reference

PREFACE

Thank you for purchasing and developing systems using TigerSHARC®
processors from Analog Devices.

Purpose of This Manual

The ADSP-TS201 TigerSHARC Processor Hardware Reference contains
information about the DSP architecture and DSP system design for
TigerSHARC processors. These are 32-bit, fixed- and floating-point digi­tal signal processors from Analog Devices for use in computing,
communications, and consumer applications.

The manual provides information on how the processor core and I/O
peripherals operate in the TigerSHARC processor’s architecture along
with reference information about I/O peripheral features.

Intended Audience

The primary audience for this manual is a system developer who is famil­iar with Analog Devices processors. This manual assumes that the
audience has a working knowledge of the appropriate processor architec­ture and microprocessor system design. Programmers who are unfamiliar
with Analog Devices processors can use this manual, but should supple­ment it with other texts (such as the appropriate programming reference
manuals and data sheets) that describe your target architecture.

ADSP-TS201 TigerSHARC Processor Hardware Reference xxi

Manual Contents

Manual Contents

The manual consists of:

• Chapter 1, Processor Architecture
This chapter provides an architectural overview of the
TigerSHARC processor.

• Chapter 2, Memory and Registers
This chapter defines the memory map of the ADSP-TS201
TigerSHARC processor. The memory space defines the location of
each element on the TigerSHARC processor.

• Chapter 3, SOC Interface
This chapter discusses clocking inputs, including the three differ­ent types of operating modes in which the ADSP-TS201
TigerSHARC processor can operate and the boot modes from
which the TigerSHARC processor initiates.

• Chapter 4, Timers
This chapter discusses clocking inputs, including the three differ­ent types of operating modes in which the ADSP-TS201
TigerSHARC processor can operate and the boot modes from
which the TigerSHARC processor initiates.

• Chapter 5, Flags
This chapter discusses clocking inputs, including the three differ­ent types of operating modes in which the ADSP-TS201
TigerSHARC processor can operate and the boot modes from
which the TigerSHARC processor initiates.

• Chapter 6, Interrupts
This chapter discusses the various types of interrupts supported by
the ADSP-TS201 TigerSHARC processor. Some of the interrupts
are generated internally or externally.

xxii ADSP-TS201 TigerSHARC Processor Hardware Reference

Preface

• Chapter 7, Direct Memory Access
This chapter describes how the ADSP-TS201 TigerSHARC pro­cessor’s on-chip DMA controller acts as a machine for transferring
data without core interruption.

• Chapter 8, External Port and SDRAM Interface
This chapter focuses on the external bus interface of the
ADSP-TS201 TigerSHARC processor, which includes the bus
arbitration logic and the external address, data and control buses,
and interface to SDRAM devices.

• Chapter 9, Link Ports
This chapter describes how link ports provide point-to-point com­munications between ADSP-TS201 TigerSHARC processors in a
system. The Link ports can also be used to interface with any other
device that is designed to work in the same protocol.

• Chapter 10, JTAG Port and Test/Debug Interface
This chapter describes features of the ADSP-TS201 TigerSHARC
processor that are useful for performing software debugging and
services usually found in Operating System (OS) kernels.

• Chapter 11, System Design
This chapter describes system features of the ADSP-TS201
TigerSHARC processor. These include Power, Reset, Clock,
JTAG, and Booting, as well as pin descriptions and other system
level information.

L

ADSP-TS201 TigerSHARC Processor Hardware Reference xxiii

This hardware reference is a companion document to the
ADSP-TS201 TigerSHARC Processor Programming Reference.

What’s New in This Manual

What’s New in This Manual

Revision 1.0 of the ADSP-TS201 TigerSHARC Processor Hardware
Reference differs in a number of ways from the revision 0.2 book. In

revision 1.0, the following additions and corrections have been made:

• The Processor Architecture chapter has replaced the previous Intro­duction chapter. This new chapter provides a more detailed road
map to the processor architecture and processor core mode
controls.

• The SOC Interface, Timers, and Flags chapters have been added. A
description of the operation of all I/O peripherals as bus masters or
slaves on the SOC bus has been added in all chapters.

• The Interrupts chapter has been re-ordered to provide more guid­ance on using interrupts, and a consolidated interrupt vector table
has been added.

• The System Design chapter has been expanded. Many of the
Engineer-to-Engineer (EE) Notes to which the revision 0.2 book
referred have been added to the revision 1.0 book. The topics
added include booting, system design guidelines, and thermal
design guidelines.

• The index has been enhanced.

• Errata reports against the revision 0.2 book have been corrected.

xxiv ADSP-TS201 TigerSHARC Processor Hardware Reference

Technical or Customer Support

You can reach Analog Devices, Inc. Customer Support in the following
ways:

• Visit the Embedded Processing and DSP products Web site at

http://www.analog.com/processors/technicalSupport

• E-mail tools questions to

[e-mail]

• E-mail processor questions to

[e-mail]

• Phone questions to 1-800-ANALOGD

• Contact your Analog Devices, Inc. local sales office or authorized
distributor

Preface

• Send questions by mail to:

Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA

ADSP-TS201 TigerSHARC Processor Hardware Reference xxv

Supported Processors

Supported Processors

The following is the list of Analog Devices, Inc. processors supported in
VisualDSP++®.

TigerSHARC (ADSP-TSxxx) Processors

The name “TigerSHARC” refers to a family of floating-point and
fixed-point [8-bit, 16-bit, and 32-bit] processors. VisualDSP++ currently
supports the following TigerSHARC processors:

ADSP-TS101, ADSP-TS201, ADSP-TS202, and ADSP-TS203

SHARC® (ADSP-21xxx) Processors

The name “SHARC” refers to a family of high-performance, 32-bit,
floating-point processors that can be used in speech, sound, graphics, and
imaging applications. VisualDSP++ currently supports the following
SHARC processors:

ADSP-21020, ADSP-21060, ADSP-21061, ADSP-21062,
ADSP-21065L, ADSP-21160, ADSP-21161, ADSP-21261,
ADSP-21262, ADSP-21266, ADSP-21267, ADSP-21363, ADSP-21364,
and ADSP-21365

Blackfin® (ADSP-BFxxx) Processors

The name “Blackfin” refers to a family of 16-bit, embedded processors.
VisualDSP++ currently supports the following Blackfin processors:

ADSP-BF531, ADSP-BF532 (formerly ADSP-21532), ADSP-BF533,
ADSP-BF535 (formerly ADSP-21535), ADSP-BF561, AD6532, and
AD90747

xxvi ADSP-TS201 TigerSHARC Processor Hardware Reference

Preface

Product Information

You can obtain product information from the Analog Devices Web site,
from the product CD-ROM, or from the printed publications (manuals).

Analog Devices is online at www.analog.com. Our Web site provides infor­mation about a broad range of products—analog integrated circuits,
amplifiers, converters, and digital signal processors.

MyAnalog.com

MyAnalog.com is a free feature of the Analog Devices Web site that allows

customization of a Web page to display only the latest information on
products you are interested in. You can also choose to receive weekly
e-mail notifications containing updates to the Web pages that meet your
interests. MyAnalog.com provides access to books, application notes, data
sheets, code examples, and more.

Registration

Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com.
Registration takes about five minutes and serves as a means to select the
information you want to receive.

If you are already a registered user, just log on. Your user name is your
e-mail address.

Processor Product Information

For information on embedded processors and DSPs, visit our Web site at

www.analog.com/processors, which provides access to technical publica-

tions, data sheets, application notes, product overviews, and product
announcements.

ADSP-TS201 TigerSHARC Processor Hardware Reference xxvii

Product Information

You may also obtain additional information about Analog Devices and its
products in any of the following ways.

• E-mail questions or requests for information to

[e-mail]

• Fax questions or requests for information to

1-781-461-3010 (North America)
089/76 903-557 (Europe)

• Access the FTP Web site at

ftp ftp.analog.com or ftp 137.71.23.21
ftp://ftp.analog.com

Related Documents

The following publications that describe the ADSP-TS201 TigerSHARC
processor (and related processors) can be ordered from any Analog Devices
sales office:

• ADSP-TS201S TigerSHARC Embedded Processor Data Sheet

• ADSP-TS202S TigerSHARC Embedded Processor Data Sheet

• ADSP-TS203S TigerSHARC Embedded Processor Data Sheet

• ADSP-TS201 TigerSHARC Processor Hardware Reference

• ADSP-TS201 TigerSHARC Processor Programming Reference

For information on product related development software and Analog
Devices processors, see these publications:

• VisualDSP++ User's Guide for TigerSHARC Processors

• VisualDSP++ C/C++ Compiler and Library Manual for

TigerSHARC Processors

xxviii ADSP-TS201 TigerSHARC Processor Hardware Reference

Preface

• VisualDSP++ Assembler and Preprocessor Manual for TigerSHARC
Processors

• VisualDSP++ Linker and Utilities Manual for TigerSHARC
Processors

• VisualDSP++ Kernel (VDK) User's Guide

Visit the Technical Library Web site to access all processor and tools
manuals and data sheets:

http://www.analog.com/processors/resources/technicalLibrary

Online Technical Documentation

Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, the Dinkum
Abridged C++ library, and Flexible License Manager (FlexLM) network
license manager software documentation. You can easily search across the
entire VisualDSP++ documentation set for any topic of interest. For easy
printing, supplementary .PDF files of most manuals are also provided.

Each documentation file type is described as follows.

File Description

.CHM Help system files and manuals in Help format

.HTM or
.HTML

.PDF VisualDSP++ and processor manuals in Portable Documentation Format (PDF).

Dinkum Abridged C++ library and FlexLM network license manager software doc­umentation. Viewing and printing the .HTML files requires a browser, such as
Internet Explorer 4.0 (or higher).

Viewing and printing the .PDF files requires a PDF reader, such as Adobe Acrobat
Reader (4.0 or higher).

ADSP-TS201 TigerSHARC Processor Hardware Reference xxix

Product Information

If documentation is not installed on your system as part of the software
installation, you can add it from the VisualDSP++ CD-ROM at any time
by running the Tools installation. Access the online documentation from
the VisualDSP++ environment, Windows® Explorer, or the Analog
Devices Web site.

Accessing Documentation From VisualDSP++

From the VisualDSP++ environment:

• Access VisualDSP++ online Help from the Help menu’s Contents,
Search, and Index commands.

• Open online Help from context-sensitive user interface items (tool­bar buttons, menu commands, and windows).

Accessing Documentation From Windows

In addition to any shortcuts you may have constructed, there are many
ways to open VisualDSP++ online Help or the supplementary documenta­tion from Windows.

Help system files (.

CHM) are located in the Help folder, and .PDF files are

located in the Docs folder of your VisualDSP++ installation CD-ROM.
The Docs folder also contains the Dinkum Abridged C++ library and the
FlexLM network license manager software documentation.

Using Windows Explorer

• Double-click the

vdsp-help.chm file, which is the master Help sys-

tem, to access all the other .CHM files.

• Double-click any file that is part of the VisualDSP++ documenta­tion set.

xxx ADSP-TS201 TigerSHARC Processor Hardware Reference