ANALOG DEVICES ADSP-BF59x Service Manual

a

ADSP-BF59x Blackfin® Processor

Hardware Reference

Revision 1.0, May 2011

Part Number

82-100102-01

Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Copyright Information

© 2011 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu­ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli­cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, TigerSHARC,
and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of
their respective owners.

CONTENTS

PREFACE

Purpose of This Manual ............................................................. xxxi

Intended Audience ....................................................................... xxxi

Manual Contents ........................................................................ xxxii

What’s New in This Manual ....................................................... xxxiv

Technical or Customer Support .................................................. xxxiv

Registration for MyAnalog.com ............................................. xxxv

EngineerZone ........................................................................ xxxv

Social Networking Web Sites ................................................ xxxvi

Supported Processors .................................................................. xxxvi

Product Information ................................................................. xxxvii

Analog Devices Web Site ..................................................... xxxvii

VisualDSP++ Online Documentation ................................ xxxviii

Technical Library CD ......................................................... xxxviii

Notation Conventions ................................................................ xxxix

INTRODUCTION

General Description of Processor ................................................... 1-1

Portable Low-Power Architecture ............................................. 1-2

ADSP-BF59x Blackfin Processor Hardware Reference i

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Peripherals .................................................................................... 1-3

Memory Architecture .................................................................... 1-4

Internal Memory ..................................................................... 1-5

I/O Memory Space .................................................................. 1-5

DMA Support .............................................................................. 1-6

General-Purpose I/O (GPIO) ........................................................ 1-7

Two-Wire Interface ....................................................................... 1-8

Parallel Peripheral Interface ........................................................... 1-9

SPORT Controllers .................................................................... 1-11

Serial Peripheral Interface (SPI) Ports .......................................... 1-13

Timers ....................................................................................... 1-13

UART Port ................................................................................. 1-14

Watchdog Timer ......................................................................... 1-15

Clock Signals .............................................................................. 1-16

Dynamic Power Management ..................................................... 1-16

Full-On Mode (Maximum Performance) ................................ 1-17

Active Mode (Moderate Power Savings) ................................. 1-17

Sleep Mode (High Power Savings) ......................................... 1-17

Deep Sleep Mode (Maximum Power Savings) ........................ 1-18

Hibernate State .................................................................... 1-18

Instruction Set Description ......................................................... 1-18

Development Tools ..................................................................... 1-19

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MEMORY

Memory Architecture .................................................................... 2-1

L1 Instruction SRAM ................................................................... 2-2

L1 Instruction ROM ..................................................................... 2-3

L1 Data SRAM ............................................................................. 2-3

Boot ROM ................................................................................... 2-4

External Memory .......................................................................... 2-4

Processor-Specific MMRs .............................................................. 2-4

DTEST_COMMAND Register ............................................... 2-5

ITEST_COMMAND Register ................................................. 2-6

DMEM_CONTROL Register ................................................. 2-7

IMEM_CONTROL Register ................................................... 2-7

DCPLB_DATAx Registers ....................................................... 2-8

ICPLB_DATAx Registers ......................................................... 2-9

CHIP BUS HIERARCHY

Chip Bus Hierarchy Overview ....................................................... 3-1

Interface Overview ........................................................................ 3-2

Internal Clocks ........................................................................ 3-3

Core Bus Overview .................................................................. 3-3

Peripheral Access Bus (PAB) ..................................................... 3-4

PAB Arbitration .................................................................. 3-5

PAB Agents (Masters, Slaves) ............................................... 3-5

PAB Performance ................................................................ 3-6

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DMA Access Bus (DAB), DMA Core Bus (DCB) .................... 3-6

DAB and DCB Arbitration ................................................. 3-6

DAB Bus Agents (Masters) .................................................. 3-7

DAB and DCB Performance ............................................... 3-8

SYSTEM INTERRUPTS

Specific Information for the ADSP-BF59x .................................... 4-1

Overview ...................................................................................... 4-1

Features .................................................................................. 4-2

Description of Operation .............................................................. 4-2

Events and Sequencing ............................................................ 4-2

System Peripheral Interrupts .................................................... 4-4

Programming Model ..................................................................... 4-7

System Interrupt Initialization ................................................. 4-7

System Interrupt Processing Summary ..................................... 4-8

System Interrupt Controller Registers .......................................... 4-10

System Interrupt Assignment (SIC_IAR) Register .................. 4-10

System Interrupt Mask (SIC_IMASK) Register ...................... 4-12

System Interrupt Status (SIC_ISR) Register ........................... 4-12

System Interrupt Wakeup-Enable (SIC_IWR) Register ........... 4-12

Programming Examples .............................................................. 4-13

Clearing Interrupt Requests ................................................... 4-13

Unique Information for the ADSP-BF59x Processor .................... 4-15

Interfaces .............................................................................. 4-15

System Peripheral Interrupts .................................................. 4-17

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DIRECT MEMORY ACCESS

Specific Information for the ADSP-BF59x ..................................... 5-1

Overview and Features .................................................................. 5-2

DMA Controller Overview ............................................................ 5-4

External Interfaces ................................................................... 5-4

Internal Interfaces ................................................................... 5-4

Peripheral DMA ...................................................................... 5-5

Memory DMA ........................................................................ 5-6

Handshaked Memory DMA (HMDMA) Mode ................... 5-8

Modes of Operation ...................................................................... 5-9

Register-Based DMA Operation ............................................... 5-9

Stop Mode ........................................................................ 5-11

Autobuffer Mode .............................................................. 5-11

Two-Dimensional DMA Operation ........................................ 5-11

Examples of Two-Dimensional DMA ................................ 5-12

Descriptor-based DMA Operation ......................................... 5-13

Descriptor List Mode ........................................................ 5-14

Descriptor Array Mode ..................................................... 5-15

Variable Descriptor Size .................................................... 5-15

Mixing Flow Modes .......................................................... 5-16

Functional Description ............................................................... 5-17

DMA Operation Flow ........................................................... 5-17

DMA Startup .................................................................... 5-17

DMA Refresh ................................................................... 5-22

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Work Unit Transitions ...................................................... 5-24

DMA Transmit and MDMA Source .............................. 5-25

DMA Receive ............................................................... 5-26

Stopping DMA Transfers .................................................. 5-28

DMA Errors (Aborts) ............................................................ 5-28

DMA Control Commands .................................................... 5-31

Restrictions ...................................................................... 5-34

Transmit Restart or Finish ............................................. 5-34

Receive Restart or Finish ............................................... 5-35

Handshaked Memory DMA Operation .................................. 5-36

Pipelining DMA Requests ................................................. 5-37

HMDMA Interrupts ......................................................... 5-39

DMA Performance ................................................................ 5-40

DMA Throughput ............................................................ 5-41

Memory DMA Timing Details .......................................... 5-44

Static Channel Prioritization ............................................ 5-44

Temporary DMA Urgency ................................................ 5-44

Memory DMA Priority and Scheduling ............................. 5-46

Traffic Control ................................................................. 5-48

Programming Model .................................................................. 5-50

Synchronization of Software and DMA .................................. 5-50

Single-Buffer DMA Transfers ............................................ 5-52

Continuous Transfers Using Autobuffering ........................ 5-53

Descriptor Structures ........................................................ 5-55

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Descriptor Queue Management ......................................... 5-56

Descriptor Queue Using Interrupts on Every Descriptor 5-57

Descriptor Queue Using Minimal Interrupts .................. 5-58

Software Triggered Descriptor Fetches ............................... 5-60

DMA Registers ........................................................................... 5-62

DMA Channel Registers ........................................................ 5-62

DMA Peripheral Map Registers DMAx_PERIPHERAL_MAP/

MDMA_yy_PERIPHERAL_MAP) ................................ 5-66

DMA Configuration Registers

(DMAx_CONFIG/MDMA_yy_CONFIG) ................... 5-67

DMA Interrupt Status Registers

(DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) ...... 5-71

DMA Start Address Registers

(DMAx_START_ADDR/MDMA_yy_START_ADDR) .. 5-74

DMA Current Address Registers

(DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) .... 5-74

DMA Inner Loop Count Registers

(DMAx_X_COUNT/MDMA_yy_X_COUNT) ............. 5-75

DMA Current Inner Loop Count Registers

(DMAx_CURR_X_COUNT

/MDMA_yy_CURR_X_COUNT) ................................. 5-76

DMA Inner Loop Address Increment Registers

(DMAx_X_MODIFY/MDMA_yy_X_MODIFY) ........... 5-77

DMA Outer Loop Count Registers

(DMAx_Y_COUNT/MDMA_yy_Y_COUNT) .............. 5-78

DMA Current Outer Loop Count Registers

(DMAx_CURR_Y_COUNT/

MDMA_yy_CURR_Y_COUNT) .................................. 5-78

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DMA Outer Loop Address Increment Registers

(DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY) ........... 5-79

DMA Next Descriptor Pointer Registers

(DMAx_NEXT_DESC_PTR/

MDMA_yy_NEXT_DESC_PTR) .................................. 5-80

DMA Current Descriptor Pointer Registers

(DMAx_CURR_DESC_PTR/

MDMA_yy_CURR_DESC_PTR) ................................. 5-81

HMDMA Registers ............................................................... 5-82

Handshake MDMA Control Registers

(HMDMAx_CONTROL) ............................................. 5-82

Handshake MDMA Initial Block Count Registers

(HMDMAx_BCINIT) ................................................... 5-84

Handshake MDMA Current Block Count Registers

(HMDMAx_BCOUNT) ............................................... 5-84

Handshake MDMA Current Edge Count Registers

(HMDMAx_ECOUNT) ............................................... 5-85

Handshake MDMA Initial Edge Count Registers

(HMDMAx_ECINIT) ................................................... 5-86

Handshake MDMA Edge Count Urgent Registers

(HMDMAx_ECURGENT) ........................................... 5-87

Handshake MDMA Edge Count Overflow Interrupt

Registers (HMDMAx_ECOVERFLOW) ........................ 5-87

DMA Traffic Control Registers

(DMA_TC_PER and DMA_TC_CNT) ............................. 5-88

DMA_TC_PER Register .................................................. 5-88

DMA_TC_CNT Register ................................................. 5-88

Programming Examples .............................................................. 5-90

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Register-Based 2-D Memory DMA ........................................ 5-90

Initializing Descriptors in Memory ........................................ 5-93

Software-Triggered Descriptor Fetch Example ........................ 5-96

Handshaked Memory DMA Example ..................................... 5-99

Unique Information for the ADSP-BF59x Processor .................. 5-101

Static Channel Prioritization ............................................... 5-101

DYNAMIC POWER MANAGEMENT

Phase Locked Loop and Clock Control .......................................... 6-1

PLL Overview ......................................................................... 6-2

PLL Clock Multiplier Ratios .................................................... 6-3

Core Clock/System Clock Ratio Control ............................. 6-5

Dynamic Power Management Controller ....................................... 6-7

Operating Modes ..................................................................... 6-7

Dynamic Power Management Controller States ........................ 6-8

Full-On Mode ................................................................... 6-8

Active Mode ...................................................................... 6-8

Sleep Mode ........................................................................ 6-9

Deep Sleep Mode ............................................................... 6-9

Hibernate State ................................................................ 6-10

Operating Mode Transitions .................................................. 6-10

Programming Operating Mode Transitions ............................. 6-13

Dynamic Supply Voltage Control ........................................... 6-15

Power Supply Management .................................................... 6-15

Changing Voltage .............................................................. 6-15

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Powering Down the Core (Hibernate State) ....................... 6-17

PLL and VR Registers ................................................................. 6-18

PLL_DIV Register ................................................................ 6-19

PLL_CTL Register ................................................................ 6-20

PLL_STAT Register .............................................................. 6-20

PLL_LOCKCNT Register ..................................................... 6-21

VR_CTL Register ................................................................. 6-21

System Control ROM Function .................................................. 6-22

Programming Model ............................................................. 6-24

Accessing the System Control ROM Function in C/C++ ........ 6-24

Accessing the System Control ROM Function in Assembly .... 6-25

Programming Examples .............................................................. 6-28

Full-on Mode to Active Mode and Back ................................. 6-30

Transition to Sleep Mode or Deep Sleep Mode ....................... 6-32

Set Wakeup Events and Enter Hibernate State ........................ 6-33

Perform a System Reset or Soft-Reset ..................................... 6-35

In Full-on Mode, Change VCO Frequency, Core Clock

Frequency, and System Clock Frequency ............................. 6-36

Changing Voltage Levels ....................................................... 6-38

GENERAL-PURPOSE PORTS

Overview ...................................................................................... 7-1

Features ........................................................................................ 7-1

Interface Overview ....................................................................... 7-2

External Interface .................................................................... 7-3

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Port F Structure .................................................................. 7-3

Port G Structure ................................................................. 7-4

Additional Considerations ................................................... 7-5

Internal Interfaces ................................................................... 7-6

Performance/Throughput ........................................................ 7-6

Description of Operation .............................................................. 7-7

Operation ............................................................................... 7-7

General-Purpose I/O Modules ................................................. 7-8

GPIO Interrupt Processing .................................................... 7-11

Programming Model ................................................................... 7-17

GPIO Schmitt Trigger Control .................................................... 7-19

PORTx Pad Control Registers ................................................ 7-19

Memory-Mapped GPIO Registers ............................................... 7-20

Port Multiplexer Control Register (PORTx_MUX) ................ 7-21

Function Enable Registers (PORTx_FER) .............................. 7-22

GPIO Direction Registers (PORTxIO_DIR) .......................... 7-22

GPIO Input Enable Registers (PORTxIO_INEN) .................. 7-23

GPIO Data Registers (PORTxIO) .......................................... 7-23

GPIO Set Registers (PORTxIO_SET) .................................... 7-24

GPIO Clear Registers (PORTxIO_CLEAR) ........................... 7-24

GPIO Toggle Registers (PORTxIO_TOGGLE) ...................... 7-25

GPIO Polarity Registers (PORTxIO_POLAR) ....................... 7-25

Interrupt Sensitivity Registers (PORTxIO_EDGE) ................. 7-26

GPIO Set on Both Edges Registers (PORTxIO_BOTH) ......... 7-26

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GPIO Mask Interrupt Registers (PORTxIO_MASKA/B) ....... 7-27

GPIO Mask Interrupt Set Registers

(PORTxIO_MASKA/B_SET) ............................................ 7-28

GPIO Mask Interrupt Clear Registers

(PORTxIO_MASKA/B_CLEAR) ....................................... 7-30

GPIO Mask Interrupt Toggle Registers

(PORTxIO_MASKA/B_TOGGLE) .................................... 7-32

Programming Examples .............................................................. 7-33

GENERAL-PURPOSE TIMERS

Specific Information for the ADSP-BF59x .................................... 8-1

Overview ...................................................................................... 8-2

External Interface .................................................................... 8-3

Internal Interface .................................................................... 8-4

Description of Operation .............................................................. 8-4

Interrupt Processing ................................................................ 8-5

Illegal States ............................................................................ 8-7

Modes of Operation ................................................................... 8-10

Pulse Width Modulation (PWM_OUT) Mode ...................... 8-10

Output Pad Disable .......................................................... 8-12

Single Pulse Generation .................................................... 8-12

Pulse Width Modulation Waveform Generation ................ 8-13

PULSE_HI Toggle Mode .................................................. 8-15

Externally Clocked PWM_OUT ....................................... 8-20

Using PWM_OUT Mode With the PPI ............................ 8-21

Stopping the Timer in PWM_OUT Mode ........................ 8-21

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Pulse Width Count and Capture (WDTH_CAP) Mode ......... 8-23

Autobaud Mode ................................................................ 8-31

External Event (EXT_CLK) Mode ......................................... 8-32

Programming Model ................................................................... 8-33

Timer Registers ........................................................................... 8-34

Timer Enable Register (TIMER_ENABLE) ............................ 8-35

Timer Disable Register (TIMER_DISABLE) .......................... 8-36

Timer Status Register (TIMER_STATUS) .............................. 8-38

Timer Configuration Register (TIMER_CONFIG) ................ 8-40

Timer Counter Register (TIMER_COUNTER) ..................... 8-41

Timer Period (TIMER_PERIOD) and Timer

Width (TIMER_WIDTH) Registers ................................... 8-42

Summary .............................................................................. 8-45

Programming Examples ............................................................... 8-47

Unique Information for the ADSP-BF59x Processor .................... 8-56

Interface Overview ................................................................ 8-57

External Interface .............................................................. 8-58

CORE TIMER

Specific Information for the ADSP-BF59x ..................................... 9-1

Overview and Features .................................................................. 9-1

Timer Overview ............................................................................ 9-2

External Interfaces ................................................................... 9-2

Internal Interfaces ................................................................... 9-3

Description of Operation .............................................................. 9-3

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Interrupt Processing ................................................................ 9-3

Core Timer Registers .................................................................... 9-4

Core Timer Control Register (TCNTL) ................................... 9-5

Core Timer Count Register (TCOUNT) ................................. 9-5

Core Timer Period Register (TPERIOD) ................................. 9-6

Core Timer Scale Register (TSCALE) ...................................... 9-7

Programming Examples ................................................................ 9-7

Unique Information for the ADSP-BF59x Processor ...................... 9-9

WAT CH DO G TIMER

Specific Information for the ADSP-BF59x .................................. 10-1

Overview and Features ................................................................ 10-1

Interface Overview ..................................................................... 10-3

External Interface .................................................................. 10-3

Internal Interface .................................................................. 10-3

Description of Operation ............................................................ 10-4

Register Definitions .................................................................... 10-5

Watchdog Count (WDOG_CNT) Register ........................... 10-5

Watchdog Status (WDOG_STAT) Register ........................... 10-6

Watchdog Control (WDOG_CTL) Register .......................... 10-7

Programming Examples .............................................................. 10-8

Unique Information for the ADSP-BF59x Processor .................. 10-10

UART PORT CONTROLLERS

Specific Information for the ADSP-BF59x .................................. 11-1

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Overview .................................................................................... 11-2

Features ...................................................................................... 11-2

Interface Overview ...................................................................... 11-3

External Interface .................................................................. 11-3

Internal Interface ................................................................... 11-4

Description of Operation ............................................................ 11-5

UART Transfer Protocol ........................................................ 11-5

UART Transmit Operation .................................................... 11-6

UART Receive Operation ...................................................... 11-7

IrDA Transmit Operation ...................................................... 11-8

IrDA Receive Operation ........................................................ 11-9

Interrupt Processing ............................................................ 11-11

Bit Rate Generation ............................................................. 11-12

Autobaud Detection ............................................................ 11-13

Programming Model ................................................................. 11-15

Non-DMA Mode ................................................................ 11-15

DMA Mode ........................................................................ 11-17

Mixing Modes ..................................................................... 11-18

UART Registers ........................................................................ 11-19

UART Line Control (UART_LCR) Register ......................... 11-21

UART Modem Control (UART_MCR) Register .................. 11-23

UART Line Status (UART_LSR) Register ............................ 11-24

UART Transmit Holding (UART_THR) Register ................ 11-25

UART Receive Buffer (UART_RBR) Register ...................... 11-26

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UART Interrupt Enable (UART_IER) Register .................... 11-26

UART Interrupt Identification (UART_IIR) Register ........... 11-28

UART Divisor Latch

(UART_DLL and UART_DLH) Registers ........................ 11-29

UART Scratch (UART_SCR) Register ................................. 11-30

UART Global Control (UART_GCTL) Register .................. 11-31

Programming Examples ............................................................ 11-32

Unique Information for the ADSP-BF59x Processor .................. 11-41

TWO WIRE INTERFACE CONTROLLER

Specific Information for the ADSP-BF59x .................................. 12-1

Overview .................................................................................... 12-2

Interface Overview ..................................................................... 12-3

External Interface .................................................................. 12-4

Serial Clock Signal (SCL) ................................................. 12-4

Serial Data Signal (SDA) .................................................. 12-4

TWI Pins ......................................................................... 12-5

Internal Interfaces ................................................................. 12-5

Description of Operation ............................................................ 12-6

TWI Transfer Protocols ......................................................... 12-6

Clock Generation and Synchronization ............................. 12-7

Bus Arbitration ................................................................. 12-8

Start and Stop Conditions ................................................. 12-8

General Call Support ........................................................ 12-9

Fast Mode ...................................................................... 12-10

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Functional Description ............................................................. 12-10

General Setup ...................................................................... 12-10

Slave Mode .......................................................................... 12-11

Master Mode Clock Setup ................................................... 12-12

Master Mode Transmit ........................................................ 12-12

Master Mode Receive ........................................................... 12-14

Repeated Start Condition ................................................ 12-15

Transmit/Receive Repeated Start Sequence ................... 12-15

Receive/Transmit Repeated Start Sequence ................... 12-16

Clock Stretching ............................................................. 12-17

Clock Stretching During FIFO Underflow ....................... 12-17

Clock Stretching During FIFO Overflow ......................... 12-19

Clock Stretching During Repeated Start Condition .......... 12-20

Programming Model ................................................................. 12-22

Register Descriptions ................................................................ 12-24

TWI CONTROL Register (TWI_CONTROL) ................... 12-24

SCL Clock Divider Register (TWI_CLKDIV) ...................... 12-25

TWI Slave Mode Control Register (TWI_SLAVE_CTL) ...... 12-26

TWI Slave Mode Address Register (TWI_SLAVE_ADDR) ... 12-28

TWI Slave Mode Status Register (TWI_SLAVE_STAT) ....... 12-28

TWI Master Mode Control Register

(TWI_MASTER_CTL) .................................................... 12-29

TWI Master Mode Address Register

(TWI_MASTER_ADDR) ................................................ 12-32

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TWI Master Mode Status Register

(TWI_MASTER_STAT) .................................................. 12-33

TWI FIFO Control Register (TWI_FIFO_CTL) ................. 12-36

TWI FIFO Status Register (TWI_FIFO_STAT) .................. 12-38

TWI FIFO Status ........................................................... 12-38

TWI Interrupt Mask Register (TWI_INT_MASK) .............. 12-39

TWI Interrupt Status Register (TWI_INT_STAT) .............. 12-40

TWI FIFO Transmit Data Single Byte

Register (TWI_XMT_DATA8) ......................................... 12-43

TWI FIFO Transmit Data Double Byte

Register (TWI_XMT_DATA16) ....................................... 12-43

TWI FIFO Receive Data Single Byte

Register (TWI_RCV_DATA8) ......................................... 12-44

TWI FIFO Receive Data Double Byte

Register (TWI_RCV_DATA16) ........................................ 12-45

Programming Examples ............................................................ 12-46

Master Mode Setup ............................................................. 12-46

Slave Mode Setup ................................................................ 12-50

Electrical Specifications ............................................................ 12-56

Unique Information for the ADSP-BF59x Processor .................. 12-56

SPI-COMPATIBLE PORT CONTROLLER

Specific Information for the ADSP-BF59x .................................. 13-1

Overview .................................................................................... 13-2

Features ...................................................................................... 13-2

Interface Overview ..................................................................... 13-3

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External Interface .................................................................. 13-4

SPI Clock Signal (SCK) ................................................... 13-4

Master-Out, Slave-In (MOSI) Signal ................................. 13-5

Master-In, Slave-Out (MISO) Signal ................................. 13-5

SPI Slave Select Input Signal (SPISS) ................................. 13-6

SPI Slave Select Enable Output Signals .............................. 13-6

Slave Select Inputs ............................................................ 13-7

Use of FLS Bits in SPI_FLG for Multiple Slave SPI

Systems .......................................................................... 13-8

Internal Interfaces ............................................................... 13-10

DMA Functionality ........................................................ 13-10

Description of Operation .......................................................... 13-11

SPI Transfer Protocols ......................................................... 13-11

SPI General Operation ........................................................ 13-14

Clock Signals ...................................................................... 13-15

Interrupt Output ................................................................. 13-16

Functional Description ............................................................. 13-16

Master Mode Operation (Non-DMA) .................................. 13-17

Transfer Initiation From Master (Transfer Modes) ................ 13-18

Slave Mode Operation (Non-DMA) ..................................... 13-19

Slave Ready for a Transfer .................................................... 13-21

Programming Model ................................................................. 13-21

Beginning and Ending an SPI Transfer ................................. 13-21

Master Mode DMA Operation ............................................. 13-23

Slave Mode DMA Operation ............................................... 13-26

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SPI Registers ............................................................................ 13-33

SPI Baud Rate (SPI_BAUD) Register .................................. 13-34

SPI Control (SPI_CTL) Register ......................................... 13-35

SPI Flag (SPI_FLG) Register ............................................... 13-37

SPI Status (SPI_STAT) Register ........................................... 13-38

Mode Fault Error (MODF) ............................................. 13-39

Transmission Error (TXE) .............................................. 13-40

Reception Error (RBSY) ................................................. 13-41

Transmit Collision Error (TXCOL) ................................. 13-41

SPI Transmit Data Buffer (SPI_TDBR) Register .................. 13-41

SPI Receive Data Buffer (SPI_RDBR) Register .................... 13-42

SPI RDBR Shadow (SPI_SHADOW) Register ..................... 13-43

Programming Examples ............................................................ 13-43

Core-Generated Transfer ..................................................... 13-43

Initialization Sequence .................................................... 13-44

Starting a Transfer .......................................................... 13-45

Post Transfer and Next Transfer ...................................... 13-46

Stopping ........................................................................ 13-46

DMA-Based Transfer ........................................................... 13-47

DMA Initialization Sequence .......................................... 13-47

SPI Initialization Sequence ............................................. 13-48

Starting a Transfer .......................................................... 13-49

Stopping a Transfer ......................................................... 13-50

Unique Information for the ADSP-BF59x Processor .................. 13-52

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SPORT CONTROLLER

Specific Information for the ADSP-BF59x ................................... 14-1

Overview .................................................................................... 14-2

Features ................................................................................. 14-2

Interface Overview ...................................................................... 14-4

SPORT Pin/Line Terminations .............................................. 14-8

Description of Operation ............................................................ 14-9

SPORT Disable ..................................................................... 14-9

Setting SPORT Modes ........................................................ 14-10

Stereo Serial Operation ........................................................ 14-10

Multichannel Operation ...................................................... 14-14

Multichannel Enable ....................................................... 14-17

Frame Syncs in Multichannel Mode ................................. 14-18

The Multichannel Frame ................................................. 14-19

Multichannel Frame Delay .............................................. 14-20

Window Size ................................................................... 14-20

Window Offset ............................................................... 14-21

Other Multichannel Fields in SPORT_MCMC2 .............. 14-21

Channel Selection Register .............................................. 14-22

Multichannel DMA Data Packing ................................... 14-23

Support for H.100 Standard Protocol ................................... 14-24

2× Clock Recovery Control ............................................. 14-24

Functional Description ............................................................. 14-25

Clock and Frame Sync Frequencies ...................................... 14-25

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Maximum Clock Rate Restrictions .................................. 14-26

Word Length ...................................................................... 14-27

Bit Order ............................................................................ 14-27

Data Type ........................................................................... 14-27

Companding ....................................................................... 14-28

Clock Signal Options .......................................................... 14-29

Frame Sync Options ............................................................ 14-30

Framed Versus Unframed ................................................ 14-30

Internal Versus External Frame Syncs .............................. 14-31

Active Low Versus Active High Frame Syncs .................... 14-32

Sampling Edge for Data and Frame Syncs ........................ 14-32

Early Versus Late Frame Syncs (Normal Versus

Alternate Timing) ........................................................ 14-34

Data Independent Transmit Frame Sync .......................... 14-36

Moving Data Between SPORTs and Memory ....................... 14-37

SPORT RX, TX, and Error Interrupts ................................. 14-37

Peripheral Bus Errors ........................................................... 14-38

Timing Examples ................................................................ 14-38

SPORT Registers ...................................................................... 14-44

Register Writes and Effective Latency .................................. 14-45

SPORT Transmit Configuration

(SPORT_TCR1 and SPORT_TCR2) Registers ................. 14-46

SPORT Receive Configuration

(SPORT_RCR1 and SPORT_RCR2) Registers ................. 14-51

Data Word Formats ............................................................. 14-55

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SPORT Transmit Data (SPORT_TX) Register ..................... 14-56

SPORT Receive Data (SPORT_RX) Register ....................... 14-58

SPORT Status (SPORT_STAT) Register .............................. 14-60

SPORT Transmit and Receive Serial Clock Divider

(SPORT_TCLKDIV and SPORT_RCLKDIV) Registers ... 14-61

SPORT Transmit and Receive Frame Sync Divider

(SPORT_TFSDIV and SPORT_RFSDIV) Registers .......... 14-62

SPORT Multichannel Configuration

(SPORT_MCMC1 and SPORT_MCMC2) Registers ........ 14-63

SPORT Current Channel (SPORT_CHNL) Register ........... 14-64

SPORT Multichannel Receive Selection

(SPORT_MRCSn) Registers ............................................. 14-65

SPORT Multichannel Transmit Selection

(SPORT_MTCSn) Registers ............................................. 14-66

Programming Examples ............................................................. 14-67

SPORT Initialization Sequence ............................................ 14-68

DMA Initialization Sequence ............................................... 14-70

Interrupt Servicing .............................................................. 14-72

Starting a Transfer ............................................................... 14-73

Unique Information for the ADSP-BF59x Processor .................. 14-73

Clock Gating Functionality ................................................. 14-74

Modes of Operation ............................................................ 14-75

Gated Clock Mode 0 – SPORT Gated Clocks Without

Using TIMERs ............................................................. 14-75

Gated Clock Mode 1 – SPORT Gated Clocks Using

TIMERs ...................................................................... 14-75

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Programming Model ....................................................... 14-76

PARALLEL PERIPHERAL INTERFACE

Specific Information for the ADSP-BF59x .................................. 15-1

Overview .................................................................................... 15-2

Features ...................................................................................... 15-2

Interface Overview ..................................................................... 15-3

Description of Operation ............................................................ 15-4

Functional Description ............................................................... 15-5

ITU-R 656 Modes ................................................................ 15-5

ITU-R 656 Background .................................................... 15-5

ITU-R 656 Input Modes .................................................. 15-9

Entire Field .................................................................. 15-9

Active Video Only ...................................................... 15-10

Vertical Blanking Interval (VBI) only .......................... 15-10

ITU-R 656 Output Mode ............................................... 15-11

Frame Synchronization in ITU-R 656 Modes .................. 15-11

General-Purpose PPI Modes ................................................ 15-12

Data Input (RX) Modes .................................................. 15-14

No Frame Syncs .......................................................... 15-14

1, 2, or 3 External Frame Syncs ................................... 15-15

2 or 3 Internal Frame Syncs ........................................ 15-16

Data Output (TX) Modes ............................................... 15-16

No Frame Syncs .......................................................... 15-17

1 or 2 External Frame Syncs ........................................ 15-17

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1, 2, or 3 Internal Frame Syncs .................................... 15-18

Frame Synchronization in GP Modes ............................... 15-19

Modes With Internal Frame Syncs ............................... 15-19

Modes With External Frame Syncs .............................. 15-20

Programming Model ................................................................. 15-21

DMA Operation .................................................................. 15-22

PPI Registers ............................................................................. 15-25

PPI Control Register (PPI_CONTROL) .............................. 15-25

PPI Status Register (PPI_STATUS) ...................................... 15-29

PPI Delay Count Register (PPI_DELAY) ............................. 15-32

PPI Transfer Count Register (PPI_COUNT) ....................... 15-32

PPI Lines Per Frame Register (PPI_FRAME) ........................ 15-33

Programming Examples ............................................................. 15-34

Unique Information for the ADSP-BF59x Processor .................. 15-37

SYSTEM RESET AND BOOTING

Overview .................................................................................... 16-1

Reset and Power-up .................................................................... 16-3

Hardware Reset ..................................................................... 16-4

Software Resets ...................................................................... 16-5

Reset Vector .......................................................................... 16-6

Servicing Reset Interrupts ...................................................... 16-6

Basic Booting Process .................................................................. 16-8

Block Headers ..................................................................... 16-10

Block Code ..................................................................... 16-12

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DMA Code Field ........................................................ 16-12

Block Flags Field ......................................................... 16-14

Header Checksum Field .............................................. 16-15

Header Sign Field ....................................................... 16-16

Target Address ................................................................ 16-16

Byte Count ..................................................................... 16-17

Argument ....................................................................... 16-17

Boot Host Wait (HWAIT) Feedback Strobe ......................... 16-18

Using HWAIT as Reset Indicator .................................... 16-19

Boot Termination ............................................................... 16-19

Single Block Boot Streams ................................................... 16-20

Advanced Boot Techniques ....................................................... 16-21

Initialization Code .............................................................. 16-21

Quick Boot ......................................................................... 16-25

Indirect Booting .................................................................. 16-26

Callback Routines ............................................................... 16-27

Error Handler ..................................................................... 16-30

CRC Checksum Calculation ................................................ 16-30

Load Functions ................................................................... 16-30

Calling the Boot Kernel at Runtime .................................... 16-32

Debugging the Boot Process ................................................ 16-32

Boot Management .................................................................... 16-35

Booting a Different Application .......................................... 16-35

Multi-DXE Boot Streams ................................................ 16-36

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Determining Boot Stream Start Addresses ........................ 16-37

Initialization Hook Routine ............................................ 16-38

Specific Boot Modes .................................................................. 16-38

No Boot Mode .................................................................... 16-39

SPI Master Boot Modes ....................................................... 16-40

SPI Device Detection Routine ......................................... 16-42

SPI Slave Boot Mode ........................................................... 16-44

PPI Boot Mode ................................................................... 16-47

UART Slave Mode Boot ...................................................... 16-49

L1 ROM Boot Mode ........................................................... 16-51

Reset and Booting Registers ....................................................... 16-51

Software Reset (SWRST) Register ........................................ 16-52

System Reset Configuration (SYSCR) Register ..................... 16-54

Boot Code Revision Control (BK_REVISION) .................... 16-55

Boot Code Date Code (BK_DATECODE) .......................... 16-56

Zero Word (BK_ZEROS) .................................................... 16-57

Ones Word (BK_ONES) ..................................................... 16-58

Data Structures ......................................................................... 16-58

ADI_BOOT_HEADER ...................................................... 16-59

ADI_BOOT_BUFFER ........................................................ 16-59

ADI_BOOT_DATA ............................................................ 16-59

dFlags Word ................................................................... 16-63

Callable ROM Functions for Booting ........................................ 16-64

BFROM_FINALINIT ......................................................... 16-64

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BFROM_PDMA ................................................................ 16-65

BFROM_MDMA .............................................................. 16-65

BFROM_SPIBOOT ........................................................... 16-66

BFROM_BOOTKERNEL .................................................. 16-68

BFROM_CRC32 ................................................................ 16-68

BFROM_CRC32POLY ....................................................... 16-69

BFROM_CRC32CALLBACK ............................................. 16-70

BFROM_CRC32INITCODE ............................................. 16-70

Programming Examples ............................................................ 16-71

System Reset ....................................................................... 16-71

Exiting Reset to User Mode ................................................. 16-72

Exiting Reset to Supervisor Mode ........................................ 16-72

Initcode (Power Management Control) ................................ 16-73

XOR Checksum .................................................................. 16-75

SYSTEM DESIGN

Pin Descriptions ......................................................................... 17-1

Managing Clocks ........................................................................ 17-1

Managing Core and System Clocks ........................................ 17-2

Configuring and Servicing Interrupts .......................................... 17-2

Data Delays, Latencies and Throughput ...................................... 17-2

Bus Priorities .............................................................................. 17-3

High-Frequency Design Considerations ...................................... 17-3

Signal Integrity ..................................................................... 17-3

Decoupling Capacitors and Ground Planes ............................ 17-4

xxviii ADSP-BF59x Blackfin Processor Hardware Reference