ANALOG DEVICES ADSP-BF59x Service Manual

a

ADSP-BF59x Blackfin® Processor

Hardware Reference

Revision 1.0, May 2011

Part Number

82-100102-01

Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Copyright Information

© 2011 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu­ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli­cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, TigerSHARC,
and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of
their respective owners.

CONTENTS

PREFACE

Purpose of This Manual ............................................................. xxxi

Intended Audience ....................................................................... xxxi

Manual Contents ........................................................................ xxxii

What’s New in This Manual ....................................................... xxxiv

Technical or Customer Support .................................................. xxxiv

Registration for MyAnalog.com ............................................. xxxv

EngineerZone ........................................................................ xxxv

Social Networking Web Sites ................................................ xxxvi

Supported Processors .................................................................. xxxvi

Product Information ................................................................. xxxvii

Analog Devices Web Site ..................................................... xxxvii

VisualDSP++ Online Documentation ................................ xxxviii

Technical Library CD ......................................................... xxxviii

Notation Conventions ................................................................ xxxix

INTRODUCTION

General Description of Processor ................................................... 1-1

Portable Low-Power Architecture ............................................. 1-2

ADSP-BF59x Blackfin Processor Hardware Reference i

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Peripherals .................................................................................... 1-3

Memory Architecture .................................................................... 1-4

Internal Memory ..................................................................... 1-5

I/O Memory Space .................................................................. 1-5

DMA Support .............................................................................. 1-6

General-Purpose I/O (GPIO) ........................................................ 1-7

Two-Wire Interface ....................................................................... 1-8

Parallel Peripheral Interface ........................................................... 1-9

SPORT Controllers .................................................................... 1-11

Serial Peripheral Interface (SPI) Ports .......................................... 1-13

Timers ....................................................................................... 1-13

UART Port ................................................................................. 1-14

Watchdog Timer ......................................................................... 1-15

Clock Signals .............................................................................. 1-16

Dynamic Power Management ..................................................... 1-16

Full-On Mode (Maximum Performance) ................................ 1-17

Active Mode (Moderate Power Savings) ................................. 1-17

Sleep Mode (High Power Savings) ......................................... 1-17

Deep Sleep Mode (Maximum Power Savings) ........................ 1-18

Hibernate State .................................................................... 1-18

Instruction Set Description ......................................................... 1-18

Development Tools ..................................................................... 1-19

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MEMORY

Memory Architecture .................................................................... 2-1

L1 Instruction SRAM ................................................................... 2-2

L1 Instruction ROM ..................................................................... 2-3

L1 Data SRAM ............................................................................. 2-3

Boot ROM ................................................................................... 2-4

External Memory .......................................................................... 2-4

Processor-Specific MMRs .............................................................. 2-4

DTEST_COMMAND Register ............................................... 2-5

ITEST_COMMAND Register ................................................. 2-6

DMEM_CONTROL Register ................................................. 2-7

IMEM_CONTROL Register ................................................... 2-7

DCPLB_DATAx Registers ....................................................... 2-8

ICPLB_DATAx Registers ......................................................... 2-9

CHIP BUS HIERARCHY

Chip Bus Hierarchy Overview ....................................................... 3-1

Interface Overview ........................................................................ 3-2

Internal Clocks ........................................................................ 3-3

Core Bus Overview .................................................................. 3-3

Peripheral Access Bus (PAB) ..................................................... 3-4

PAB Arbitration .................................................................. 3-5

PAB Agents (Masters, Slaves) ............................................... 3-5

PAB Performance ................................................................ 3-6

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DMA Access Bus (DAB), DMA Core Bus (DCB) .................... 3-6

DAB and DCB Arbitration ................................................. 3-6

DAB Bus Agents (Masters) .................................................. 3-7

DAB and DCB Performance ............................................... 3-8

SYSTEM INTERRUPTS

Specific Information for the ADSP-BF59x .................................... 4-1

Overview ...................................................................................... 4-1

Features .................................................................................. 4-2

Description of Operation .............................................................. 4-2

Events and Sequencing ............................................................ 4-2

System Peripheral Interrupts .................................................... 4-4

Programming Model ..................................................................... 4-7

System Interrupt Initialization ................................................. 4-7

System Interrupt Processing Summary ..................................... 4-8

System Interrupt Controller Registers .......................................... 4-10

System Interrupt Assignment (SIC_IAR) Register .................. 4-10

System Interrupt Mask (SIC_IMASK) Register ...................... 4-12

System Interrupt Status (SIC_ISR) Register ........................... 4-12

System Interrupt Wakeup-Enable (SIC_IWR) Register ........... 4-12

Programming Examples .............................................................. 4-13

Clearing Interrupt Requests ................................................... 4-13

Unique Information for the ADSP-BF59x Processor .................... 4-15

Interfaces .............................................................................. 4-15

System Peripheral Interrupts .................................................. 4-17

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DIRECT MEMORY ACCESS

Specific Information for the ADSP-BF59x ..................................... 5-1

Overview and Features .................................................................. 5-2

DMA Controller Overview ............................................................ 5-4

External Interfaces ................................................................... 5-4

Internal Interfaces ................................................................... 5-4

Peripheral DMA ...................................................................... 5-5

Memory DMA ........................................................................ 5-6

Handshaked Memory DMA (HMDMA) Mode ................... 5-8

Modes of Operation ...................................................................... 5-9

Register-Based DMA Operation ............................................... 5-9

Stop Mode ........................................................................ 5-11

Autobuffer Mode .............................................................. 5-11

Two-Dimensional DMA Operation ........................................ 5-11

Examples of Two-Dimensional DMA ................................ 5-12

Descriptor-based DMA Operation ......................................... 5-13

Descriptor List Mode ........................................................ 5-14

Descriptor Array Mode ..................................................... 5-15

Variable Descriptor Size .................................................... 5-15

Mixing Flow Modes .......................................................... 5-16

Functional Description ............................................................... 5-17

DMA Operation Flow ........................................................... 5-17

DMA Startup .................................................................... 5-17

DMA Refresh ................................................................... 5-22

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Work Unit Transitions ...................................................... 5-24

DMA Transmit and MDMA Source .............................. 5-25

DMA Receive ............................................................... 5-26

Stopping DMA Transfers .................................................. 5-28

DMA Errors (Aborts) ............................................................ 5-28

DMA Control Commands .................................................... 5-31

Restrictions ...................................................................... 5-34

Transmit Restart or Finish ............................................. 5-34

Receive Restart or Finish ............................................... 5-35

Handshaked Memory DMA Operation .................................. 5-36

Pipelining DMA Requests ................................................. 5-37

HMDMA Interrupts ......................................................... 5-39

DMA Performance ................................................................ 5-40

DMA Throughput ............................................................ 5-41

Memory DMA Timing Details .......................................... 5-44

Static Channel Prioritization ............................................ 5-44

Temporary DMA Urgency ................................................ 5-44

Memory DMA Priority and Scheduling ............................. 5-46

Traffic Control ................................................................. 5-48

Programming Model .................................................................. 5-50

Synchronization of Software and DMA .................................. 5-50

Single-Buffer DMA Transfers ............................................ 5-52

Continuous Transfers Using Autobuffering ........................ 5-53

Descriptor Structures ........................................................ 5-55

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Descriptor Queue Management ......................................... 5-56

Descriptor Queue Using Interrupts on Every Descriptor 5-57

Descriptor Queue Using Minimal Interrupts .................. 5-58

Software Triggered Descriptor Fetches ............................... 5-60

DMA Registers ........................................................................... 5-62

DMA Channel Registers ........................................................ 5-62

DMA Peripheral Map Registers DMAx_PERIPHERAL_MAP/

MDMA_yy_PERIPHERAL_MAP) ................................ 5-66

DMA Configuration Registers

(DMAx_CONFIG/MDMA_yy_CONFIG) ................... 5-67

DMA Interrupt Status Registers

(DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) ...... 5-71

DMA Start Address Registers

(DMAx_START_ADDR/MDMA_yy_START_ADDR) .. 5-74

DMA Current Address Registers

(DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) .... 5-74

DMA Inner Loop Count Registers

(DMAx_X_COUNT/MDMA_yy_X_COUNT) ............. 5-75

DMA Current Inner Loop Count Registers

(DMAx_CURR_X_COUNT

/MDMA_yy_CURR_X_COUNT) ................................. 5-76

DMA Inner Loop Address Increment Registers

(DMAx_X_MODIFY/MDMA_yy_X_MODIFY) ........... 5-77

DMA Outer Loop Count Registers

(DMAx_Y_COUNT/MDMA_yy_Y_COUNT) .............. 5-78

DMA Current Outer Loop Count Registers

(DMAx_CURR_Y_COUNT/

MDMA_yy_CURR_Y_COUNT) .................................. 5-78

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DMA Outer Loop Address Increment Registers

(DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY) ........... 5-79

DMA Next Descriptor Pointer Registers

(DMAx_NEXT_DESC_PTR/

MDMA_yy_NEXT_DESC_PTR) .................................. 5-80

DMA Current Descriptor Pointer Registers

(DMAx_CURR_DESC_PTR/

MDMA_yy_CURR_DESC_PTR) ................................. 5-81

HMDMA Registers ............................................................... 5-82

Handshake MDMA Control Registers

(HMDMAx_CONTROL) ............................................. 5-82

Handshake MDMA Initial Block Count Registers

(HMDMAx_BCINIT) ................................................... 5-84

Handshake MDMA Current Block Count Registers

(HMDMAx_BCOUNT) ............................................... 5-84

Handshake MDMA Current Edge Count Registers

(HMDMAx_ECOUNT) ............................................... 5-85

Handshake MDMA Initial Edge Count Registers

(HMDMAx_ECINIT) ................................................... 5-86

Handshake MDMA Edge Count Urgent Registers

(HMDMAx_ECURGENT) ........................................... 5-87

Handshake MDMA Edge Count Overflow Interrupt

Registers (HMDMAx_ECOVERFLOW) ........................ 5-87

DMA Traffic Control Registers

(DMA_TC_PER and DMA_TC_CNT) ............................. 5-88

DMA_TC_PER Register .................................................. 5-88

DMA_TC_CNT Register ................................................. 5-88

Programming Examples .............................................................. 5-90

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Register-Based 2-D Memory DMA ........................................ 5-90

Initializing Descriptors in Memory ........................................ 5-93

Software-Triggered Descriptor Fetch Example ........................ 5-96

Handshaked Memory DMA Example ..................................... 5-99

Unique Information for the ADSP-BF59x Processor .................. 5-101

Static Channel Prioritization ............................................... 5-101

DYNAMIC POWER MANAGEMENT

Phase Locked Loop and Clock Control .......................................... 6-1

PLL Overview ......................................................................... 6-2

PLL Clock Multiplier Ratios .................................................... 6-3

Core Clock/System Clock Ratio Control ............................. 6-5

Dynamic Power Management Controller ....................................... 6-7

Operating Modes ..................................................................... 6-7

Dynamic Power Management Controller States ........................ 6-8

Full-On Mode ................................................................... 6-8

Active Mode ...................................................................... 6-8

Sleep Mode ........................................................................ 6-9

Deep Sleep Mode ............................................................... 6-9

Hibernate State ................................................................ 6-10

Operating Mode Transitions .................................................. 6-10

Programming Operating Mode Transitions ............................. 6-13

Dynamic Supply Voltage Control ........................................... 6-15

Power Supply Management .................................................... 6-15

Changing Voltage .............................................................. 6-15

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Powering Down the Core (Hibernate State) ....................... 6-17

PLL and VR Registers ................................................................. 6-18

PLL_DIV Register ................................................................ 6-19

PLL_CTL Register ................................................................ 6-20

PLL_STAT Register .............................................................. 6-20

PLL_LOCKCNT Register ..................................................... 6-21

VR_CTL Register ................................................................. 6-21

System Control ROM Function .................................................. 6-22

Programming Model ............................................................. 6-24

Accessing the System Control ROM Function in C/C++ ........ 6-24

Accessing the System Control ROM Function in Assembly .... 6-25

Programming Examples .............................................................. 6-28

Full-on Mode to Active Mode and Back ................................. 6-30

Transition to Sleep Mode or Deep Sleep Mode ....................... 6-32

Set Wakeup Events and Enter Hibernate State ........................ 6-33

Perform a System Reset or Soft-Reset ..................................... 6-35

In Full-on Mode, Change VCO Frequency, Core Clock

Frequency, and System Clock Frequency ............................. 6-36

Changing Voltage Levels ....................................................... 6-38

GENERAL-PURPOSE PORTS

Overview ...................................................................................... 7-1

Features ........................................................................................ 7-1

Interface Overview ....................................................................... 7-2

External Interface .................................................................... 7-3

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Port F Structure .................................................................. 7-3

Port G Structure ................................................................. 7-4

Additional Considerations ................................................... 7-5

Internal Interfaces ................................................................... 7-6

Performance/Throughput ........................................................ 7-6

Description of Operation .............................................................. 7-7

Operation ............................................................................... 7-7

General-Purpose I/O Modules ................................................. 7-8

GPIO Interrupt Processing .................................................... 7-11

Programming Model ................................................................... 7-17

GPIO Schmitt Trigger Control .................................................... 7-19

PORTx Pad Control Registers ................................................ 7-19

Memory-Mapped GPIO Registers ............................................... 7-20

Port Multiplexer Control Register (PORTx_MUX) ................ 7-21

Function Enable Registers (PORTx_FER) .............................. 7-22

GPIO Direction Registers (PORTxIO_DIR) .......................... 7-22

GPIO Input Enable Registers (PORTxIO_INEN) .................. 7-23

GPIO Data Registers (PORTxIO) .......................................... 7-23

GPIO Set Registers (PORTxIO_SET) .................................... 7-24

GPIO Clear Registers (PORTxIO_CLEAR) ........................... 7-24

GPIO Toggle Registers (PORTxIO_TOGGLE) ...................... 7-25

GPIO Polarity Registers (PORTxIO_POLAR) ....................... 7-25

Interrupt Sensitivity Registers (PORTxIO_EDGE) ................. 7-26

GPIO Set on Both Edges Registers (PORTxIO_BOTH) ......... 7-26

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GPIO Mask Interrupt Registers (PORTxIO_MASKA/B) ....... 7-27

GPIO Mask Interrupt Set Registers

(PORTxIO_MASKA/B_SET) ............................................ 7-28

GPIO Mask Interrupt Clear Registers

(PORTxIO_MASKA/B_CLEAR) ....................................... 7-30

GPIO Mask Interrupt Toggle Registers

(PORTxIO_MASKA/B_TOGGLE) .................................... 7-32

Programming Examples .............................................................. 7-33

GENERAL-PURPOSE TIMERS

Specific Information for the ADSP-BF59x .................................... 8-1

Overview ...................................................................................... 8-2

External Interface .................................................................... 8-3

Internal Interface .................................................................... 8-4

Description of Operation .............................................................. 8-4

Interrupt Processing ................................................................ 8-5

Illegal States ............................................................................ 8-7

Modes of Operation ................................................................... 8-10

Pulse Width Modulation (PWM_OUT) Mode ...................... 8-10

Output Pad Disable .......................................................... 8-12

Single Pulse Generation .................................................... 8-12

Pulse Width Modulation Waveform Generation ................ 8-13

PULSE_HI Toggle Mode .................................................. 8-15

Externally Clocked PWM_OUT ....................................... 8-20

Using PWM_OUT Mode With the PPI ............................ 8-21

Stopping the Timer in PWM_OUT Mode ........................ 8-21

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Pulse Width Count and Capture (WDTH_CAP) Mode ......... 8-23

Autobaud Mode ................................................................ 8-31

External Event (EXT_CLK) Mode ......................................... 8-32

Programming Model ................................................................... 8-33

Timer Registers ........................................................................... 8-34

Timer Enable Register (TIMER_ENABLE) ............................ 8-35

Timer Disable Register (TIMER_DISABLE) .......................... 8-36

Timer Status Register (TIMER_STATUS) .............................. 8-38

Timer Configuration Register (TIMER_CONFIG) ................ 8-40

Timer Counter Register (TIMER_COUNTER) ..................... 8-41

Timer Period (TIMER_PERIOD) and Timer

Width (TIMER_WIDTH) Registers ................................... 8-42

Summary .............................................................................. 8-45

Programming Examples ............................................................... 8-47

Unique Information for the ADSP-BF59x Processor .................... 8-56

Interface Overview ................................................................ 8-57

External Interface .............................................................. 8-58

CORE TIMER

Specific Information for the ADSP-BF59x ..................................... 9-1

Overview and Features .................................................................. 9-1

Timer Overview ............................................................................ 9-2

External Interfaces ................................................................... 9-2

Internal Interfaces ................................................................... 9-3

Description of Operation .............................................................. 9-3

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Interrupt Processing ................................................................ 9-3

Core Timer Registers .................................................................... 9-4

Core Timer Control Register (TCNTL) ................................... 9-5

Core Timer Count Register (TCOUNT) ................................. 9-5

Core Timer Period Register (TPERIOD) ................................. 9-6

Core Timer Scale Register (TSCALE) ...................................... 9-7

Programming Examples ................................................................ 9-7

Unique Information for the ADSP-BF59x Processor ...................... 9-9

WAT CH DO G TIMER

Specific Information for the ADSP-BF59x .................................. 10-1

Overview and Features ................................................................ 10-1

Interface Overview ..................................................................... 10-3

External Interface .................................................................. 10-3

Internal Interface .................................................................. 10-3

Description of Operation ............................................................ 10-4

Register Definitions .................................................................... 10-5

Watchdog Count (WDOG_CNT) Register ........................... 10-5

Watchdog Status (WDOG_STAT) Register ........................... 10-6

Watchdog Control (WDOG_CTL) Register .......................... 10-7

Programming Examples .............................................................. 10-8

Unique Information for the ADSP-BF59x Processor .................. 10-10

UART PORT CONTROLLERS

Specific Information for the ADSP-BF59x .................................. 11-1

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Overview .................................................................................... 11-2

Features ...................................................................................... 11-2

Interface Overview ...................................................................... 11-3

External Interface .................................................................. 11-3

Internal Interface ................................................................... 11-4

Description of Operation ............................................................ 11-5

UART Transfer Protocol ........................................................ 11-5

UART Transmit Operation .................................................... 11-6

UART Receive Operation ...................................................... 11-7

IrDA Transmit Operation ...................................................... 11-8

IrDA Receive Operation ........................................................ 11-9

Interrupt Processing ............................................................ 11-11

Bit Rate Generation ............................................................. 11-12

Autobaud Detection ............................................................ 11-13

Programming Model ................................................................. 11-15

Non-DMA Mode ................................................................ 11-15

DMA Mode ........................................................................ 11-17

Mixing Modes ..................................................................... 11-18

UART Registers ........................................................................ 11-19

UART Line Control (UART_LCR) Register ......................... 11-21

UART Modem Control (UART_MCR) Register .................. 11-23

UART Line Status (UART_LSR) Register ............................ 11-24

UART Transmit Holding (UART_THR) Register ................ 11-25

UART Receive Buffer (UART_RBR) Register ...................... 11-26

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UART Interrupt Enable (UART_IER) Register .................... 11-26

UART Interrupt Identification (UART_IIR) Register ........... 11-28

UART Divisor Latch

(UART_DLL and UART_DLH) Registers ........................ 11-29

UART Scratch (UART_SCR) Register ................................. 11-30

UART Global Control (UART_GCTL) Register .................. 11-31

Programming Examples ............................................................ 11-32

Unique Information for the ADSP-BF59x Processor .................. 11-41

TWO WIRE INTERFACE CONTROLLER

Specific Information for the ADSP-BF59x .................................. 12-1

Overview .................................................................................... 12-2

Interface Overview ..................................................................... 12-3

External Interface .................................................................. 12-4

Serial Clock Signal (SCL) ................................................. 12-4

Serial Data Signal (SDA) .................................................. 12-4

TWI Pins ......................................................................... 12-5

Internal Interfaces ................................................................. 12-5

Description of Operation ............................................................ 12-6

TWI Transfer Protocols ......................................................... 12-6

Clock Generation and Synchronization ............................. 12-7

Bus Arbitration ................................................................. 12-8

Start and Stop Conditions ................................................. 12-8

General Call Support ........................................................ 12-9

Fast Mode ...................................................................... 12-10

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Functional Description ............................................................. 12-10

General Setup ...................................................................... 12-10

Slave Mode .......................................................................... 12-11

Master Mode Clock Setup ................................................... 12-12

Master Mode Transmit ........................................................ 12-12

Master Mode Receive ........................................................... 12-14

Repeated Start Condition ................................................ 12-15

Transmit/Receive Repeated Start Sequence ................... 12-15

Receive/Transmit Repeated Start Sequence ................... 12-16

Clock Stretching ............................................................. 12-17

Clock Stretching During FIFO Underflow ....................... 12-17

Clock Stretching During FIFO Overflow ......................... 12-19

Clock Stretching During Repeated Start Condition .......... 12-20

Programming Model ................................................................. 12-22

Register Descriptions ................................................................ 12-24

TWI CONTROL Register (TWI_CONTROL) ................... 12-24

SCL Clock Divider Register (TWI_CLKDIV) ...................... 12-25

TWI Slave Mode Control Register (TWI_SLAVE_CTL) ...... 12-26

TWI Slave Mode Address Register (TWI_SLAVE_ADDR) ... 12-28

TWI Slave Mode Status Register (TWI_SLAVE_STAT) ....... 12-28

TWI Master Mode Control Register

(TWI_MASTER_CTL) .................................................... 12-29

TWI Master Mode Address Register

(TWI_MASTER_ADDR) ................................................ 12-32

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TWI Master Mode Status Register

(TWI_MASTER_STAT) .................................................. 12-33

TWI FIFO Control Register (TWI_FIFO_CTL) ................. 12-36

TWI FIFO Status Register (TWI_FIFO_STAT) .................. 12-38

TWI FIFO Status ........................................................... 12-38

TWI Interrupt Mask Register (TWI_INT_MASK) .............. 12-39

TWI Interrupt Status Register (TWI_INT_STAT) .............. 12-40

TWI FIFO Transmit Data Single Byte

Register (TWI_XMT_DATA8) ......................................... 12-43

TWI FIFO Transmit Data Double Byte

Register (TWI_XMT_DATA16) ....................................... 12-43

TWI FIFO Receive Data Single Byte

Register (TWI_RCV_DATA8) ......................................... 12-44

TWI FIFO Receive Data Double Byte

Register (TWI_RCV_DATA16) ........................................ 12-45

Programming Examples ............................................................ 12-46

Master Mode Setup ............................................................. 12-46

Slave Mode Setup ................................................................ 12-50

Electrical Specifications ............................................................ 12-56

Unique Information for the ADSP-BF59x Processor .................. 12-56

SPI-COMPATIBLE PORT CONTROLLER

Specific Information for the ADSP-BF59x .................................. 13-1

Overview .................................................................................... 13-2

Features ...................................................................................... 13-2

Interface Overview ..................................................................... 13-3

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External Interface .................................................................. 13-4

SPI Clock Signal (SCK) ................................................... 13-4

Master-Out, Slave-In (MOSI) Signal ................................. 13-5

Master-In, Slave-Out (MISO) Signal ................................. 13-5

SPI Slave Select Input Signal (SPISS) ................................. 13-6

SPI Slave Select Enable Output Signals .............................. 13-6

Slave Select Inputs ............................................................ 13-7

Use of FLS Bits in SPI_FLG for Multiple Slave SPI

Systems .......................................................................... 13-8

Internal Interfaces ............................................................... 13-10

DMA Functionality ........................................................ 13-10

Description of Operation .......................................................... 13-11

SPI Transfer Protocols ......................................................... 13-11

SPI General Operation ........................................................ 13-14

Clock Signals ...................................................................... 13-15

Interrupt Output ................................................................. 13-16

Functional Description ............................................................. 13-16

Master Mode Operation (Non-DMA) .................................. 13-17

Transfer Initiation From Master (Transfer Modes) ................ 13-18

Slave Mode Operation (Non-DMA) ..................................... 13-19

Slave Ready for a Transfer .................................................... 13-21

Programming Model ................................................................. 13-21

Beginning and Ending an SPI Transfer ................................. 13-21

Master Mode DMA Operation ............................................. 13-23

Slave Mode DMA Operation ............................................... 13-26

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SPI Registers ............................................................................ 13-33

SPI Baud Rate (SPI_BAUD) Register .................................. 13-34

SPI Control (SPI_CTL) Register ......................................... 13-35

SPI Flag (SPI_FLG) Register ............................................... 13-37

SPI Status (SPI_STAT) Register ........................................... 13-38

Mode Fault Error (MODF) ............................................. 13-39

Transmission Error (TXE) .............................................. 13-40

Reception Error (RBSY) ................................................. 13-41

Transmit Collision Error (TXCOL) ................................. 13-41

SPI Transmit Data Buffer (SPI_TDBR) Register .................. 13-41

SPI Receive Data Buffer (SPI_RDBR) Register .................... 13-42

SPI RDBR Shadow (SPI_SHADOW) Register ..................... 13-43

Programming Examples ............................................................ 13-43

Core-Generated Transfer ..................................................... 13-43

Initialization Sequence .................................................... 13-44

Starting a Transfer .......................................................... 13-45

Post Transfer and Next Transfer ...................................... 13-46

Stopping ........................................................................ 13-46

DMA-Based Transfer ........................................................... 13-47

DMA Initialization Sequence .......................................... 13-47

SPI Initialization Sequence ............................................. 13-48

Starting a Transfer .......................................................... 13-49

Stopping a Transfer ......................................................... 13-50

Unique Information for the ADSP-BF59x Processor .................. 13-52

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SPORT CONTROLLER

Specific Information for the ADSP-BF59x ................................... 14-1

Overview .................................................................................... 14-2

Features ................................................................................. 14-2

Interface Overview ...................................................................... 14-4

SPORT Pin/Line Terminations .............................................. 14-8

Description of Operation ............................................................ 14-9

SPORT Disable ..................................................................... 14-9

Setting SPORT Modes ........................................................ 14-10

Stereo Serial Operation ........................................................ 14-10

Multichannel Operation ...................................................... 14-14

Multichannel Enable ....................................................... 14-17

Frame Syncs in Multichannel Mode ................................. 14-18

The Multichannel Frame ................................................. 14-19

Multichannel Frame Delay .............................................. 14-20

Window Size ................................................................... 14-20

Window Offset ............................................................... 14-21

Other Multichannel Fields in SPORT_MCMC2 .............. 14-21

Channel Selection Register .............................................. 14-22

Multichannel DMA Data Packing ................................... 14-23

Support for H.100 Standard Protocol ................................... 14-24

2× Clock Recovery Control ............................................. 14-24

Functional Description ............................................................. 14-25

Clock and Frame Sync Frequencies ...................................... 14-25

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Maximum Clock Rate Restrictions .................................. 14-26

Word Length ...................................................................... 14-27

Bit Order ............................................................................ 14-27

Data Type ........................................................................... 14-27

Companding ....................................................................... 14-28

Clock Signal Options .......................................................... 14-29

Frame Sync Options ............................................................ 14-30

Framed Versus Unframed ................................................ 14-30

Internal Versus External Frame Syncs .............................. 14-31

Active Low Versus Active High Frame Syncs .................... 14-32

Sampling Edge for Data and Frame Syncs ........................ 14-32

Early Versus Late Frame Syncs (Normal Versus

Alternate Timing) ........................................................ 14-34

Data Independent Transmit Frame Sync .......................... 14-36

Moving Data Between SPORTs and Memory ....................... 14-37

SPORT RX, TX, and Error Interrupts ................................. 14-37

Peripheral Bus Errors ........................................................... 14-38

Timing Examples ................................................................ 14-38

SPORT Registers ...................................................................... 14-44

Register Writes and Effective Latency .................................. 14-45

SPORT Transmit Configuration

(SPORT_TCR1 and SPORT_TCR2) Registers ................. 14-46

SPORT Receive Configuration

(SPORT_RCR1 and SPORT_RCR2) Registers ................. 14-51

Data Word Formats ............................................................. 14-55

xxii ADSP-BF59x Blackfin Processor Hardware Reference

Contents

SPORT Transmit Data (SPORT_TX) Register ..................... 14-56

SPORT Receive Data (SPORT_RX) Register ....................... 14-58

SPORT Status (SPORT_STAT) Register .............................. 14-60

SPORT Transmit and Receive Serial Clock Divider

(SPORT_TCLKDIV and SPORT_RCLKDIV) Registers ... 14-61

SPORT Transmit and Receive Frame Sync Divider

(SPORT_TFSDIV and SPORT_RFSDIV) Registers .......... 14-62

SPORT Multichannel Configuration

(SPORT_MCMC1 and SPORT_MCMC2) Registers ........ 14-63

SPORT Current Channel (SPORT_CHNL) Register ........... 14-64

SPORT Multichannel Receive Selection

(SPORT_MRCSn) Registers ............................................. 14-65

SPORT Multichannel Transmit Selection

(SPORT_MTCSn) Registers ............................................. 14-66

Programming Examples ............................................................. 14-67

SPORT Initialization Sequence ............................................ 14-68

DMA Initialization Sequence ............................................... 14-70

Interrupt Servicing .............................................................. 14-72

Starting a Transfer ............................................................... 14-73

Unique Information for the ADSP-BF59x Processor .................. 14-73

Clock Gating Functionality ................................................. 14-74

Modes of Operation ............................................................ 14-75

Gated Clock Mode 0 – SPORT Gated Clocks Without

Using TIMERs ............................................................. 14-75

Gated Clock Mode 1 – SPORT Gated Clocks Using

TIMERs ...................................................................... 14-75

ADSP-BF59x Blackfin Processor Hardware Reference xxiii

Contents

Programming Model ....................................................... 14-76

PARALLEL PERIPHERAL INTERFACE

Specific Information for the ADSP-BF59x .................................. 15-1

Overview .................................................................................... 15-2

Features ...................................................................................... 15-2

Interface Overview ..................................................................... 15-3

Description of Operation ............................................................ 15-4

Functional Description ............................................................... 15-5

ITU-R 656 Modes ................................................................ 15-5

ITU-R 656 Background .................................................... 15-5

ITU-R 656 Input Modes .................................................. 15-9

Entire Field .................................................................. 15-9

Active Video Only ...................................................... 15-10

Vertical Blanking Interval (VBI) only .......................... 15-10

ITU-R 656 Output Mode ............................................... 15-11

Frame Synchronization in ITU-R 656 Modes .................. 15-11

General-Purpose PPI Modes ................................................ 15-12

Data Input (RX) Modes .................................................. 15-14

No Frame Syncs .......................................................... 15-14

1, 2, or 3 External Frame Syncs ................................... 15-15

2 or 3 Internal Frame Syncs ........................................ 15-16

Data Output (TX) Modes ............................................... 15-16

No Frame Syncs .......................................................... 15-17

1 or 2 External Frame Syncs ........................................ 15-17

xxiv ADSP-BF59x Blackfin Processor Hardware Reference

Contents

1, 2, or 3 Internal Frame Syncs .................................... 15-18

Frame Synchronization in GP Modes ............................... 15-19

Modes With Internal Frame Syncs ............................... 15-19

Modes With External Frame Syncs .............................. 15-20

Programming Model ................................................................. 15-21

DMA Operation .................................................................. 15-22

PPI Registers ............................................................................. 15-25

PPI Control Register (PPI_CONTROL) .............................. 15-25

PPI Status Register (PPI_STATUS) ...................................... 15-29

PPI Delay Count Register (PPI_DELAY) ............................. 15-32

PPI Transfer Count Register (PPI_COUNT) ....................... 15-32

PPI Lines Per Frame Register (PPI_FRAME) ........................ 15-33

Programming Examples ............................................................. 15-34

Unique Information for the ADSP-BF59x Processor .................. 15-37

SYSTEM RESET AND BOOTING

Overview .................................................................................... 16-1

Reset and Power-up .................................................................... 16-3

Hardware Reset ..................................................................... 16-4

Software Resets ...................................................................... 16-5

Reset Vector .......................................................................... 16-6

Servicing Reset Interrupts ...................................................... 16-6

Basic Booting Process .................................................................. 16-8

Block Headers ..................................................................... 16-10

Block Code ..................................................................... 16-12

ADSP-BF59x Blackfin Processor Hardware Reference xxv

Contents

DMA Code Field ........................................................ 16-12

Block Flags Field ......................................................... 16-14

Header Checksum Field .............................................. 16-15

Header Sign Field ....................................................... 16-16

Target Address ................................................................ 16-16

Byte Count ..................................................................... 16-17

Argument ....................................................................... 16-17

Boot Host Wait (HWAIT) Feedback Strobe ......................... 16-18

Using HWAIT as Reset Indicator .................................... 16-19

Boot Termination ............................................................... 16-19

Single Block Boot Streams ................................................... 16-20

Advanced Boot Techniques ....................................................... 16-21

Initialization Code .............................................................. 16-21

Quick Boot ......................................................................... 16-25

Indirect Booting .................................................................. 16-26

Callback Routines ............................................................... 16-27

Error Handler ..................................................................... 16-30

CRC Checksum Calculation ................................................ 16-30

Load Functions ................................................................... 16-30

Calling the Boot Kernel at Runtime .................................... 16-32

Debugging the Boot Process ................................................ 16-32

Boot Management .................................................................... 16-35

Booting a Different Application .......................................... 16-35

Multi-DXE Boot Streams ................................................ 16-36

xxvi ADSP-BF59x Blackfin Processor Hardware Reference

Contents

Determining Boot Stream Start Addresses ........................ 16-37

Initialization Hook Routine ............................................ 16-38

Specific Boot Modes .................................................................. 16-38

No Boot Mode .................................................................... 16-39

SPI Master Boot Modes ....................................................... 16-40

SPI Device Detection Routine ......................................... 16-42

SPI Slave Boot Mode ........................................................... 16-44

PPI Boot Mode ................................................................... 16-47

UART Slave Mode Boot ...................................................... 16-49

L1 ROM Boot Mode ........................................................... 16-51

Reset and Booting Registers ....................................................... 16-51

Software Reset (SWRST) Register ........................................ 16-52

System Reset Configuration (SYSCR) Register ..................... 16-54

Boot Code Revision Control (BK_REVISION) .................... 16-55

Boot Code Date Code (BK_DATECODE) .......................... 16-56

Zero Word (BK_ZEROS) .................................................... 16-57

Ones Word (BK_ONES) ..................................................... 16-58

Data Structures ......................................................................... 16-58

ADI_BOOT_HEADER ...................................................... 16-59

ADI_BOOT_BUFFER ........................................................ 16-59

ADI_BOOT_DATA ............................................................ 16-59

dFlags Word ................................................................... 16-63

Callable ROM Functions for Booting ........................................ 16-64

BFROM_FINALINIT ......................................................... 16-64

ADSP-BF59x Blackfin Processor Hardware Reference xxvii

Contents

BFROM_PDMA ................................................................ 16-65

BFROM_MDMA .............................................................. 16-65

BFROM_SPIBOOT ........................................................... 16-66

BFROM_BOOTKERNEL .................................................. 16-68

BFROM_CRC32 ................................................................ 16-68

BFROM_CRC32POLY ....................................................... 16-69

BFROM_CRC32CALLBACK ............................................. 16-70

BFROM_CRC32INITCODE ............................................. 16-70

Programming Examples ............................................................ 16-71

System Reset ....................................................................... 16-71

Exiting Reset to User Mode ................................................. 16-72

Exiting Reset to Supervisor Mode ........................................ 16-72

Initcode (Power Management Control) ................................ 16-73

XOR Checksum .................................................................. 16-75

SYSTEM DESIGN

Pin Descriptions ......................................................................... 17-1

Managing Clocks ........................................................................ 17-1

Managing Core and System Clocks ........................................ 17-2

Configuring and Servicing Interrupts .......................................... 17-2

Data Delays, Latencies and Throughput ...................................... 17-2

Bus Priorities .............................................................................. 17-3

High-Frequency Design Considerations ...................................... 17-3

Signal Integrity ..................................................................... 17-3

Decoupling Capacitors and Ground Planes ............................ 17-4

xxviii ADSP-BF59x Blackfin Processor Hardware Reference

Contents

Test Point Access ................................................................... 17-6

Oscilloscope Probes ............................................................... 17-6

Recommended Reading ......................................................... 17-7

Resetting the Processor ................................................................ 17-8

Recommendations for Unused Pins ............................................. 17-8

Programmable Outputs ............................................................... 17-9

Voltage Regulation Interface ........................................................ 17-9

SYSTEM MMR ASSIGNMENTS

Processor-Specific Memory Registers ............................................ A-2

Core Timer Registers .................................................................... A-3

System Reset and Interrupt Control

Registers ................................................................................... A-3

DMA/Memory DMA Control Registers ....................................... A-4

Ports Registers .............................................................................. A-7

Timer Registers ............................................................................ A-9

Watchdog Timer Registers .......................................................... A-11

Dynamic Power Management Registers ....................................... A-11

PPI Registers .............................................................................. A-12

SPI Controller Registers ............................................................. A-12

SPORT Controller Registers ....................................................... A-14

SPORT Clock Gating Register ................................................... A-17

UART Controller Registers ........................................................ A-18

TWI Registers ............................................................................ A-19

ADSP-BF59x Blackfin Processor Hardware Reference xxix

Contents

TEST FEATURES

JTAG Standard ............................................................................. B-1

Boundary-Scan Architecture ......................................................... B-2

Instruction Register ................................................................. B-4

Public Instructions .................................................................. B-5

EXTEST – Binary Code 00000 ........................................... B-6

SAMPLE/PRELOAD – Binary Code 10000 ....................... B-6

BYPASS – Binary Code 11111 ............................................ B-6

Boundary-Scan Register .......................................................... B-7

INDEX

xxx ADSP-BF59x Blackfin Processor Hardware Reference

PREFACE

Thank you for purchasing and developing systems using an enhanced
Blackfin® processor from Analog Devices.

Purpose of This Manual

The ADSP-BF59x Blackfin Processor Hardware Reference provides architec-
tural information about the ADSP-BF59x processors. This hardware
reference provides the main architectural information about these proces­sors. The architectural descriptions cover functional blocks, buses, and
ports, including all features and processes that they support. For program­ming information, see the Blackfin Processor Programming Reference. For
timing, electrical, and package specifications, see the ADSP-BF592 Black-
fin Processor Data Sheet.

Intended Audience

The primary audience for this manual is a programmer who is familiar
with Analog Devices processors. The manual assumes the audience has a
working knowledge of the appropriate processor architecture and instruc­tion set. Programmers who are unfamiliar with Analog Devices processors
can use this manual, but should supplement it with other texts, such as
hardware reference and programming reference manuals, that describe
their target architecture.

ADSP-BF59x Blackfin Processor Hardware Reference xxxi

Manual Contents

Manual Contents

This manual consists of one volume:

• Chapter 1, “Introduction”
Provides a high level overview of the processor, including peripher­als, power management, and development tools.

• Chapter 2, “Memory”
Describes processor-specific memory topics, including L1memories
and processor-specific memory MMRs.

• Chapter 3, “Chip Bus Hierarchy”
Describes on-chip buses, including how data moves through the
system.

• Chapter 4, “System Interrupts”
Describes the system peripheral interrupts, including setup and
clearing of interrupt requests.

• Chapter 5, “Direct Memory Access”
Describes the peripheral DMA and Memory DMA controllers.
Includes performance, software management of DMA, and DMA
errors.

• Chapter 6, “Dynamic Power Management”
Describes the clocking, including the PLL, and the dynamic power
management controller.

• Chapter 7, “General-Purpose Ports”
Describes the general-purpose I/O ports, including the structure of
each port, multiplexing, configuring the pins, and generating
interrupts.

• Chapter 8, “General-Purpose Timers”
Describes the eight general-purpose timers.

xxxii ADSP-BF59x Blackfin Processor Hardware Reference

Preface

• Chapter 9, “Core Timer”
Describes the core timer.

• Chapter 10, “Watchdog Timer”
Describes the watchdog timer.

• Chapter 11, “UART Port Controllers”
Describes the Universal Asynchronous Receiver/Transmitter port
that converts data between serial and parallel formats. The UART
supports the half-duplex IrDA® SIR protocol as a mode-enabled
feature.

• Chapter 12, “Two Wire Interface Controller”
Describes the Two Wire Interface (TWI) controller, which allows a
device to interface to an Inter IC bus as specified by the Philips I
Bus Specification version 2.1 dated January 2000.

• Chapter 13, “SPI-Compatible Port Controller”
Describes the Serial Peripheral Interface (SPI) port that provides an
I/O interface to a variety of SPI compatible peripheral devices.

2

C

• Chapter 14, “SPORT Controller”
Describes the independent, synchronous Serial Port Controller
which provides an I/O interface to a variety of serial peripheral
devices.

• Chapter 15, “Parallel Peripheral Interface”
Describes the Parallel Peripheral Interface (PPI) of the processor.
The PPI is a half-duplex, bidirectional port accommodating up to
16 bits of data and is used for digital video and data converter
applications.

• Chapter 16, “System Reset and Booting”
Describes the booting methods, booting process and specific boot
modes for the processor.

ADSP-BF59x Blackfin Processor Hardware Reference xxxiii

What’s New in This Manual

• Chapter 17, “System Design”
Describes how to use the processor as part of an overall system. It
includes information about bus timing and latency numbers, sema­phores, and a discussion of the treatment of unused pins.

• Appendix A, “System MMR Assignments”
Lists the memory-mapped registers included in this manual, their
addresses, and cross-references to text.

• Appendix B, “Test Features”
Describes test features for the processor, discusses the JTAG stan­dard, boundary-scan architecture, instruction and boundary
registers, and public instructions.



This hardware reference is a companion document to the Blackfin
Processor Programming Reference.

What’s New in This Manual

This revision (1.0) is the second release of the ADSP-BF59x Blackfin Pro­cessor Hardware Reference. Minor typographical errors have been corrected

in this revision.

Technical or Customer Support

You can reach Analog Devices, Inc. Customer Support in the following
ways:

• Visit the Embedded Processing and DSP products Web site at

http://www.analog.com/processors/technical_support

• E-mail tools questions to

[e-mail]

xxxiv ADSP-BF59x Blackfin Processor Hardware Reference

• E-mail processor questions to

[e-mail] (World wide support)
[e-mail] (China support)

• Phone questions to 1-800-ANALOGD

• Contact your Analog Devices, Inc. local sales office or authorized
distributor

• Send questions by mail to:

Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA

Registration for MyAnalog.com

Preface

MyAnalog.com is a free feature of the Analog Devices Web site that allows
customization of a Web page to display only the latest information about
products you are interested in. Click Register to use this site. Registration
takes about five minutes and serves as a means to select the information
you want to receive.

If you are already a registered user, just log on. Your user name is your
e-mail address.

EngineerZone

EngineerZone is a technical support forum from Analog Devices. It allows
you direct access to ADI technical support engineers. You can search
FAQs and technical information to get quick answers to your embedded
processing and DSP design questions.

ADSP-BF59x Blackfin Processor Hardware Reference xxxv

Supported Processors

Use EngineerZone to connect with other DSP developers who face similar
design challenges. You can also use this open forum to share knowledge
and collaborate with the ADI support team and your peers. Visit

http://ez.analog.com to sign up.

Social Networking Web Sites

You can now follow Analog Devices SHARC development on Twitter and
LinkedIn. To access:

• Twitter:

• LinkedIn: Network with the LinkedIn group, Analog Devices
SHARC: http://www.linkedin.com

http://twitter.com/ADISHARC

Supported Processors

The following is the list of Analog Devices, Inc. processors supported in
VisualDSP++®.

Blackfin (ADSP-BFxxx) Processors

The name Blackfin refers to a family of 16-bit, embedded processors.
VisualDSP++ currently supports the following Blackfin families
ADSP-BF51x, ADSP-BF52x, ADSP-BF53x, ADSP-BF54x, ADSP-BF59x,
and ADSP-BF561 processors.

TigerSHARC® (ADSP-TSxxx) Processors

The name TigerSHARC refers to a family of floating-point and fixed-point
[8-bit, 16-bit, and 32-bit] processors. VisualDSP++ currently supports the
following TigerSHARC families: ADSP-TS101 and ADSP-TS20x.

xxxvi ADSP-BF59x Blackfin Processor Hardware Reference

Preface

SHARC® (ADSP-21xxx) Processors

The name SHARC refers to a family of high-performance, 32-bit,
floating-point processors that can be used in speech, sound, graphics, and
imaging applications. VisualDSP++ currently supports the following
SHARC families: ADSP-2106x, ADSP-2116x, ADSP-2126x,
ADSP-2136x, and ADSP-214xx.

Product Information

Product information can be obtained from the Analog Devices Web site,
VisualDSP++ online Help system, and a technical library CD.

Analog Devices Web Site

The Analog Devices Web site, www.analog.com, provides information
about a broad range of products—analog integrated circuits, amplifiers,
converters, and digital signal processors.

To access a complete technical library for each processor family, go to

http://www.analog.com/processors/technical_library. The manuals

selection opens a list of current manuals related to the product as well as a
link to the previous revisions of the manuals. When locating your manual
title, note a possible errata check mark next to the title that leads to the
current correction report against the manual.

Also note,

MyAnalog.com is a free feature of the Analog Devices Web site

that allows customization of a Web page to display only the latest infor­mation on products you are interested in. You can also choose to receive
weekly e-mail notifications containing updates to the Web pages that meet
your interests, including documentation errata against all manuals.

MyAnalog.com provides access to books, application notes, data sheets,

code examples, and more.

ADSP-BF59x Blackfin Processor Hardware Reference xxxvii

Product Information

Visit

www.myanalog.com to sign up. If you are already a registered user, just

log on. Your user name is your e-mail address.

VisualDSP++ Online Documentation

Online documentation comprises the VisualDSP++ Help system, software
tools manuals, hardware tools manuals, processor manuals, Dinkum
Abridged C++ library, and FLEXnet License Tools software
documentation. You can search easily across the entire VisualDSP++ doc­umentation set for any topic of interest.

For easy printing, supplementary Portable Documentation Format (.pdf)
files for all manuals are provided on the VisualDSP++ installation CD.

Each documentation file type is described as follows.

File Description

.chm Help system files and manuals in Microsoft help format

.htm or
.html

.pdf VisualDSP++ and processor manuals in PDF format. Viewing and printing the

Dinkum Abridged C++ library and FLEXnet License Tools software documenta­tion. Viewing and printing the
Explorer 6.0 (or higher).

.pdf files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher).

.html files requires a browser, such as Internet

Technical Library CD

The technical library CD contains seminar materials, product highlights, a
selection guide, and documentation files of processor manuals,
VisualDSP++ software manuals, and hardware tools manuals for the fol­lowing processor families: Blackfin®, SHARC, TigerSHARC®,
ADSP-218x, and ADSP-219x.

To order the technical library CD, go to

sors/manuals

, navigate to the manuals page for your processor, click the

request CD check mark, and fill out the order form.

xxxviii ADSP-BF59x Blackfin Processor Hardware Reference

http://www.analog.com/proces-

Preface



Data sheets, which can be downloaded from the Analog Devices Web site,
change rapidly, and therefore are not included on the technical library
CD. Technical manuals change periodically. Check the Web site for the
latest manual revisions and associated documentation errata.

Notation Conventions

Text conventions used in this manual are identified and described as fol­lows. Additional conventions, which apply only to specific chapters, may
appear throughout this document.

Example Description

Close command
(File menu)

{this | that} Alternative required items in syntax descriptions appear within curly

[this | that] Optional items in syntax descriptions appear within brackets and sepa-

[this,…] Optional item lists in syntax descriptions appear within brackets delim-

SECTION Commands, directives, keywords, and feature names are in text with let-

.

filename Non-keyword placeholders appear in text with italic style format.

Titles in reference sections indicate the location of an item within the
VisualDSP++ environment’s menu system (for example, the Close com­mand appears on the File menu).

brackets and separated by vertical bars; read the example as this or that.
One or the other is required.

rated by vertical bars; read the example as an optional this or that.

ited by commas and terminated with an ellipse; read the example as an
optional comma-separated list of

ter gothic

Note: For correct operation, ...
A Note provides supplementary information on a related topic. In the
online version of this book, the word Note appears instead of this symbol.

font.

this.

ADSP-BF59x Blackfin Processor Hardware Reference xxxix

Notation Conventions





Example Description

Caution: Incorrect device operation may result if ...
Caution: Device damage may result if ...

A Caution identifies conditions or inappropriate usage of the product that
could lead to undesirable results or product damage. In the online version
of this book, the word Caution appears instead of this symbol.

War ni ng : Injury to device users may result if ...
A Warning identifies conditions or inappropriate usage of the product
that could lead to conditions that are potentially hazardous for the devices
users. In the online version of this book, the word War ni ng appears
instead of this symbol.

xl ADSP-BF59x Blackfin Processor Hardware Reference

1 INTRODUCTION

The ADSP-BF59x processors are members of the Blackfin processor fam­ily that offer significant high performance and low power features while
retaining their ease-of-use benefits.



This hardware reference is a companion document to the Blackfin
Processor Programming Reference.

General Description of Processor

The ADSP-BF59x processor is a member of the Blackfin® family of prod­ucts, incorporating the Analog Devices/Intel Micro Signal Architecture
(MSA). Blackfin processors combine a dual-MAC state-of-the-art signal
processing engine, the advantages of a clean, orthogonal RISC-like micro­processor instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set architecture.

The ADSP-BF59x processor is completely code compatible with other
Blackfin processors. ADSP-BF59x processors offer performance up to
400 MHz and reduced static power consumption. The processor features
are shown in Table 1-1.

By integrating a rich set of industry-leading system peripherals and mem­ory, Blackfin processors are the platform of choice for next-generation
applications that require RISC-like programmability, multimedia support,
and leading-edge signal processing in one integrated package.

ADSP-BF59x Blackfin Processor Hardware Reference 1-1

General Description of Processor

Table 1-1. Processor Features

Feature ADSP-BF592

Timer/Counters with PWM 3

SPORTs 2

SPIs 2

UART 1

Parallel Peripheral Interface 1

TWI 1

GPIOs 32

L1 Instruction SRAM 32K

L1 Instruction ROM 64K

L1 Data SRAM 32K

L1 Scratchpad 4K

Memory (bytes)

L3 Boot ROM 4K

Maximum Instruction Rate

1

400 MHz

Maximum System Clock Speed 100 MHz

Package Options 64-Lead

LFCSP

1 Maximum instruction rate is not available with every

possible SCLK selection.

Portable Low-Power Architecture

Blackfin processors provide world-class power management and perfor­mance. They are produced with a low-power and low-voltage design
methodology and feature on-chip dynamic power management, which
provides the ability to vary both the voltage and frequency of operation to
significantly lower overall power consumption. This capability can result
in a substantial reduction in power consumption, compared with just

1-2 ADSP-BF59x Blackfin Processor Hardware Reference

Introduction

varying the frequency of operation. This allows longer battery life for
portable appliances.

Peripherals

The processor system peripherals include:

• Two memory-to-memory DMAs

• Event handler with 28 interrupt inputs

• 9 peripheral DMAs

• 32 General-Purpose I/Os (GPIOs)

• Three 32-bit timer/counters with PWM support

• 32-bit core timer

• On-chip PLL capable of 5× to 64× frequency multiplication

• Debug/JTAG interface

• Parallel Peripheral Interface (PPI), supporting ITU-R 656 video
data formats

• Two Serial Peripheral Interface (SPI)-compatible ports

• Two-Wire Interface (TWI) controller

• Two dual-channel, full-duplex synchronous Serial Ports
(SPORTs), supporting eight stereo I

• One UART with IrDA® support

These peripherals are connected to the core via several high bandwidth
buses, as shown in Figure 1-1.

ADSP-BF59x Blackfin Processor Hardware Reference 1-3

2

S channels

Memory Architecture

SPORT0

VOLTAGE REGULATOR INTERFACE

PORT F

JTAG TEST AND EMULATION

PERIPHERAL

ACCESS BUS

WATCHDOG TIMER

PPI

SPI0

SPI1

BOOT

ROM

DMA

ACCESS

BUS

INTERRUPT

CONTROLLER

DMA

CONTROLLER

L1 DATA

SRAM

L1 INSTRUCTION

SRAM

DCB

B

UART

DEB

TIMER2–0

L1 INSTRUCTION

ROM

GPIO

SPORT1

TWI

PORT G

Most of the peripherals are supported by a flexible DMA structure. There
are also two separate memory DMA channels dedicated to data transfers
between the processor’s memory spaces. Multiple on-chip buses provide
enough bandwidth to keep the processor core running even when there is
also activity on all of the on-chip and external peripherals.

Figure 1-1. ADSP-BF59x Processor Block Diagram

Memory Architecture

The Blackfin processor architecture structures memory as a single, unified
4G byte address space using 32-bit addresses. All resources, including
internal memory, external memory, and I/O control registers, occupy sep­arate sections of this common address space. The memory portions of this
address space are arranged in a hierarchical structure to provide a good
cost/performance balance of some very fast, low latency on-chip memory,

1-4 ADSP-BF59x Blackfin Processor Hardware Reference

Introduction

and larger, lower cost and lower performance off-chip memory systems.

Table 1-2 shows the memory for the ADSP-BF59x processors.

Table 1-2. Memory Configurations

Type of Memory ADSP-BF59x

Instruction SRAM 32K byte

Instruction ROM 64K byte

Data SRAM 32K byte

Data scratchpad SRAM 4K byte

L3 Boot ROM 4K byte

Total 136K byte

Internal Memory

The processor has four blocks of on-chip memory that provide high band­width access to the core:

• L1 instruction SRAM memory. This memory is accessed at full
processor speed.

• L1 data SRAM memory. This memory block is accessed at full pro­cessor speed.

• L1 scratchpad RAM, which runs at the same speed as the L1 mem­ories but is only accessible as data SRAM.

• L1 instruction ROM memory, accessed at full processor speed.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All resources are
mapped through the flat 32-bit address space. Control registers for
on-chip I/O devices are mapped into memory-mapped registers (MMRs)
at addresses near the top of the 4G byte address space. These are separated

ADSP-BF59x Blackfin Processor Hardware Reference 1-5

DMA Support

into two smaller blocks: one contains the control MMRs for all core func­tions and the other contains the registers needed for setup and control of
the on-chip peripherals outside of the core. The MMRs are accessible only
in supervisor mode. They appear as reserved space to on-chip peripherals.

DMA Support

The processor has a DMA controller which supports automated data
transfers with minimal overhead for the core. DMA transfers can occur
between the internal memories and any of its DMA-capable peripherals.
DMA-capable peripherals include the SPORTs, SPI ports, UART, and
PPI. Each individual DMA-capable peripheral has at least one dedicated
DMA channel.

The DMA controller supports both one-dimensional (1D) and
two-dimensional (2-D) DMA transfers. DMA transfer initialization can
be implemented from registers or from sets of parameters called descriptor
blocks.

The 2-D DMA capability supports arbitrary row and column sizes up to
64K elements by 64K elements, and arbitrary row and column step sizes
up to +/- 32K elements. Furthermore, the column step size can be less
than the row step size, allowing implementation of interleaved data­streams. This feature is especially useful in video applications where data
can be de-interleaved on the fly.

Examples of DMA types supported include:

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each full or
fractionally full buffer

1-6 ADSP-BF59x Blackfin Processor Hardware Reference

Introduction

• 1-D or 2-D DMA using a linked list of descriptors

• 2-D DMA using an array of descriptors specifying only the base
DMA address within a common page

In addition to the dedicated peripheral DMA channels, there are two sep­arate pairs of memory DMA channels provided for transfers between the
various memories of the system. Memory DMA transfers can be controlled
by a very flexible descriptor-based methodology or by a standard regis­ter-based autobuffer mechanism.

General-Purpose I/O (GPIO)

The ADSP-BF59x processors have 32 bi-directional, general-purpose I/O
(GPIO) pins allocated across two separate GPIO modules—PORTFIO,
and PORTGIO, associated with port F and port G, respectively. Port J
does not provide GPIO functionality. Each GPIO-capable pin shares
functionality with other ADSP-BF59x processor peripherals via a multi­plexing scheme; however, the GPIO functionality is the default state of
the device upon powerup. Neither GPIO output or input drivers are
active by default. Each general-purpose port pin can be individually con­trolled by manipulation of the port control, status, and interrupt registers:

• GPIO direction control register – Specifies the direction of each
individual GPIO pin as input or output.

• GPIO control and status registers – The ADSP-BF59x processors
employ a “write one to modify” mechanism that allows any combi­nation of individual GPIO pins to be modified in a single
instruction, without affecting the level of any other GPIO pins.
Four control registers are provided. One register is written in order
to set pin values, one register is written in order to clear pin values,
one register is written in order to toggle pin values, and one register
is written in order to specify a pin value. Reading the GPIO status
register allows software to interrogate the sense of the pins.

ADSP-BF59x Blackfin Processor Hardware Reference 1-7

Two-Wire Interface

• GPIO interrupt mask registers – The two GPIO interrupt mask
registers allow each individual GPIO pin to function as an inter­rupt to the processor. Similar to the two GPIO control registers
that are used to set and clear individual pin values, one GPIO
interrupt mask register sets bits to enable interrupt function, and
the other GPIO interrupt mask register clears bits to disable inter­rupt function. GPIO pins defined as inputs can be configured to
generate hardware interrupts, while output pins can be triggered by
software interrupts.

• GPIO interrupt sensitivity registers – The two GPIO interrupt sen­sitivity registers specify whether individual pins are level- or
edge-sensitive and specify—if edge-sensitive—whether just the ris­ing edge or both the rising and falling edges of the signal are
significant. One register selects the type of sensitivity, and one reg­ister selects which edges are significant for edge-sensitivity.

Two-Wire Interface

The Two-Wire Interface (TWI) is compatible with the widely used I2C
bus standard. It was designed with a high level of functionality and is
compatible with multi-master, multi-slave bus configurations. To preserve
processor bandwidth, the TWI controller can be set up and a transfer ini­tiated with interrupts only to service FIFO buffer data reads and writes.
Protocol related interrupts are optional.

The TWI externally moves 8-bit data while maintaining compliance with

2

C bus protocol. The Philips I2C Bus Specification version 2.1 covers

the I
many variants of I2C. The TWI controller includes these features:

• Simultaneous master and slave operation on multiple device
systems

• Support for multi-master data arbitration

1-8 ADSP-BF59x Blackfin Processor Hardware Reference

Introduction

• 7-bit addressing

• 100K bits/second and 400K bit/second data rates

• General call address support

• Master clock synchronization and support for clock low extension

• Separate multiple-byte receive and transmit FIFOs

• Low interrupt rate

• Individual override control of data and clock lines in the event of
bus lock-up

• Input filter for spike suppression

• Serial camera control bus support as specified in the OmniVision

Serial Camera Control Bus (SCCB) Functional Specification
version 2.1

Parallel Peripheral Interface

The processor provides a Parallel Peripheral Interface (PPI) that can con­nect directly to parallel A/D and D/A converters, ITU-R 601/656 video
encoders and decoders, and other general-purpose peripherals. The PPI
consists of a dedicated input clock pin and three multiplexed frame sync
pins. The input clock supports parallel data rates up to half the system
clock rate.

In ITU-R 656 modes, the PPI receives and parses a data stream of 8-bit or
10-bit data elements. On-chip decode of embedded preamble control and
synchronization information is supported.

ADSP-BF59x Blackfin Processor Hardware Reference 1-9

Parallel Peripheral Interface

Three distinct ITU-R 656 modes are supported:

• Active video only - The PPI does not read in any data between the
End of Active Video (EAV) and Start of Active Video (SAV) pre­amble symbols, or any data present during the vertical blanking
intervals. In this mode, the control byte sequences are not stored to
memory; they are filtered by the PPI.

• Vertical blanking only - The PPI only transfers Vertical Blanking
Interval (VBI) data, as well as horizontal blanking information and
control byte sequences on VBI lines.

• Entire field - The entire incoming bitstream is read in through the
PPI. This includes active video, control preamble sequences, and
ancillary data that may be embedded in horizontal and vertical
blanking intervals.

Though not explicitly supported, ITU-R 656 output functionality can be
achieved by setting up the entire frame structure (including active video,
blanking, and control information) in memory and streaming the data out
the PPI in a frame sync-less mode. The processor’s 2-D DMA features
facilitate this transfer by allowing the static frame buffer (blanking and
control codes) to be placed in memory once, and simply updating the
active video information on a per-frame basis.

The general-purpose modes of the PPI are intended to suit a wide variety
of data capture and transmission applications. The modes are divided into
four main categories, each allowing up to 16 bits of data transfer per

PPI_CLK cycle:

• Data receive with internally generated frame syncs

• Data receive with externally generated frame syncs

• Data transmit with internally generated frame syncs

• Data transmit with externally generated frame syncs

1-10 ADSP-BF59x Blackfin Processor Hardware Reference

Introduction

These modes support ADC/DAC connections, as well as video communi­cation with hardware signalling. Many of the modes support more than
one level of frame synchronization. If desired, a programmable delay can
be inserted between assertion of a frame sync and reception/transmission
of data.

SPORT Controllers

The processor incorporates two dual-channel synchronous serial ports
(SPORT0 and SPORT1) for serial and multiprocessor communications.
The SPORTs support these features:

• Bidirectional, I2S capable operation

Each SPORT has two sets of independent transmit and receive
pins, which enable eight channels of I2S stereo audio.

• Buffered (eight-deep) transmit and receive ports

Each port has a data register for transferring data words to and
from other processor components and shift registers for shifting
data in and out of the data registers.

• Clocking

Each transmit and receive port can either use an external serial
clock or can generate its own in a wide range of frequencies.

• Word length

Each SPORT supports serial data words from 3 to 32 bits in
length, transferred in most significant bit first or least significant
bit first format.

ADSP-BF59x Blackfin Processor Hardware Reference 1-11

SPORT Controllers

• Framing

Each transmit and receive port can run with or without frame sync
signals for each data word. Frame sync signals can be generated
internally or externally, active high or low, and with either of two
pulse widths and early or late frame sync.

• Companding in hardware

Each SPORT can perform A-law or µ-law companding according
to ITU recommendation G.711. Companding can be selected on
the transmit and/or receive channel of the SPORT without addi­tional latencies.

• DMA operations with single cycle overhead

Each SPORT can automatically receive and transmit multiple buf­fers of memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.

• Interrupts

Each transmit and receive port generates an interrupt upon com­pleting the transfer of a data word or after transferring an entire
data buffer or buffers through DMA.

• Multichannel capability

Each SPORT supports 128 channels out of a 1024-channel win­dow and is compatible with the H.100, H.110, MVIP-90, and
HMVIP standards.

1-12 ADSP-BF59x Blackfin Processor Hardware Reference

Introduction

Serial Peripheral Interface (SPI) Ports

The processor has two SPI-compatible ports that enable the processor to
communicate with multiple SPI-compatible devices.

Each SPI interface uses three pins for transferring data: two data pins and
a clock pin. An SPI chip select input pin lets other SPI devices select the
processor, and several SPI chip select output pins let the processor select
other SPI devices. The SPI select pins are reconfigured general-purpose
I/O pins. Using these pins, the SPI port provides a full-duplex, synchro­nous serial interface, which supports both master and slave modes and
multimaster environments.

Each SPI port’s baud rate and clock phase/polarities are programmable,
and it has an integrated DMA controller, configurable to support either
transmit or receive datastreams. The SPI’s DMA controller can only ser­vice unidirectional accesses at any given time.

During transfers, the SPI port simultaneously transmits and receives by
serially shifting data in and out of its two serial data lines. The serial clock
line synchronizes the shifting and sampling of data on the two serial data
lines.

Timers

There are three general-purpose programmable timer units in the proces­sor. Eight timers have an external pin that can be configured either as a
Pulse Width Modulator (PWM) or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths of external events.
These timer units can be synchronized to an external clock input con­nected to the TMRCLK/PPI_CLK pin or to the internal SCLK.

The timer units can be used in conjunction with the UARTs to measure
the width of the pulses in the datastream to provide an autobaud detect
function for a serial channel.

ADSP-BF59x Blackfin Processor Hardware Reference 1-13

UART Port

The timers can generate interrupts to the processor core to provide peri­odic events for synchronization, either to the processor clock or to a count
of external signals.

In addition to the eight general-purpose programmable timers, a 9th timer
is also provided. This extra timer is clocked by the internal processor clock
and is typically used as a system tick clock for generation of operating sys­tem periodic interrupts.

UART Port

The processor provides one Universal Asynchronous Receiver/Transmitter
(UART) port, which is fully compatible with PC-standard UARTs. The
UART port provides a simplified UART interface to other peripherals or
hosts, providing half-duplex, DMA-supported, asynchronous transfers of
serial data. The UART port includes support for 5 to 8 data bits; 1 or 2
stop bits; and none, even, or odd parity. The UART port supports two
modes of operation:

• Programmed I/O

The processor sends or receives data by writing or reading
I/O-mapped UART registers. The data is double buffered on both
transmit and receive.

• Direct Memory Access (DMA)

The DMA controller transfers both transmit and receive data. This
reduces the number and frequency of interrupts required to trans­fer data to and from memory. The UART has two dedicated DMA
channels, one for transmit and one for receive. These DMA chan­nels have lower priority than most DMA channels because of their
relatively low service rates.

1-14 ADSP-BF59x Blackfin Processor Hardware Reference

Introduction

The UART’s baud rate, serial data format, error code generation and sta­tus, and interrupts can be programmed to support:

• Wide range of bit rates

• Data formats from 7 to 12 bits per frame

• Generation of maskable interrupts to the processor by both trans­mit and receive operations

In conjunction with the general-purpose timer functions, autobaud detec­tion is supported.

The capabilities of the UART port is further extended with support for
the Infrared Data Association (IrDA

Specification (SIR) protocol.

®

) Serial Infrared Physical Layer Link

Watchdog Timer

The processor includes a 32-bit timer that can be used to implement a
software watchdog function. A software watchdog can improve system
availability by forcing the processor to a known state through generation
of a hardware reset, nonmaskable interrupt (NMI), or general-purpose
interrupt, if the timer expires before being reset by software. The pro­grammer initializes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must reload the
counter before it counts to zero from the programmed value. This protects
the system from remaining in an unknown state where software that
would normally reset the timer has stopped running due to an external
noise condition or software error.

If configured to generate a hardware reset, the watchdog timer resets both
the CPU and the peripherals. After a reset, software can determine if the
watchdog was the source of the hardware reset by interrogating a status bit
in the watchdog control register.

ADSP-BF59x Blackfin Processor Hardware Reference 1-15

Clock Signals

The timer is clocked by the system clock (
of f

SCLK

.

SCLK), at a maximum frequency

Clock Signals

The processor can be clocked by an external crystal, a sine wave input, or a
buffered, shaped clock derived from an external clock oscillator.

This external clock connects to the processor’s
cannot be halted, changed, or operated below the specified frequency dur­ing normal operation. This clock signal should be a TTL-compatible
signal.

The core clock (CCLK) and system peripheral clock (SCLK) are derived from
the input clock (CLKIN) signal. An on-chip Phase Locked Loop (PLL) is
capable of multiplying the CLKIN signal by a user-programmable (5× to
64×) multiplication factor (bounded by specified minimum and maxi­mum VCO frequencies). The default multiplier is 6×, but it can be modified
by a software instruction sequence. On-the-fly frequency changes can be
made by simply writing to the PLL_DIV register.

CLKIN pin. The CLKIN input

All on-chip peripherals are clocked by the system clock (SCLK). The system
clock frequency is programmable by means of the SSEL[3:0] bits of the

PLL_DIV register.

Dynamic Power Management

The processor provides four operating modes, each with a different perfor­mance/power profile. In addition, dynamic power management provides
the control functions to dynamically alter the processor core supply volt­age to further reduce power dissipation. Control of clocking to each of the
peripherals also reduces power consumption.

1-16 ADSP-BF59x Blackfin Processor Hardware Reference

Introduction

Full-On Mode (Maximum Performance)

In the full-on mode, the PLL is enabled, not bypassed, providing the max­imum operational frequency. This is the normal execution state in which
maximum performance can be achieved. The processor core and all
enabled peripherals run at full speed.

Active Mode (Moderate Power Savings)

In the active mode, the PLL is enabled, but bypassed. Because the PLL is
bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run at
the input clock (CLKIN) frequency. In this mode, the CLKIN to VCO multi­plier ratio can be changed, although the changes are not realized until the
full on mode is entered. DMA access is available to appropriately config­ured L1 memories.

In the active mode, it is possible to disable the PLL through the PLL con­trol register (PLL_CTL). If disabled, the PLL must be re-enabled before
transitioning to the full on or sleep modes.

Sleep Mode (High Power Savings)

The sleep mode reduces power dissipation by disabling the clock to the
processor core (CCLK). The PLL and system clock (SCLK), however, con­tinue to operate in this mode. Typically an external event will wake up the
processor. When in the sleep mode, assertion of any interrupt causes the
processor to sense the value of the bypass bit (
register (PLL_CTL). If bypass is disabled, the processor transitions to the
full on mode. If bypass is enabled, the processor transitions to the active
mode.

When in the sleep mode, system DMA access to L1 memory is not
supported.

ADSP-BF59x Blackfin Processor Hardware Reference 1-17

BYPASS) in the PLL control

Instruction Set Description

Deep Sleep Mode (Maximum Power Savings)

The deep sleep mode maximizes dynamic power savings by disabling the
processor core and synchronous system clocks (CCLK and SCLK). Asynchro­nous systems may still be running, but cannot access internal resources or
external memory. This powered-down mode can only be exited by asser­tion of the reset interrupt or by an wakeup input. When in deep sleep
mode, a wakeup input interrupt causes the processor to transition to the
active mode. Assertion of RESET while in deep sleep mode causes the pro­cessor to transition to the full on mode.

Hibernate State

For lowest possible power dissipation, this state allows the internal supply
(V

DDINT

running. Although not strictly an operating mode like the four modes
detailed above, it is illustrative to view it as such.

) to be powered down, while keeping the I/O supply (V

DDEXT

)

Instruction Set Description

The Blackfin processor family assembly language instruction set employs
an algebraic syntax designed for ease of coding and readability. Refer to
the Blackfin Processor Programming Reference for detailed information. The
instructions have been specifically tuned to provide a flexible, densely
encoded instruction set that compiles to a very small final memory size.
The instruction set also provides fully featured multifunction instructions
that allow the programmer to use many of the processor core resources in
a single instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when compiling C
and C++ source code. In addition, the architecture supports both user
(algorithm/application code) and supervisor (O/S kernel, device drivers,
debuggers, ISRs) modes of operation, allowing multiple levels of access to
core resources.

1-18 ADSP-BF59x Blackfin Processor Hardware Reference

Introduction

The assembly language, which takes advantage of the processor’s unique
architecture, offers these advantages:

• Embedded 16/32-bit microcontroller features, such as arbitrary bit
and bit field manipulation, insertion, and extraction; integer opera­tions on 8-, 16-, and 32-bit data types; and separate user and
supervisor stack pointers

• Seamlessly integrated DSP/CPU features optimized for both 8-bit
and 16-bit operations

• A multi-issue load/store modified Harvard architecture, which sup­ports two 16-bit MAC or four 8-bit ALU + two load/store + two
pointer updates per cycle

• All registers, I/O, and memory mapped into a unified 4G byte
memory space, providing a simplified programming model

Code density enhancements include intermixing of 16- and 32-bit
instructions with no mode switching or code segregation. Frequently used
instructions are encoded in 16 bits.

Development Tools

The processor is supported with a complete set of CROSSCORE® soft­ware and hardware development tools, including Analog Devices

emulators and the VisualDSP++® development environment. The same
emulator hardware that supports other Analog Devices products also fully
emulates the Blackfin processor family.

The VisualDSP++ project management environment lets programmers
develop and debug an application. This environment includes an
easy-to-use assembler that is based on an algebraic syntax, an archiver
(librarian/library builder), a linker, a loader, a cycle-accurate instruc­tion-level simulator, a C/C++ compiler, and a C/C++ runtime library that

ADSP-BF59x Blackfin Processor Hardware Reference 1-19

Development Tools

includes DSP and mathematical functions. A key point for these tools is
C/C++ code efficiency. The compiler has been developed for efficient
translation of C/C++ code to Blackfin processor assembly. The Blackfin
processor has architectural features that improve the efficiency of com­piled C/C++ code.

Debugging both C/C++ and assembly programs with the VisualDSP++
debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source and
object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory, and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ Integrated Development and Debugging Environment
(IDDE) lets programmers define and manage software development. Its
dialog boxes and property pages let programmers configure and manage all
development tools, including color syntax highlighting in the Visu­alDSP++ editor. These capabilities permit programmers to:

• Control how the development tools process inputs and generate
outputs

• Maintain a one-to-one correspondence with the tool’s com­mand-line switches

1-20 ADSP-BF59x Blackfin Processor Hardware Reference

Introduction

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource
management tailored specifically to address the memory and timing con­straints of DSP programming. These capabilities enable engineers to
develop code more effectively, eliminating the need to start from the very
beginning, when developing new application code. The VDK features
include threads, critical and unscheduled regions, semaphores, events, and
device flags. The VDK also supports priority-based, pre-emptive, coopera­tive and time-sliced scheduling approaches. In addition, the VDK was
designed to be scalable. If the application does not use a specific feature,
the support code for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to use it or
not. The VDK is integrated into the VisualDSP++ development environ­ment but can also be used with standard command-line tools. The VDK
development environment assists in managing system resources, automat­ing the generation of various VDK-based objects, and visualizing the
system state during application debug.

Analog Devices emulators use the IEEE 1149.1 JTAG test access port of
the processor to monitor and control the target board processor during
emulation. The emulator provides full speed emulation, allowing inspec­tion and modification of memory, registers, and processor stacks.
Nonintrusive in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system loading or
timing.

In addition to the software and hardware development tools available
from Analog Devices, third parties provide a wide range of tools support­ing the Blackfin processor family. Hardware tools include the
ADSP-BF59x EZ-KIT Lite standalone evaluation/development cards.
Third party software tools include DSP libraries, real-time operating sys­tems, and block diagram design tools.

ADSP-BF59x Blackfin Processor Hardware Reference 1-21

Development Tools

1-22 ADSP-BF59x Blackfin Processor Hardware Reference

2MEMORY

This chapter discusses memory population specific to the ADSP-BF59x
processors. Functional memory architecture is described in the Blackfin
Processor Programming Reference.



Note that the ADSP-BF59x processors do not have L1 instruction
cache or data cache. For ADSP-BF59x processors, disregard those
portions of the Blackfin Processor Programming Reference that per­tain to cache.

Memory Architecture

Figure 2-1 on page 2-2 provides an overview of the ADSP-BF59x proces-

sor system memory map. For a detailed discussion of how to use them, see
the Blackfin Processor Programming Reference.

Note the architecture does not define a separate I/O space. All resources
are mapped through the flat 32-bit address space. The memory is
byte-addressable.

The upper portion of internal memory space is allocated to the core and
system MMRs. Accesses to this area are allowed only when the processor is
in supervisor or emulation mode (see the Operating Modes and States
chapter of the Blackfin Processor Programming Reference).

ADSP-BF59x Blackfin Processor Hardware Reference 2-1

L1 Instruction SRAM

0x0000 0000

0xEF00 0000

0xFF80 0000

0xFF80 8000

0xFFA0 0000

0xFFA0 8000

0xFFA1 0000

0xFFA2 0000

0xFFB0 0000

0xFFB0 1000

0xFFC0 0000

0xFFE0 0000

BOOT ROM (4K BYTES)

RESERVED

L1 ROM (64K BYTES)

RESERVED

INTERNAL SCRATCHPAD RAM (4K BYTES)

RESERVED

SYSTEM MEMORY MAPPED REGISTERS (2M BYTES)

CORE MEMORY MAPPED REGISTERS (2M BYTES)

RESERVED

DATA BANK SRAM (32K BYTES)

RESERVED

INSTRUCTION BANK A SRAM (16K BYTES)

RESERVED

0xEF00 1000

0xFFFF FFFF

INSTRUCTION BANK B SRAM (16K BYTES)

0xFFA0 4000

Figure 2-1. ADSP-BF59x Memory Map

L1 Instruction SRAM

The processor core reads the instruction memory through the 64-bit wide
instruction fetch bus. All addresses from this bus are 64-bit aligned. Each
instruction fetch can return any combination of 16-, 32-, or 64-bit
instructions (for example, four 16-bit instructions, two 16-bit instructions
and one 32-bit instruction, or one 64-bit instruction).

Table 2-1 lists the memory start locations of the L1 instruction SRAM

subbanks.

Table 2-1. L1 Instruction Memory Subbanks

Memory Bbank Memory Subbank Memory Start Location for

Instruction Bank A 0 0xFFA0 0000

Instruction Bank A 1 0xFFA0 1000

2-2 ADSP-BF59x Blackfin Processor Hardware Reference

ADSP-BF59x Processors

Memory

Table 2-1. L1 Instruction Memory Subbanks (Continued)

Memory Bbank Memory Subbank Memory Start Location for

ADSP-BF59x Processors

Instruction Bank A 2 0xFFA0 2000

Instruction Bank A 3 0xFFA0 3000

Instruction Bank B 0 0xFFA0 4000

Instruction Bank B 1 0xFFA0 5000

Instruction Bank B 2 0xFFA0 6000

Instruction Bank B 3 0xFFA0 7000

L1 Instruction ROM

The 64K byte L1 instruction ROM consists of a single 64K byte bank of
read-only memory. The instruction ROM is typically read by the proces­sor to acquire instructions for execution, but contents of instruction ROM
may also be read using the DTEST_COMMAND and DTEST_DATA registers.
Attempts to write ROM using the DTEST_COMMAND and DTEST_DATA regis­ters fail without any errors or exceptions signaled by hardware. DMA
access of instruction ROM is not possible.

L1 Data SRAM

Table 2-2 shows how the subbank organization is mapped into memory.

Table 2-2. L1 Data Memory SRAM Subbank Start Addresses

Memory Bank and Subbank ADSP-BF59x Processors

Data Bank A, Subbank 0 0xFF80 0000

Data Bank A, Subbank 1 0xFF80 1000

Data Bank A, Subbank 2 0xFF80 2000

ADSP-BF59x Blackfin Processor Hardware Reference 2-3

Boot ROM

Table 2-2. L1 Data Memory SRAM Subbank Start Addresses (Continued)

Memory Bank and Subbank ADSP-BF59x Processors

Data Bank A, Subbank 3 0xFF80 3000

Data Bank A, Subbank 4 0xFF80 4000

Data Bank A, Subbank 5 0xFF80 5000

Data Bank A, Subbank 6 0xFF80 6000

Data Bank A, Subbank 7 0xFF80 7000

Boot ROM

A 4K byte area of internal memory space is occupied by the boot ROM,
starting from address 0xEF00 0000. This 16-bit boot ROM is not part of
the L1 memory module. Read accesses take one SCLK cycle and no wait
states are required. The read-only memory can be read by the core as well
as by DMA. The boot ROM not only contains boot-strap loader code, it
also provides some subfunctions that are user-callable at runtime. For
more information, see “System Reset and Booting” in Chapter 16, System

Reset and Booting.

External Memory

Aside from the Boot ROM, which sits in External Memory space, there is
no additional external memory address space on the processor.

Processor-Specific MMRs

The complete set of memory-related MMRs is described in the Blackfin
Processor Programming Reference. Several MMRs have bit definitions spe-

cific to the processors described in this manual. These registers are
described in the following sections.

2-4 ADSP-BF59x Blackfin Processor Hardware Reference

Memory

X

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

XXXXXXX XXXXXXXX

Data Test Command Register (DTEST_COMMAND)

Address bits [13:12]

ADR[13:12]

Reset = Undefined

Read/Write Access

ADR[11]

Address bit [11]

REGION[2:0]

000 - L1 Data SRAM from 0xFF80 0000 to 0xFF80 7FFF
100 - L1 Inst SRAM from 0xFFA0 0000 to 0xFFA0 3FFF
101 - L1 Inst ROM from 0xFFA1 000 to 0xFFA1 FFFF

Note that the ITEST COMMAND register must be used to
access to L1 Inst SRAM from 0xFFA0 4000 to 0xFFA0 7FFF

0 - Read access
1 - Write access

Reserved - Write 1

ADR[10:3]

Address bits [10:3]

ADR[15:14]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

XXXXXXXXX XX XXXXX

0xFFE0 0300

Address bits [15:14]

DTEST_COMMAND Register

When the data test command register (DTEST_COMMAND) is written to, L1
memory is accessed, and the data is transferred through the data test data
registers (DTEST DATA[1:0]). This register is shown in Figure 2-2.



DTEST_COMMAND MMR to L1 instruction SRAM.

Figure 2-2. Data Test Command Register

The data/instruction access bit allows direct access via the

ADSP-BF59x Blackfin Processor Hardware Reference 2-5

Processor-Specific MMRs

X

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

XXXXXXX XXXXXXXX

Instruction Test Command Register (ITEST_COMMAND)

Address bits [13:12]

ADR[13:12]

Reset = Undefined

Read/Write Access

ADR[11:10]

Address bits [11:10]

0 - Read access
1 - Write access

Reserved - Write 1

ADR[9:3]

Address bits [9:3]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

XXXXXXXXX XX XXXXX

0xFFE0 1300

ITEST_COMMAND Register

The instruction test command register (ITEST_COMMAND), shown in

Figure 2-3, contains control bits for the L1 data memory.

Figure 2-3. Instruction Test Command Register

This register may be used to gain access to the 16K bytese of L1 instruc­tion SRAM from address 0xFFA04000 to address 0xFFA07FFF. All other
regions of L1 memory—both data and instruction—are accessed using the

DTEST_COMMAND register.

2-6 ADSP-BF59x Blackfin Processor Hardware Reference

DMEM_CONTROL Register

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0000000 00000000

Data Memory Control Register (DMEM_CONTROL)

Reset = 0x00000001

ENDCPLB (Data Cacheability
Protection Lookaside Buffer
Enable)

0 - CPLBs disabled. Minimal
address checking only
1 - CPLBs enabled

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

10000000000 00000

0xFFE0 0004

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0000000 00000000

Instruction Memory Control Register (IMEM_CONTROL)

Reset = 0x00000001

ENICPLB (Instruction Cache­ability Protection Lookaside
Buffer Enable)

0 - CPLBs disabled. Minimal
address checking only
1 - CPLBs enabled

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

10000000000 00000

0xFFE0 1004

The data memory control register (DMEM_CONTROL), shown in Figure 2-4,
contains control bits for the L1 data memory.

Figure 2-4. Data Memory Control Register

Memory

IMEM_CONTROL Register

The instruction memory control register (IMEM_CONTROL), shown in

Figure 2-5, contains control bits for the L1 instruction memory.

Figure 2-5. Instruction Memory Control Register

ADSP-BF59x Blackfin Processor Hardware Reference 2-7

Processor-Specific MMRs

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0000000 00000000

Data CPLB Data Registers (DCPLB_DATAx)

00 - 1K byte page
01 - 4K byte page
10 - 1M byte page
11 - 4M byte page

PAGE_SIZE1–0

Reset = 0x00000000

CPLB_VALID

0 - Invalid (disabled) CPLB entry
1 - Valid (enabled) CPLB entry

CPLB_USER_WR

0 - Write access prohibited
in User Mode (writes generate
protection violation exceptions)
1 - Write access permitted
in User Mode

CPLB_SUPV_WR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00000000000 00000

0xFFE0 023C
0xFFE0 0228
0xFFE0 0214
0xFFE0 0200

0 - Write access prohibited
in Supervisor Mode (writes generate
protection violation exceptions)
1 - Write access permitted
in Supervisor Mode

CPLB_LOCK

0 - Unlocked, CPLB entry replaceable
1 - Locked, CPLB entry not replaceable

CPLB_USER_RD

0 - Read access prohibited
in User Mode (reads generate
protection violation exceptionss)
1 - Read access permitted
in User Mode

DCPLB_DATAx Registers

The data CPLB data registers (DCPLB_DATAx), shown in Figure 2-6,
contain CPLB control bits for the L1 data memory.

Figure 2-6. Data CPLB Data Register

2-8 ADSP-BF59x Blackfin Processor Hardware Reference

Memory

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

0000000 00000000

Instruction CPLB Data Registers (ICPLB_DATAx)

00 - 1K byte page
01 - 4K byte page
10 - 1M byte page
11 - 4M byte page

PAGE_SIZE1–0

Reset = 0x00000000

CPLB_VALID

0 - Invalid (disabled) CPLB entry
1 - Valid (enabled) CPLB entry

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00000000000 00000

0xFFE0 123C
0xFFE0 1228
0xFFE0 1214
0xFFE0 1200

CPLB_LOCK

0 - Unlocked, CPLB entry replaceable
1 - Locked, CPLB entry not replaceable

CPLB_USER_RD

0 - Read access prohibited
in User Mode (reads generate
protection violation exceptionss)
1 - Read access permitted
in User Mode

ICPLB_DATAx Registers

The instruction CPLB data registers (ICPLB_DATAx), shown in Figure 2-7,
contain CPLB control bits for the L1 instruction memory.

Figure 2-7. Instruction CPLB Data Register

ADSP-BF59x Blackfin Processor Hardware Reference 2-9

Processor-Specific MMRs

2-10 ADSP-BF59x Blackfin Processor Hardware Reference

3 CHIP BUS HIERARCHY

This chapter discusses on-chip buses, how data moves through the system,
and other factors that determine the system organization. Following an
overview and a list of key features is a block diagram of the chip bus hier­archy and a description of its operation. The chapter concludes with
details about the system interconnects and associated system buses.

This chapter provides

• “Chip Bus Hierarchy Overview” on page 3-1

• “Interface Overview” on page 3-2

Chip Bus Hierarchy Overview

ADSP-BF59x Blackfin processors feature a powerful chip bus hierarchy on
which all data movement between the processor core, internal memory,
and its rich set of peripherals occurs. The chip bus hierarchy includes the
controllers for system interrupts, test/emulation, and clock and power
management. Synchronous clock domain conversion is provided to sup­port clock domain transactions between the core and the system.

The processor system includes:

• The peripheral set including timers, TWI, UART, SPORTs, SPIs,
PPI, and watchdog timer

• The Direct Memory Access (DMA) controller

• The interfaces between these and the system

ADSP-BF59x Blackfin Processor Hardware Reference 3-1

Interface Overview

GPIOS

SPORTs

SPIs

BOOT

ROM

PPI

UART

TIMERS

DMA

CONTROLLER

L1

SRAM

&

L1

ROM

CORE

PROCESSOR

INSTRUCTION

LOAD DATA

LOAD DATA

64

32

32

32

STORE DATA

SYSTEM CLOCK
(SCLK) DOMAIN

CORE CLOCK
(CCLK) DOMAIN

DMA

ACCESS

BUS

(DAB)

DMA
EXT.
BUS
(DEB)

DMA
CORE
BUS
(DCB)

WATCHDOG

TIMER

TWI

PERIPHERAL

ACCESS

BUS (PAB)

16

16

16

PLL

VOLTAGE

CONTROL UNIT

16

The following sections describe the on-chip interfaces between the system
and the peripherals via the:

• Peripheral Access Bus (PAB)

• DMA Access Bus (DAB)

• DMA Core Bus (DCB)

Interface Overview

Figure 3-1 shows the core processor and system boundaries as well as the

interfaces between them.

Figure 3-1. Processor Bus Hierarchy

3-2 ADSP-BF59x Blackfin Processor Hardware Reference

Chip Bus Hierarchy

Internal Clocks

The core processor clock (CCLK) rate is highly programmable with respect
to CLKIN. The CCLK rate is divided down from the Phase Locked Loop
(PLL) output rate. This divider ratio is set using the CSEL parameter of the
PLL divide register.

The PAB, the DAB, and the DCB run at system clock frequency (SCLK
domain). This divider ratio is set using the SSEL parameter of the PLL
divide (PLL_DIV) register and must be set so that these buses run as speci­fied in the processor data sheet, and slower than or equal to the core clock
frequency.

These buses can also be cycled at a programmable frequency to reduce
power consumption, or to allow the core processor to run at an optimal
frequency. Note all synchronous peripherals derive their timing from the

SCLK. For example, the UART clock rate is determined by further divid-

ing this clock frequency.

Core Bus Overview

For the purposes of this discussion, level 1 memories (L1) are included in
the description of the core; they have full bandwidth access from the pro­cessor core with a 64-bit instruction bus and two 32-bit data buses.

Figure 3-2 shows the core processor and its interfaces to the peripherals

and external memory resources.

The core can generate up to three simultaneous off-core accesses per cycle.

The core bus structure between the processor and L1 memory runs at the
full core frequency and has data paths up to 64 bits.

When the instruction request is filled, the 64-bit read can contain a single
64-bit instruction or any combination of 16-, 32-, or 64-bit (partial)
instructions.

ADSP-BF59x Blackfin Processor Hardware Reference 3-3

Interface Overview

INT

RESET

VECTOR

ACK

CORE TIMER

CORE

EVENT

CONTROLLER

DEBUG AND JTAG INTERFACE

JTAG

DSP ID

(8 BITS)

SYSTEM CLOCK

AND POWER

MANAGEMENT

POWER AND

CLOCK

CONTROLLER

PERFORMANCE

MONITOR

MEMORY

MANAGEMENT

UNIT

L1 DATA

L1 INSTRUCTION

LD0

LD1

SD

DA0

DA1

IAB

IDB

CORE

EAB

PROCESSOR

DMA CORE BUS
(DCB)

PAB

32 32 32 32 32 32 64

Figure 3-2. Core Block Diagram

Peripheral Access Bus (PAB)

The processor has a dedicated low latency peripheral bus that keeps core
stalls to a minimum and allows for manageable interrupt latencies to
time-critical peripherals. All peripheral resources accessed through the
PAB are mapped into the system MMR space of the processor memory
map. The core accesses system MMR space through the PAB bus.

3-4 ADSP-BF59x Blackfin Processor Hardware Reference

Chip Bus Hierarchy

The core processor has byte addressability, but the programming model is
restricted to only 32-bit (aligned) access to the system MMRs. Byte
accesses to this region are not supported.

PAB Arbitration

The core is the only master on this bus. No arbitration is necessary.

PAB Agents (Masters, Slaves)

The processor core can master bus operations on the PAB. All peripherals
have a peripheral bus slave interface which allows the core to access con­trol and status state. These registers are mapped into the system MMR
space of the memory map. Appendix B lists system MMR addresses.

The slaves on the PAB bus are:

• System event controller

• Clock and power management controller

• Watchdog timer

• Timer 0–2

• SPORT0–1

• SPI0–1

• General-purpose ports

•UART

•PPI

• TWI

• DMA controller

ADSP-BF59x Blackfin Processor Hardware Reference 3-5

Interface Overview

PAB Performance

For the PAB, the primary performance criteria is latency, not throughput.
Transfer latencies for both read and write transfers on the PAB are two

SCLK cycles.

For example, the core can transfer up to 32 bits per access to the PAB
slaves. With the core clock running at 2x the frequency of the system
clock, the first and subsequent system MMR read or write accesses take
four core clocks (CCLK) of latency.

The PAB has a maximum frequency of SCLK.

DMA Access Bus (DAB), DMA Core Bus (DCB)

The DAB and DCB buses provide a means for DMA-capable peripherals
to gain access to on-chip memory with little or no degradation in core
bandwidth to memory.

DAB and DCB Arbitration

Thirteen DMA channels and bus masters support the DMA-capable
peripherals in the processor system. The nine peripheral DMA channel
controllers can transfer data between peripherals and internal memory.
Both the read and write channels of the dual-stream memory DMA con­troller access their descriptor lists through the DAB.

The DCB has priority over the core processor on arbitration into L1
SRAM. The processor has a programmable priority arbitration policy on
the DAB. Table 3-1 shows the default arbitration priority.

Table 3-1. DAB and DCB Arbitration Priority

DAB, DCB Master Default Arbitration Priority

PPI receive or transmit 0 - highest

SPORT0 receive 1

3-6 ADSP-BF59x Blackfin Processor Hardware Reference

Chip Bus Hierarchy

Table 3-1. DAB and DCB Arbitration Priority (Continued)

DAB, DCB Master Default Arbitration Priority

SPORT0 transmit 2

SPORT1 receive 3

SPORT1 transmit 4

SPI0 transmit/receive 5

SPI1 transmit/receive 6

UART0 receive 7

UART0 transmit 8

Not available on this product 9

Not available on this product 10

Not available on this product 11

Mem DMA has no peripheral mapping. 12

Mem DMA has no peripheral mapping. 13

Mem DMA has no peripheral mapping. 14

Mem DMA has no peripheral mapping. 15 - lowest

DAB Bus Agents (Masters)

All peripherals capable of sourcing a DMA access are masters on this bus,
as shown in Table 3-1. A single arbiter supports a programmable priority
arbitration policy for access to the DAB.

When two or more DMA master channels are actively requesting the
DAB, bus utilization is considerably higher due to the DAB’s pipelined
design. Bus arbitration cycles are concurrent with the previous DMA
access’s data cycles.

ADSP-BF59x Blackfin Processor Hardware Reference 3-7

Interface Overview

DAB and DCB Performance

The processor DAB supports data transfers of 16 bits or 32 bits. The data
bus has a 16-bit width with a maximum frequency as specified in the pro­cessor data sheet.

The DAB has a dedicated port into L1 memory. No stalls occur as long as
the core access and the DMA access are not to the same memory bank (4K
byte size for L1). If there is a conflict, DMA is the highest priority
requester, followed by the core.

Note that a locked transfer by the core processor effectively disables arbi­tration for the addressed memory bank or resource until the memory lock
is deasserted. DMA controllers cannot perform locked transfers.

DMA access to L1 memory can only be stalled by an access already in
progress from another DMA channel. Latencies caused by these stalls are
in addition to any arbitration latencies.

3-8 ADSP-BF59x Blackfin Processor Hardware Reference

4 SYSTEM INTERRUPTS

This chapter discusses the system interrupt controller (SIC). While this
chapter does refer to features of the core event controller (CEC), it does
not cover all aspects of it. Please refer to the Blackfin Processor Program-
ming Reference for more information on the CEC.

Specific Information for the ADSP-BF59x

For details regarding the number of system interrupts for the
ADSP-BF59x product, please refer to the ADSP-BF592 Blackfin Processor
Data Sheet.

To determine how each of the system interrupts is multiplexed with other
functional pins, refer to Table 7-1 on page 7-3 through Table 7-2 on

page 7-4 in Chapter 7, “General-Purpose Ports”.

For a list of MMR addresses for each DMA, refer to Chapter A, “System

MMR Assignments”.

System interrupt behavior for the ADSP-BF59x that differs from the gen­eral information in this chapter can be found at the end of this chapter in
the section “Unique Information for the ADSP-BF59x Processor” on

page 4-15.

Overview

The processor system has numerous peripherals, which therefore require
many supporting interrupts.

ADSP-BF59x Blackfin Processor Hardware Reference 4-1

Description of Operation

Features

The Blackfin architecture provides a two-level interrupt processing
scheme:

• The core event controller (CEC) runs in the CCLK clock domain. It
interacts closely with the program sequencer and manages the event
vector table (EVT). The CEC processes not only core-related inter­rupts such as exceptions, core errors, and emulation events; it also
supports software interrupts.

• The system interrupt controller (SIC) runs in the SCLK clock
domain. It masks, groups, and prioritizes interrupt requests sig­nalled by on-chip or off-chip peripherals and forwards them to the
CEC.

Description of Operation

The following sections describe the operation of the system interrupts.

Events and Sequencing

The processor employs a two-level event control mechanism. The proces­sor SIC works with the CEC to prioritize and control all system
interrupts. The SIC provides mapping between the many peripheral inter­rupt sources and the prioritized general-purpose interrupt inputs of the
core. This mapping is programmable, and individual interrupt sources can
be masked in the SIC.

The CEC of the processor manages five types of activities or events:

• Emulation

•Reset

• Nonmaskable interrupts (NMI)

4-2 ADSP-BF59x Blackfin Processor Hardware Reference

System Interrupts

• Exceptions

• Interrupts

Note the word event describes all five types of activities. The CEC man­ages fifteen different events in all: emulation, reset, NMI, exception, and
eleven interrupts.

An interrupt is an event that changes the normal processor instruction
flow and is asynchronous to program flow. In contrast, an exception is a
software initiated event whose effects are synchronous to program flow.

The event system is nested and prioritized. Consequently, several service
routines may be active at any time, and a low priority event may be
pre-empted by one of higher priority.

The CEC supports nine general-purpose interrupts (

IVG7 – IVG15) in

addition to the dedicated interrupt and exception events that are described
in Table 4-1. It is common for applications to reserve the lowest or the
two lowest priority interrupts (IVG14 and IVG15) for software interrupts,
leaving eight or seven prioritized interrupt inputs (IVG7 – IVG13) for
peripheral purposes. Refer to Table 4-1.

Table 4-1. System and Core Event Mapping

Event Source Core Event

Name

Core events

Emulation (highest priority) EMU

Reset RST

NMI NMI

Exception EVX

Reserved –

Hardware error IVHW

Core timer IVTMR

ADSP-BF59x Blackfin Processor Hardware Reference 4-3

Description of Operation

Table 4-1. System and Core Event Mapping (Continued)

Event Source Core Event

Name

System interrupts IVG7–IVG13

Software interrupt 1 IVG14

Software interrupt 2 (lowest priority) IVG15

System Peripheral Interrupts

To service the rich set of peripherals, the SIC has multiple interrupt
request inputs and outputs that go to the CEC. The primary function of
the SIC is to mask, group, and prioritize interrupt requests and to forward
them to the nine general-purpose interrupt inputs of the CEC (IVG7–

IVG15). Additionally, the SIC controller can enable individual peripheral

interrupts to wake up the processor from Idle or power-down state.

The nine general-purpose interrupt inputs (IVG7–IVG15) of the core event
controller have fixed priority. Of this group, the IVG7 channel has the
highest priority and IVG15 has the lowest priority. Therefore, the interrupt
assignment in the SIC_IAR registers not only groups peripheral interrupts;
it also programs their priority by assigning them to individual IVG chan­nels. However, the relative priority of peripheral interrupts can be set by
mapping the peripheral interrupt to the appropriate general-purpose inter­rupt level in the core. The mapping is controlled by the

SIC_IAR register

settings shown in Figure 4-2 on page 4-11 and the tables in Chapter A,

“System MMR Assignments”. If more than one interrupt source is

mapped to the same interrupt, they are logically OR’ed, with no hardware
prioritization. Software can prioritize the interrupt processing as required
for a particular system application.

For general-purpose interrupts with multiple peripheral interrupts



assigned to them, take special care to ensure that software correctly
processes all pending interrupts sharing that input. Software is
responsible for prioritizing the shared interrupts.

4-4 ADSP-BF59x Blackfin Processor Hardware Reference

System Interrupts

The core timer has a dedicated input to the CEC controller. Its interrupt
is not routed through the SIC controller and always has higher priority
than requests from all peripherals.

The

SIC_IMASK register allows software to mask any peripheral interrupt

source at the SIC level. This functionality is independent of whether the
particular interrupt is enabled at the peripheral itself. At reset, the con­tents of the SIC_IMASK register are all 0s to mask off all peripheral
interrupts. Turning off a system interrupt mask and enabling the particu­lar interrupt is performed by writing a 1 to a bit location in the SIC_IMASK
register.

The SIC includes one or more read-only SIC_ISR registers with individual
bits which correspond to the interrupt status of one of the peripheral
interrupt sources. When the SIC detects the interrupt, the bit is asserted.
When the SIC detects that the peripheral interrupt input has been deas­serted, the respective bit in the system interrupt status register is cleared.
Note for some peripherals, such as general-purpose I/O asynchronous
input interrupts, many cycles of latency may pass from the time an inter­rupt service routine initiates the clearing of the interrupt (usually by
writing a system MMR) to the time the SIC senses that the interrupt has
been deasserted.

Depending on how interrupt sources map to the general-purpose interrupt
inputs of the core, the interrupt service routine may have to interrogate
multiple interrupt status bits to determine the source of the interrupt.
One of the first instructions executed in an interrupt service routine
should read the

SIC_ISR register to determine whether more than one of

the peripherals sharing the input has asserted its interrupt output. The ser­vice routine should fully process all pending, shared interrupts before
executing the RTI, which enables further interrupt generation on that
interrupt input.

ADSP-BF59x Blackfin Processor Hardware Reference 4-5

Description of Operation



Many systems need relatively few interrupt-enabled peripherals, allowing
each peripheral to map to a unique core priority level. In these designs, the

SIC_ISR register will seldom, if ever, need to be interrogated.

The SIC_ISR register is not affected by the state of the SIC_IMASK register
and can be read at any time. Writes to the SIC_ISR register have no effect
on its contents.

Peripheral DMA channels are mapped in a fixed manner to the peripheral
interrupt IDs. However, the assignment between peripherals and DMA
channels is freely programmable with the DMA_PERIPHERAL_MAP registers.

Table 4-1 on page 4-3 and Table 4-2 on page 4-11 show the default DMA

assignment. Once a peripheral has been assigned to any other DMA chan­nel it uses the new DMA channel’s interrupt ID regardless of whether
DMA is enabled or not. Therefore, clean DMA_PERIPHERAL_MAP manage­ment is required even if the DMA is not used. The default setup should be
the best choice for all non-DMA applications.

When an interrupt’s service routine is finished, the RTI instruction
clears the appropriate bit in the IPEND register. However, the rele­vant SIC_ISR bit is not cleared unless the service routine clears the
mechanism that generated the interrupt.

For dynamic power management, any of the peripherals can be configured
to wake up the core from its idled state to process the interrupt, simply by
enabling the appropriate bit in the

page 4-3 and Table 4-2 on page 4-11). If a peripheral interrupt source is

enabled in SIC_IWR and the core is idled, the interrupt causes the DPMC
to initiate the core wakeup sequence in order to process the interrupt.
Note this mode of operation may add latency to interrupt processing,
depending on the power control state. For further discussion of power
modes and the idled state of the core, see the Dynamic Power Manage­ment chapter.

The

SIC_IWR register has no effect unless the core is idled. By default, all

interrupts generate a wakeup request to the core. However, for some

4-6 ADSP-BF59x Blackfin Processor Hardware Reference

SIC_IWR register (refer to Table 4-1 on

System Interrupts

applications it may be desirable to disable this function for some peripher­als, such as for a SPORT transmit interrupt. The
read from or written to at any time. To prevent spurious or lost interrupt
activity, this register should be written to only when all peripheral inter­rupts are disabled.

SIC_IWR register can be



The peripheral interrupt structure of the processor is flexible. Upon reset,
multiple peripheral interrupts share a single, general-purpose interrupt in
the core by default, as shown in Table 4-2 on page 4-11.

An interrupt service routine that supports multiple interrupt sources must
interrogate the appropriate system memory mapped registers (MMRs) to
determine which peripheral generated the interrupt.

The wakeup function is independent of the interrupt mask func­tion. If an interrupt source is enabled in the SIC_IWR but masked
off in the SIC_IMASK register, the core wakes up if it is idled, but it
does not generate an interrupt.

Programming Model

The programming model for the system interrupts is described in the fol­lowing sections.

System Interrupt Initialization

If the default peripheral-to-IVG assignments shown in Table 4-1 on

page 4-3 and Table 4-2 on page 4-11 are acceptable, then interrupt initial-

ization involves only:

• Initialization of the core event vector table (EVT) vector address
entries

ADSP-BF59x Blackfin Processor Hardware Reference 4-7

Programming Model

• Initialization of the

IMASK register

• Unmasking the specific peripheral interrupts that the system
requires in the SIC_IMASK register

System Interrupt Processing Summary

Referring to Figure 4-1 on page 4-9, note when an interrupt (interrupt A)
is generated by an interrupt-enabled peripheral:

1. SIC_ISR logs the request and keeps track of system interrupts that
are asserted but not yet serviced (that is, an interrupt service rou­tine hasn’t yet cleared the interrupt).

2. SIC_IWR checks to see if it should wake up the core from an idled
state based on this interrupt request.

3. SIC_IMASK masks off or enables interrupts from peripherals at the
system level. If interrupt A is not masked, the request proceeds to
Step 4.

4. The SIC_IAR registers, which map the peripheral interrupts to a
smaller set of general-purpose core interrupts (IVG7 – IVG15),
determine the core priority of interrupt A.

ILAT adds interrupt A to its log of interrupts latched by the core

5.
but not yet actively being serviced.

6.

IMASK masks off or enables events of different core priorities. If the
IVGx event corresponding to interrupt A is not masked, the process

proceeds to Step 7.

7. The event vector table (EVT) is accessed to look up the appropriate
vector for interrupt A’s interrupt service routine (ISR).

4-8 ADSP-BF59x Blackfin Processor Hardware Reference

System Interrupts

"INTERRUPT

A"

SYSTEM

INTERRUPT

MASK

(SIC_IMASK)

ASSIGN

SYSTEM
PRIORITY
(SIC_IAR)

CORE EVENT CONTROLLERSYSTEM INTERRUPT CONTROLLER

NOTE: NAMES IN PARENTHESES ARE MEMORY-MAPPED REGISTERS.

EMU
RESET
NMI
EVX
IVTMR

IVHW
PERIPHERAL
INTERRUPT
REQUESTS

CORE

EVENT

VECTOR

TABLE

(EVT[15:0])

CORE

PENDING

(IPEND)

CORE

STATUS

(ILAT)

CORE

INTERRUPT

MASK

(IMASK)

SYSTEM

WAKEUP

(SIC_IWR)

SYSTEM
STATUS

(SIC_ISR)

TO DYNAMIC POWER
MANAGEMENT
CONTROLLER

8. When the event vector for interrupt A has entered the core pipe­line, the appropriate

ILAT bit. Thus, IPEND tracks all pending interrupts, as well as those

IPEND bit is set, which clears the respective

being presently serviced.

9. When the interrupt service routine (ISR) for interrupt A has been
executed, the RTI instruction clears the appropriate IPEND bit.
However, the relevant SIC_ISR bit is not cleared unless the inter­rupt service routine clears the mechanism that generated interrupt
A, or if the process of servicing the interrupt clears this bit.

Figure 4-1. Interrupt Processing Block Diagram

It should be noted that emulation, reset, NMI, and exception events, as
well as hardware error (IVHW) and core timer (IVTMR) interrupt requests,
enter the interrupt processing chain at the ILAT level and are not affected

ADSP-BF59x Blackfin Processor Hardware Reference 4-9

System Interrupt Controller Registers

by the system-level interrupt registers (

SIC_IAR).

SIC_IWR, SIC_ISR, SIC_IMASK,

If multiple interrupt sources share a single core interrupt, then the inter­rupt service routine (ISR) must identify the peripheral that generated the
interrupt. The ISR may then need to interrogate the peripheral to deter­mine the appropriate action to take.

System Interrupt Controller Registers

The SIC registers are described in the following sections.

These registers can be read from or written to at any time in supervisor
mode. It is advisable, however, to configure them in the reset interrupt
service routine before enabling interrupts. To prevent spurious or lost
interrupt activity, these registers should be written to only when all
peripheral interrupts are disabled.

System Interrupt Assignment (SIC_IAR) Register

The SIC_IAR register maps each peripheral interrupt ID to a correspond­ing IVG priority level. This is accomplished with 4-bit groupings that
translate to IVG levels as shown in Table 4-2 and Figure 4-2 on

page 4-11. In other words, Table 4-2 defines the value to write in a 4-bit

field within
particular IVG priority. Refer to Table 4-1 on page 4-3 for information
on SIC_IAR mappings for this specific processor.

SIC_IAR in order to configure a peripheral interrupt ID for a

4-10 ADSP-BF59x Blackfin Processor Hardware Reference

Figure 4-2. System Interrupt Assignment Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000000000 0000000

System Interrupt Assignment Register (SIC_IAR)

ID Grouping 0

ID Grouping 2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

00000000000 00000

ID Grouping 7

ID Grouping 4

ID Grouping 1

ID Grouping 5

ID Grouping 6

ID Grouping 3

Table 4-2. IVG Select Definitions

System Interrupts

General-purpose Interrupt Value in SIC_IAR

IVG7 0

IVG8 1

IVG9 2

IVG10 3

IVG11 4

IVG12 5

IVG13 6

IVG14 7

IVG15 8

ADSP-BF59x Blackfin Processor Hardware Reference 4-11

System Interrupt Controller Registers

System Interrupt Mask (SIC_IMASK) Register

The SIC_IMASK register masks or enables peripheral interrupts at the sys­tem level. A "0" in a bit position masks off (disables) interrupts for that
particular peripheral interrupt ID. A "1" enables interrupts for that inter­rupt ID. Refer to Table 4-1 on page 4-3 and Table 4-2 on page 4-11 for
information on how peripheral interrupt IDs are mapped to the

SIC_IMASK register(s) for this particular processor.

System Interrupt Status (SIC_ISR) Register

The SIC_ISR register keeps track of system interrupts that are asserted but
not yet serviced. A "0" in a bit position indicates that a particular inter­rupt is deasserted. A "1" indicates that it is asserted. Refer to Table 4-1 on

page 4-3 and Table 4-2 on page 4-11 for information on how peripheral

interrupt IDs are mapped to the SIC_ISR register(s) for this particular
processor.

System Interrupt Wakeup-Enable (SIC_IWR) Register

The SIC_IWR register allows an interrupt request to wake up the processor
core from an idled state. A "0" in a bit position indicates that a particular
peripheral interrupt ID is not configured to wake the core (upon assertion
of the interrupt request). A "1" indicates that it is configured to do so.
Refer to Table 4-1 on page 4-3 and Table 4-2 on page 4-11 for informa­tion on how peripheral interrupt IDs are mapped to the
register(s) for this particular processor.

4-12 ADSP-BF59x Blackfin Processor Hardware Reference

SIC_IWR

System Interrupts

Programming Examples

The following section provides an example for servicing interrupt
requests.

Clearing Interrupt Requests

When the processor services a core event it automatically clears the
requesting bit in the ILAT register and no further action is required by the
interrupt service routine. It is important to understand that the SIC con­troller does not provide any interrupt acknowledgment feedback
mechanism from the CEC controller back to the peripherals. Although
the ILAT bits clear in the same way when a peripheral interrupt is serviced,
the signalling peripheral does not release its level-sensitive request until it
is explicitly instructed by software. If however, the peripheral keeps
requesting, the respective ILAT bit is set again immediately and the service
routine is invoked again as soon as its first run terminates by an RTI
instruction.

Every software routine that services peripheral interrupts must clear the
signalling interrupt request in the respective peripheral. The individual
peripherals provide customized mechanisms for how to clear interrupt
requests. Receive interrupts, for example, are cleared when received data is
read from the respective buffers. Transmit requests typically clear when
software (or DMA) writes new data into the transmit buffers. These
implicit acknowledge mechanisms avoid the need for cycle-consuming
software handshakes in streaming interfaces. Other peripherals such as
timers, GPIOs, and error requests require explicit acknowledge instruc­tions, which are typically performed by efficient W1C (write-1-to-clear)
operations.

Listing 4-1 shows a representative example of how a GPIO interrupt

request might be serviced.

ADSP-BF59x Blackfin Processor Hardware Reference 4-13

Programming Examples

Listing 4-1. Servicing GPIO Interrupt Request

#include <defBF527.h>
/*ADSP-BF527 product is used as an example*/
.section program;
_portg_a_isr:

/* push used registers */
[--sp] = (r7:7, p5:5);
/* clear interrupt request on GPIO pin PG2 */
/* no matter whether used A or B channel */
p5.l = lo(PORTGIO_CLEAR);
p5.h = hi(PORTGIO_CLEAR);
r7 = PG2;
w[p5] = r7;

/* place user code here */

/* sync system, pop registers and exit */
ssync;
(r7:7, p5:5) = [sp++];
rti;

_portg_a_isr.end:

The W1C instruction shown in this example may require several SCLK
cycles to complete, depending on system load and instruction history. The
program sequencer does not wait until the instruction completes and con­tinues program execution immediately. The

SSYNC instruction ensures that

the W1C command indeed cleared the request in the GPIO peripheral
before the RTI instruction executes. However, the

SSYNC instruction does

not guarantee that the release of interrupt request has also been recognized
by the CEC controller, which may require a few more
ing on the
instructions only, two

CCLK-to-SCLK ratio. In service routines consisting of a few

SSYNC instructions are recommended between the

CCLK cycles depend-

clear command and the RTI instruction. However, one SSYNC instruction
is typically sufficient if the clear command performs in the very beginning

4-14 ADSP-BF59x Blackfin Processor Hardware Reference

System Interrupts

of the service routine, or the
of instructions before the service routine returns. Commonly, a pop-mul­tiple instruction is used for this purpose as shown in Listing 4-1.

The level-sensitive nature of peripheral interrupts enables more than one
of them to share the same IVG channel and therefore the same interrupt
priority. This is programmable using the assignment registers. Then a
common service routine typically interrogates the SIC_ISR register to
determine the signalling interrupt source. If multiple peripherals are
requesting interrupts at the same time, it is up to the service routine to
either service all requests in a single pass or to service them one by one. If
only one request is serviced and the respective request is cleared by soft­ware before the RTI instruction executes, the same service routine is
invoked another time because the second request is still pending. While
the first approach may require fewer cycles to service both requests, the
second approach enables higher priority requests to be serviced more
quickly in a non-nested interrupt system setup.

SSYNC instruction is followed by another set

Unique Information for the ADSP-BF59x Processor

This section describes Interfaces and System Peripheral Interrupts that are
unique to the ADSP-BF59x processor.

Interfaces

Figure 4-3 provides an overview of how the individual peripheral inter-

rupt request lines connect to the SIC. It also shows how the eight
registers control the assignment to the nine available peripheral request
inputs of the CEC.



ADSP-BF59x Blackfin Processor Hardware Reference 4-15

The memory-mapped ILAT, IMASK, and IPEND registers are part of
the CEC controller.

SIC_IAR

Unique Information for the ADSP-BF59x Processor

0

DMA8 (UART0 TX)
PORT F INTERRUPT A
PORT F INTERRUPT B

GP TIMER 0

GP TIMER 2

PORT G INTERRUPT A
PORT G INTERRUPT B

TWI
RESERVED
RESERVED
RESERVED

1
2
3
4
5

6
7

PLL WAKEUP

DMA6 (SPI1 RX/TX)

DMA7 (UART0 RX)

WAKE UP

CORE TIMER

HARDWARE ERROR

EXCEPTIONS

NMI

SIC_IAR3 SIC_IAR2 SIC_IAR1 SIC_IAR0

8

9
10
11
12
13

14
15

16
17
18
19
20
21
22
23

24
25
26
27
28
29
30
31

SIC_ISR0

SIC_IWR0

SIC_IMASK0

RESET

EMULATION

IMASK

IPEND

ILAT

IVG15

IVG14

IVG13

IVG12

IVG11

IVG10

IVG9

IVG8

IVG7

IVG6

IVG5

IVG3

IVG2

IVG1

IVG0

GP TIMER 1

RESERVED

DMA 12/13 (MEM DMA STREAM 0)

WATCHDOG TIMER

DMA 14/15 (MEM DMA STREAM 1)

UART0 STATUS

DMA0 (PPI)

DMA1 (SPORT0 RX)

SPI1 STATUS

DMA2 (SPORT0 TX)

DMA4 (SPORT1 TX)

DMA5 (SPI0 RX/TX)

DMA ERROR (GENERIC)

PPI STATUS

SPORT0 STATUS

SPORT1 STATUS

SPI0 STATUS

DMA3 (SPORT1 RX)

Figure 4-3. Interrupt Routing Overview

4-16 ADSP-BF59x Blackfin Processor Hardware Reference

System Interrupts

System Peripheral Interrupts

Table 4-3 shows the peripheral interrupt events, the default mapping of

each event, the peripheral interrupt ID used in the system interrupt
assignment registers (SIC_IAR), and the core interrupt ID.

Note that the system interrupt to core event mappings shown are the
default values at reset and can be changed by software.

The peripheral interrupt structure of the processor is flexible. Upon reset,
multiple peripheral interrupts share a single, general-purpose interrupt in
the core by default, as shown in Table 4-3.

An interrupt service routine that supports multiple interrupt sources must
interrogate the appropriate system memory mapped registers (MMRs) to
determine which peripheral generated the interrupt.

Table 4-3. Peripheral Interrupt Events

Peripheral
ID Number

31 Bit 31 SIC_IAR3[31:28] Watchdog Timer IVG13

30 Bit 30 SIC_IAR3[27:24] DMA 14/15 (Mem DMA Stream 1) IVG13

29 Bit 29 SIC_IAR3[23:20] DMA 12/13 (Mem DMA Stream 0) IVG13

28 Bit 28 SIC_IAR3[19:16] Reserved IVG7

27 Bit 27 SIC_IAR3[15:12] Reserved IVG7

26 Bit 26 SIC_IAR3[11:8] Reserved IVG7

25 Bit 25 SIC_IAR3[7:4] Reserved IVG7

24 Bit 24 SIC_IAR3[3:0] TWI IVG12

23 Bit 23 SIC_IAR2[31:28] Port G Interupt B IVG12

22 Bit 22 SIC_IAR2[27:24] Port G Interrupt A IVG12

21 Bit 21 SIC_IAR2[23:20] GP Timer 2 IVG11

Bit Position for
SIC_ISR0,
SIC_IMASK0,
SIC_IWR0

SIC_IAR3-0 Interrupt Source Default

Mapping

ADSP-BF59x Blackfin Processor Hardware Reference 4-17

Unique Information for the ADSP-BF59x Processor

Table 4-3. Peripheral Interrupt Events (Continued)

Peripheral
ID Number

20 Bit 20 SIC_IAR2[19:16] GP Timer 1 IVG11

19 Bit 19 SIC_IAR2[15:12] GP Timer 0 IVG11

18 Bit 18 SIC_IAR2[11:8] Port F Interrupt B IVG11

17 Bit 17 SIC_IAR2[7:4] Port F Interrupt A IVG11

16 Bit 16 SIC_IAR2[3:0] DMA8 (UART0 TX) IVG10

15 Bit 15 SIC_IAR1[31:28] DMA7 (UART0 RX) IVG10

14 Bit 14 SIC_IAR1[27:24] DMA6 (SPI1 RX/TX) IVG10

13 Bit 13 SIC_IAR1[23:20] DMA5 (SPI0 RX/TX) IVG10

12 Bit 12 SIC_IAR1[19:16] DMA4 (SPORT1 TX) IVG9

11 Bit 11 SIC_IAR1[15:12] DMA3 (SPORT1 RX) IVG9

10 Bit 10 SIC_IAR1[11:8] DMA2 (SPORT0 TX) IVG9

9 Bit 9 SIC_IAR1[7:4] DMA1 (SPORT0 RX) IVG9

8 Bit 8 SIC_IAR1[3:0] DMA0 (PPI) IVG8

7 Bit 7 SIC_IAR0[31:28] UART0 Status IVG7

6 Bit 6 SIC_IAR0[27:24] SPI1 Status IVG7

5 Bit 5 SIC_IAR0[23:20] SPI0 Status IVG7

4 Bit 4 SIC_IAR0[19:16] SPORT1 Status IVG7

Bit Position for
SIC_ISR0,
SIC_IMASK0,
SIC_IWR0

SIC_IAR3-0 Interrupt Source Default

Mapping

3 Bit 3 SIC_IAR0[15:12] SPORT0 Status IVG7

2 Bit 2 SIC_IAR0[11:8] PPI Status IVG7

1 Bit 1 SIC_IAR0[7:4] DMA Error (generic) IVG7

0 Bit 0 SIC_IAR0[3:0] PLL Wakeup IVG7

4-18 ADSP-BF59x Blackfin Processor Hardware Reference