ANALOG DEVICES ADSP-BF592 Service Manual

Blackfin

SPORT0

VOLTAGE REGULATOR INTERFACE

PORT F

JTAG TEST AND EMULATION

PERIPHERAL

ACCESS BUS

WATCHDOG TIMER

PPI

SPI0

SPI1

BOOT

ROM

DMA

ACCESS

BUS

INTERRUPT

CONTROLLER

DMA

CONTROLLER

L1 DATA

SRAM

L1 INSTRUCTION

SRAM

DCB

B

UART

DEB

TIMER2–0

L1 INSTRUCTION

ROM

GPIO

SPORT1

TWI

PORT G

Embedded Processor

ADSP-BF592

FEATURES

Up to 400 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of

programming and compiler-friendly support

Advanced debug, trace, and performance monitoring

Accepts a wide range of supply voltages for internal and I/O

operations, see Operating Conditions on Page 15
Off-chip voltage regulator interface
64-lead (9 mm × 9 mm) LFCSP package

MEMORY

68K bytes of core-accessible memory

(See Table 1 on Page 3 for L1 and L3 memory size details)
64K byte L1 instruction ROM
Flexible booting options from internal L1 ROM and SPI mem-

ory or from host devices including SPI, PPI, and UART
Memory management unit providing memory protection

PERIPHERALS

Four 32-bit timers/counters, three with PWM support
2 dual-channel, full-duplex synchronous serial ports (SPORT),

supporting eight stereo I
2 serial peripheral interface (SPI) compatible ports
1 UART with IrDA support
Parallel peripheral interface (PPI), supporting ITU-R 656

video data formats
2-wire interface (TWI) controller
9 peripheral DMAs
2 memory-to-memory DMA channels
Event handler with 28 interrupt inputs
32 general-purpose I/Os (GPIOs), with programmable

hysteresis
Debug/JTAG interface
On-chip PLL capable of frequency multiplication

2

S channels

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

Figure 1. Processor Block Diagram

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2011 Analog Devices, Inc. All rights reserved.

ADSP-BF592

TABLE OF CONTENTS

Features ................................................................. 1

Memory ................................................................ 1

Peripherals ............................................................. 1

General Description ................................................. 3

Portable Low Power Architecture ............................. 3

System Integration ................................................ 3

Blackfin Processor Core .......................................... 3

Memory Architecture ............................................ 5

Event Handling .................................................... 5

DMA Controllers .................................................. 6

Processor Peripherals ............................................. 6

Dynamic Power Management .................................. 8

Voltage Regulation ................................................ 9

Clock Signals ....................................................... 9

Booting Modes ................................................... 11

Instruction Set Description ................................... 12

Development Tools ............................................. 12

Designing an Emulator-Compatible

Processor Board (Target) ................................... 12

Related Documents .............................................. 12

Related Signal Chains ........................................... 12

Signal Descriptions ................................................. 13

Specifications ........................................................ 15

Operating Conditions ........................................... 15

Electrical Characteristics ....................................... 17

Absolute Maximum Ratings ................................... 19

ESD Sensitivity ................................................... 19

Package Information ............................................ 20

Timing Specifications ........................................... 21

Output Drive Currents ......................................... 35

Test Conditions .................................................. 36

Environmental Conditions .................................... 39

64-Lead LFCSP Lead Assignment ............................... 40

Outline Dimensions ................................................ 42

Automotive Products .............................................. 42

Ordering Guide ..................................................... 42

REVISION HISTORY

Rev. 0 to Rev. A

Added 200 MHz model to Electrical Characteristics ....... 17

Added 200 MHz model to Ordering Guide ................... 43

Rev. A | Page 2 of 44 | August 2011

GENERAL DESCRIPTION

ADSP-BF592

The ADSP-BF592 processor is a member of the Blackfin® family
of products, incorporating the Analog Devices/Intel Micro
Signal Architecture (MSA). Blackfin processors combine a dual­MAC state-of-the-art signal processing engine, the advantages
of a clean, orthogonal RISC-like microprocessor instruction set,
and single-instruction, multiple-data (SIMD) multimedia capa­bilities into a single instruction-set architecture.

The ADSP-BF592 processor is completely code compatible with
other Blackfin processors. The ADSP-BF592 processor offers
performance up to 400 MHz and reduced static power con­sumption. The processor features are shown in Table 1.

Table 1. Processor Features

Feature ADSP-BF592

Timer/Counters with PWM 3
SPORTs 2
SPIs 2
UART 1
Parallel Peripheral Interface 1
TWI 1
GPIOs 32

L1 Instruction SRAM 32K
L1 Instruction ROM 64K
L1 Data SRAM 32K
L1 Scratchpad SRAM 4K

Memory (bytes)

L3 Boot ROM 4K
Maximum Instruction Rate
Maximum System Clock Speed 100 MHz
Package Options 64-Lead LFCSP

1

Maximum instruction rate is not available with every possible SCLK selection.

1

400 MHz

By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program­mability, multimedia support, and leading-edge signal
processing in one integrated package.

PORTABLE LOW POWER ARCHITECTURE

Blackfin processors provide world-class power management
and performance. They are produced with a low power and low
voltage design methodology and feature on-chip dynamic
power management, which provides the ability to vary both the
voltage and frequency of operation to significantly lower overall
power consumption. This capability can result in a substantial
reduction in power consumption, compared with just varying
the frequency of operation. This allows longer battery life for
portable appliances.

head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing

SYSTEM INTEGRATION

The ADSP-BF592 processor is a highly integrated system-on-a­chip solution for the next generation of digital communication
and consumer multimedia applications. By combining industry
standard interfaces with a high performance signal processing
core, cost-effective applications can be developed quickly, with­out the need for costly external components. The system
peripherals include a watchdog timer; three 32-bit timers/coun­ters with PWM support; two dual-channel, full-duplex
synchronous serial ports (SPORTs); two serial peripheral inter­face (SPI) compatible ports; one UART

®

with IrDA support; a
parallel peripheral interface (PPI); and a 2-wire interface (TWI)
controller.

BLACKFIN PROCESSOR CORE

As shown in Figure 2, the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.

The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.

Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.

The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop­ulation count, modulo 2
and rounding, and sign/exponent detection. The set of video
instructions includes byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
The compare/select and vector search instructions are also
provided.

For certain instructions, two 16-bit ALU operations can be per­formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.

The program sequencer controls the flow of instruction execu­tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction) and
subroutine calls. Hardware is provided to support zero over

instructions with data dependencies.

32

multiply, divide primitives, saturation

Rev. A | Page 3 of 44 | August 2011

ADSP-BF592

SEQUENCER

ALIGN

DECODE

LOOP BUFFER

16

16

8888

40 40

A0 A1

BARREL
SHIFTER

DATA ARITHMETIC UNIT

CONTROL

UNIT

R7.H
R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R7.L
R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

AS TAT

40 40

32

32

32

32

32
32
32LD0

LD1

SD

DAG0

DAG1

ADDRESS ARITHMETIC UNIT

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

SP
FP

P5

P4
P3

P2

P1

P0

DA1

DA0

32

32

32

PREG

RAB

32

TO MEMORY

The address arithmetic unit provides two addresses for simulta­neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering) and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).

Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. Data memory holds data, and
a dedicated scratchpad data memory stores stack and local vari­able information.

Multiple L1 memory blocks are provided. The memory
management unit (MMU) provides memory protection for
individual tasks that may be operating on the core and can
protect system registers from unintended access.

The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.

The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc­tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc­tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.

The Blackfin processor assembly language uses an algebraic syn­tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.

Figure 2. Blackfin Processor Core

Rev. A | Page 4 of 44 | August 2011

ADSP-BF592

0x0000 0000

0xEF00 0000

0xFF80 0000

0xFF80 8000

0xFFA0 0000

0xFFA0 8000

0xFFA1 0000

0xFFA2 0000

0xFFB0 0000

0xFFB0 1000

0xFFC0 0000

0xFFE0 0000

BOOT ROM (4K BYTES)

RESERVED

L1 INSTRUCTION ROM (64K BYTES)

RESERVED

L1 SCRATCHPAD RAM (4K BYTES)

RESERVED

SYSTEM MEMORY MAPPED REGISTERS (2M BYTES)

CORE MEMORY MAPPED REGISTERS (2M BYTES)

RESERVED

DATA SRAM (32K BYTES)

RESERVED

L1 INSTRUCTION BANK B SRAM (16K BYTES)

RESERVED

0xEF00 1000

0xFFFF FFFF

L1 INSTRUCTION BANK A SRAM (16K BYTES)

0xFFA0 4000

MEMORY ARCHITECTURE

The Blackfin processor views memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory and I/O control registers, occupy
separate sections of this common address space. See Figure 3.

The core-accessible L1 memory system is high performance
internal memory that operates at the core clock frequency. The
external bus interface unit (EBIU) provides access to the boot
ROM.

The memory DMA controller provides high bandwidth data­movement capability. It can perform block transfers of code or
data between the L1 Instruction SRAM and L1 Data SRAM
memory spaces.

Custom ROM (Optional)

The on-chip L1 Instruction ROM on the ADSP-BF592 may be
customized to contain user code with the following features:

• 64K bytes of L1 Instruction ROM available for custom code

• Ability to restrict access to all or specific segments of the
on-chip ROM

Customers wishing to customize the on-chip ROM for their
own application needs should contact ADI sales for more infor­mation on terms and conditions and details on the technical
implementation.

I/O Memory Space

The processor does not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory-mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func­tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.

Booting from ROM

The processor contains a small on-chip boot kernel, which con­figures the appropriate peripheral for booting. If the processor is
configured to boot from boot ROM memory space, the proces­sor starts executing from the on-chip boot ROM. For more
information, see Booting Modes on Page 11.

Figure 3. Internal/External Memory Map

Internal (Core-Accessible) Memory

The processor has three blocks of core-accessible memory, pro­viding high bandwidth access to the core.

The first block is the L1 instruction memory, consisting of
32K bytes SRAM. This memory is accessed at full processor
speed.

The second core-accessible memory block is the L1 data mem­ory, consisting of 32K bytes. This memory block is accessed at
full processor speed.

The third memory block is a 4K byte L1 scratchpad SRAM,
which runs at the same speed as the other L1 memories.

L1 Utility ROM

The L1 instruction ROM contains utility ROM code. This
includes the TMK (VDK core), C run-time libraries, and DSP
libraries. See the VisualDSP++ documentation for more
information.

Rev. A | Page 5 of 44 | August 2011

EVENT HANDLING

The event controller on the processor handles all asynchronous
and synchronous events to the processor. The processor
provides event handling that supports both nesting and prioriti­zation. Nesting allows multiple event service routines to be
active simultaneously. Prioritization ensures that servicing of a
higher-priority event takes precedence over servicing of a lower­priority event. The controller provides support for five different
types of events:

• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.

• RESET

• Nonmaskable Interrupt (NMI) – The NMI event can be

– This event resets the processor.

generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut­down of the system.

ADSP-BF592

• Exceptions – Events that occur synchronously to program
flow (in other words, the exception is taken before the
instruction is allowed to complete). Conditions such as
data alignment violations and undefined instructions cause
exceptions.

• Interrupts – Events that occur asynchronously to program
flow. They are caused by input signals, timers, and other
peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.

The processor event controller consists of two stages: the core
event controller (CEC) and the system interrupt controller
(SIC). The core event controller works with the system interrupt
controller to prioritize and control all system events. Conceptu­ally, interrupts from the peripherals enter into the SIC and are
then routed directly into the general-purpose interrupts of the
CEC.

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the processor. The inputs to
the CEC, their names in the event vector table (EVT), and their
priorities are described in the ADSP-BF59x Blackfin Processor
Hardware Reference, “System Interrupts” chapter.

System Interrupt Controller (SIC)

The system interrupt controller provides the mapping and rout­ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processor provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writ­ing the appropriate values into the interrupt assignment
registers (SIC_IARx). The inputs into the SIC and the default
mappings into the CEC are described in the ADSP-BF59x Black-
fin Processor Hardware Reference, “System Interrupts” chapter.

The SIC allows further control of event processing by providing
three pairs of 32-bit interrupt control and status registers. Each
register contains a bit, corresponding to each peripheral inter­rupt event. For more information, see the ADSP-BF59x Blackfin
Processor Hardware Reference, “System Interrupts” chapter.

DMA CONTROLLERS

The processor has multiple, independent DMA channels that
support automated data transfers with minimal overhead for
the processor core. DMA transfers can occur between the pro­cessor’s internal memories and any of its DMA-capable
peripherals. DMA-capable peripherals include the SPORTs, SPI
ports, UART, and PPI. Each individual DMA-capable periph­eral has at least one dedicated DMA channel.

The processor DMA controller supports both one-dimensional
(1-D) and two-dimensional (2-D) DMA transfers. DMA trans­fer initialization can be implemented from registers or from sets
of parameters called descriptor blocks.

The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de­interleaved on the fly.

Examples of DMA types supported by the processor DMA con­troller include:

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page

In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels, which are provided for transfers
between the various memories of the processor system with
minimal processor intervention. Memory DMA transfers can be
controlled by a very flexible descriptor-based methodology or
by a standard register-based autobuffer mechanism.

PROCESSOR PERIPHERALS

The ADSP-BF592 processor contains a rich set of peripherals
connected to the core via several high bandwidth buses, provid­ing flexibility in system configuration, as well as excellent
overall system performance (see Figure 1). The processor also
contains dedicated communication modules and high speed
serial and parallel ports, an interrupt controller for flexible man­agement of interrupts from the on-chip peripherals or external
sources, and power management control functions to tailor the
performance and power characteristics of the processor and sys­tem to many application scenarios.

The SPORTs, SPIs, UART, and PPI peripherals are supported
by a flexible DMA structure. There are also separate memory
DMA channels dedicated to data transfers between the proces­sor’s various memory spaces, including boot ROM. Multiple
on-chip buses running at up to 100 MHz provide enough band­width to keep the processor core running along with activity on
all of the on-chip and external peripherals.

The ADSP-BF592 processor includes an interface to an off-chip
voltage regulator in support of the processor’s dynamic power
management capability.

Watchdog Timer

The processor includes a 32-bit timer that can be used to imple­ment a software watchdog function. A software watchdog can
improve system availability by forcing the processor to a known
state through generation of a hardware reset, nonmaskable
interrupt (NMI), or general-purpose interrupt, if the timer
expires before being reset by software. The programmer

Rev. A | Page 6 of 44 | August 2011

ADSP-BF592

initializes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must
reload the counter before it counts to zero from the pro­grammed value. This protects the system from remaining in an
unknown state where software, which would normally reset the
timer, has stopped running due to an external noise condition
or software error.

If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine whether the watchdog was the source of
the hardware reset by interrogating a status bit in the watchdog
timer control register.

The timer is clocked by the system clock (SCLK) at a maximum
frequency of f

SCLK

.

Timers

There are four general-purpose programmable timer units in
the processor. Three timers have an external pin that can be
configured either as a pulse width modulator (PWM) or timer
output, as an input to clock the timer, or as a mechanism for
measuring pulse widths and periods of external events. These
timers can be synchronized to an external clock input to the sev­eral other associated PF pins, to an external clock input to the
PPI_CLK input pin, or to the internal SCLK.

The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide a
software auto-baud detect function for the respective serial
channels.

The timers can generate interrupts to the processor core provid­ing periodic events for synchronization, either to the system
clock or to a count of external signals.

In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.

Serial Ports

The ADSP-BF592 processor incorporates two dual-channel
synchronous serial ports (SPORT0 and SPORT1) for serial and
multiprocessor communications. The SPORTs support the fol­lowing features:

Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA chan­nels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. In this configura­tion, one SPORT provides two transmit signals while the other
SPORT provides the two receive signals. The frame sync and
clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

2

S mode

•I

2

•Packed I

S mode

•Left-justified mode

Serial Peripheral Interface (SPI) Ports

The processor has two SPI-compatible ports that enable the
processor to communicate with multiple SPI-compatible
devices.

The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSI, and Master Input­Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI
chip select input pin (SPIx_SS

) lets other SPI devices select the
processor, and many SPI chip select output pins (SPIx_SEL7–1
let the processor select other SPI devices. The SPI select pins are
reconfigured general-purpose I/O pins. Using these pins, the
SPI port provides a full-duplex, synchronous serial interface,
which supports both master/slave modes and multimaster
environments.

UART Port

The ADSP-BF592 processor provides a full-duplex universal
asynchronous receiver/transmitter (UART) port, which is fully
compatible with PC-standard UARTs. The UART port provides
a simplified UART interface to other peripherals or hosts,
supporting full-duplex, DMA-supported, asynchronous trans­fers of serial data. The UART port includes support for five to
eight data bits, one or two stop bits, and none, even, or odd par­ity. The UART port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O mapped UART registers.
The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans­fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.

Parallel Peripheral Interface (PPI)

The processor provides a parallel peripheral interface (PPI) that
can connect directly to parallel analog-to-digital and digital-to­analog converters, video encoders and decoders, and other gen­eral-purpose peripherals. The PPI consists of a dedicated input
clock pin, up to three frame synchronization pins, and up to 16
data pins. The input clock supports parallel data rates up to half
the system clock rate, and the synchronization signals can be
configured as either inputs or outputs.

The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bidirectional data transfer with up to 16 bits of
data. Up to three frame synchronization signals are also pro­vided. In ITU-R 656 mode, the PPI provides half-duplex
bidirectional transfer of 8- or 10-bit video data. Additionally,
on-chip decode of embedded start-of-line (SOL) and start-of­field (SOF) preamble packets is supported.

)

Rev. A | Page 7 of 44 | August 2011

ADSP-BF592

General-Purpose Mode Descriptions

The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:

• Input mode – Frame syncs and data are inputs into the PPI.
Input mode is intended for ADC applications, as well as
video communication with hardware signaling.

• Frame capture mode – Frame syncs are outputs from the
PPI, but data are inputs. This mode allows the video
source(s) to act as a slave (for frame capture for example).

• Output mode – Frame syncs and data are outputs from the
PPI. Output mode is used for transmitting video or other
data with up to three output frame syncs.

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applica­tions. Three distinct submodes are supported:

• Active video only mode – Active video only mode is used
when only the active video portion of a field is of interest
and not any of the blanking intervals.

• Vertical blanking only mode – In this mode, the PPI only
transfers vertical blanking interval (VBI) data.

• Entire field mode – In this mode, the entire incoming bit
stream is read in through the PPI.

TWI Controller Interface

The processor includes a 2-wire interface (TWI) module for
providing a simple exchange method of control data between
multiple devices. The TWI is functionally compatible with the
widely used I
capabilities of simultaneous master and slave operation and
support for both 7-bit addressing and multimedia data arbitra­tion. The TWI interface utilizes two pins for transferring clock
(SCL) and data (SDA) and supports the protocol at speeds up to
400K bits/sec.

The TWI module is compatible with serial camera control bus
(SCCB) functionality for easier control of various CMOS cam­era sensor devices.

2

C® bus standard. The TWI module offers the

Ports

The processor groups the many peripheral signals to two
ports—Port F and Port G. Most of the associated pins are shared
by multiple signals. The ports function as multiplexer controls.

General-Purpose I/O (GPIO)

The processor has 32 bidirectional, general-purpose I/O (GPIO)
pins allocated across two separate GPIO modules—PORTFIO
and PORTGIO, associated with Port F and Port G respectively.
Each GPIO-capable pin shares functionality with other proces­sor peripherals via a multiplexing scheme; however, the GPIO
functionality is the default state of the device upon power-up.
Neither GPIO output nor input drivers are active by default.
Each general-purpose port pin can be individually controlled by
manipulation of the port control, status, and interrupt registers.

DYNAMIC POWER MANAGEMENT

The processor provides five operating modes, each with a differ­ent performance/power profile. In addition, dynamic power
management provides the control functions to dynamically alter
the processor core supply voltage, further reducing power dissi­pation. When configured for a 0 V core supply voltage, the
processor enters the hibernate state. Control of clocking to each
of the processor peripherals also reduces power consumption.
See Table 2 for a summary of the power settings for each mode.

Table 2. Power Settings

Core

PLL

Mode/State PLL

Full On Enabled No Enabled Enabled On
Active Enabled/

Disabled
Sleep Enabled — Disabled Enabled On
Deep Sleep Disabled — Disabled Disabled On
Hibernate Disabled — Disabled Disabled Off

Bypassed

Yes En ab le d En ab led O n

Clock
(CCLK)

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per­formance can be achieved. The processor core and all enabled
peripherals run at full speed.

Active Operating Mode—Moderate Dynamic Power Savings

In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. DMA
access is available to appropriately configured L1 memories.

For more information about PLL controls, see the “Dynamic
Power Management” chapter in the ADSP-BF59x Blackfin Pro-
cessor Hardware Reference.

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi­cally, an external event wakes up the processor.

System DMA access to L1 memory is not supported in
sleep mode.

Deep Sleep Operating Mode—Maximum Dynamic Power Savings

The deep sleep mode maximizes dynamic power savings by dis­abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals
may still be running but cannot access internal resources or
external memory. This powered-down mode can only be exited
by assertion of the reset interrupt (RESET
nous interrupt generated by a GPIO pin.

System
Clock
(SCLK)

) or by an asynchro-

Core
Power

Rev. A | Page 8 of 44 | August 2011

Note that when a GPIO pin is used to trigger wake from deep

Power Savings Factor

f

CCLKRED

f

CCLKNOM

--------------------

V

DDINTRED

V

DDINTNOM

------------------------





2

×

T

RED

T

NOM

------------





×





=

% Power Savings 1 Power Savings Factor–()100%×=

sleep, the programmed wake level must linger for at least 10ns
to guarantee detection.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling
clocks to the processor core (CCLK) and to all of the peripherals
(SCLK), as well as signaling an external voltage regulator that
V

can be shut off. Any critical information stored inter-

DDINT

nally (for example, memory contents, register contents, and
other information) must be written to a nonvolatile storage
device prior to removing power if the processor state is to be
preserved. Writing b#0 to the HIBERNATE

bit causes
EXT_WAKE to transition low, which can be used to signal an
external voltage regulator to shut down.

Since V

can still be supplied in this mode, all of the exter-

DDEXT

nal pins three-state, unless otherwise specified. This allows
other devices that may be connected to the processor to still
have power applied without drawing unwanted current.

As long as V

is applied, the VR_CTL register maintains its

DDEXT

state during hibernation. All other internal registers and memo­ries, however, lose their content in the hibernate state.

Power Savings

As shown in Table 3, the processor supports two different
power domains, which maximizes flexibility while maintaining
compliance with industry standards and conventions. By isolat­ing the internal logic of the processor into its own power
domain, separate from other I/O, the processor can take advan­tage of dynamic power management without affecting the other
I/O devices. There are no sequencing requirements for the
various power domains, but all domains must be powered
according to the appropriate Specifications table for processor
operating conditions, even if the feature/peripheral is not used.

Table 3. Power Domains

Power Domain VDD Range

All internal logic and memories V
All other I/O V

DDINT

DDEXT

The dynamic power management feature of the processor
allows both the processor’s input voltage (V
quency (f

) to be dynamically controlled.

CCLK

) and clock fre-

DDINT

The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation, while reducing the
voltage by 25% reduces dynamic power dissipation by more
than 40%. Further, these power savings are additive, in that if
the clock frequency and supply voltage are both reduced, the
power savings can be dramatic, as shown in the following
equations.

ADSP-BF592

where:

f

f

V

V

T

T

VOLTAGE REGULATION

The ADSP-BF592 processor requires an external voltage regula­tor to power the V
consumption, the external voltage regulator can be signaled
through EXT_WAKE to remove power from the processor core.
This signal is high-true for power-up and may be connected
directly to the low-true shut-down input of many common
regulators.

While in the hibernate state, the external supply, V
still be applied, eliminating the need for external buffers. The
external voltage regulator can be activated from this power­down state by asserting the RESET
boot sequence. EXT_WAKE indicates a wakeup to the external
voltage regulator.

The power good (PG
only after the internal voltage has reached a chosen level. In this
way, the startup time of the external regulator is detected after
hibernation. For a complete description of the power-good
functionality, refer to the ADSP-BF59x Blackfin Processor Hard-
ware Reference.

CLOCK SIGNALS

The processor can be clocked by an external crystal, a sine wave
input, or a buffered, shaped clock derived from an external
clock oscillator.

If an external clock is used, it should be a TTL-compatible signal
and must not be halted, changed, or operated below the speci­fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.

Alternatively, because the processor includes an on-chip oscilla­tor circuit, an external crystal may be used. For fundamental
frequency operation, use the circuit shown in Figure 4. A
parallel -resonant, fundamental frequency, microprocessor­grade crystal is connected across the CLKIN and XTAL pins.
The on-chip resistance between CLKIN and the XTAL pin is in

is the nominal core clock frequency

CCLKNOM

is the reduced core clock frequency

CCLKRED

DDINTNOM

DDINTRED

NOM

RED

is the nominal internal supply voltage

is the reduced internal supply voltage

is the duration running at f

is the duration running at f

domain. To reduce standby power

DDINT

) input signal allows the processor to start

CCLKNOM

CCLKRED

, can

DDEXT

pin, which then initiates a

Rev. A | Page 9 of 44 | August 2011

ADSP-BF592

CLKIN

CLKOUT (SCLK)

XTAL

SELECT

CLKBUF

TO PLL CIRCUITRY

FOR OVERTONE
OPERATION ONLY:

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀.

18 pF *

EN

18 pF *

330 ⍀ *

BLACKFIN

560 ⍀

EXTCLK

EN

PLL

5u

to 64u

÷ 1 to 15

÷ 1, 2, 4, 8

VCO

CLKIN

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

CCLK

SCLK

SCLK d CCLK

the 500 kΩ range. Further parallel resistors are typically not rec­ommended. The two capacitors and the series resistor shown in

Figure 4 fine tune phase and amplitude of the sine frequency.

The capacitor and resistor values shown in Figure 4 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.

Figure 5. Frequency Modification Methods

All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through

15. Table 4 illustrates typical system clock ratios.

Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of f

. The SSEL value can be

SCLK

changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).

The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 5. This programmable core clock capability is useful for

fast core frequency modifications.

Figure 4. External Crystal Connections

A third-overtone crystal can be used for frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 4. A design procedure for third-overtone oper­ation is discussed in detail in (EE-168) Using Third Overtone
Crystals with the ADSP-218x DSP on the Analog Devices web­site (www.analog.com)—use site search on “EE-168.”

The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 5, the core clock (CCLK) and
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable 5× to 64× multiplication
factor (bounded by specified minimum and maximum VCO
frequencies). The default multiplier is 6×, but it can be modified
by a software instruction sequence.

On-the-fly frequency changes can be effected by simply writing
to the PLL_DIV register. The maximum allowed CCLK and
SCLK rates depend on the applied voltages V
the VCO is always permitted to run up to the frequency speci­fied by the part’s instruction rate. The EXTCLK pin can be
configured to output either the SCLK frequency or the input
buffered CLKIN frequency, called CLKBUF. When configured
to output SCLK (CLKOUT), the EXTCLK pin acts as a refer­ence signal in many timing specifications. While three-stated by
default, it can be enabled using the VRCTL register.

DDINT

Table 5. Core Clock Ratios

Signal Name
CSEL1–0

00 1:1 300 300
01 2:1 300 150
10 4:1 400 100
11 8:1 200 25

Table 4. Example System Clock Ratios

Signal Name
SSEL3–0

0010 2:1 100 50
0110 6:1 300 50
1010 10:1 400 40

and V

DDEXT

;

The maximum CCLK frequency both depends on the part’s
instruction rate (see Page Page 43) and depends on the applied
V

voltage. See Table 8 for details. The maximal system

DDINT

clock rate (SCLK) depends on the chip package and the applied

and V

V

DDINT

Rev. A | Page 10 of 44 | August 2011

Divider Ratio
VCO/CCLK

Divider Ratio
VCO/SCLK

voltages (see Table 10).

DDEXT

Example Frequency Ratios

(MHz)

VCO CCLK

Example Frequency Ratios

(MHz)

VCO SCLK

ADSP-BF592

BOOTING MODES

The processor has several mechanisms (listed in Table 6) for
automatically loading internal and external memory after a
reset. The boot mode is defined by the BMODE input pins dedi­cated to this purpose. There are two categories of boot modes.
In master boot modes, the processor actively loads data from
parallel or serial memories. In slave boot modes, the processor
receives data from external host devices.

Table 6. Booting Modes

BMODE2–0 Description

000 Idle/No Boot
001 Reserved
010 SPI1 master boot from Flash, using SPI1_SSEL5
011 SPI1 slave boot from external master
100 SPI0 master boot from Flash, using SPI0_SSEL2
101 Boot from PPI port
110 Boot from UART host device
111 Execute from Internal L1 ROM

The boot modes listed in Table 6 provide a number of mecha­nisms for automatically loading the processor’s internal and
external memories after a reset. By default, all boot modes use
the slowest meaningful configuration settings. Default settings
can be altered via the initialization code feature at boot time.
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, imple­ment the modes shown in Table 6.

• IDLE State/No Boot (BMODE - 0x0) — In this mode, the
boot kernel transitions the processor into Idle state. The
processor can then be controlled through JTAG for recov­ery, debug, or other functions.

• SPI1 master boot from flash (BMODE = 0x2) — In this
mode, SPI1 is configured to operate in master mode and to
connect to 8-, 16-, 24-, or 32-bit addressable devices. The
processor uses the PG11/SPI1_SSEL5
EEPROM/flash device, submits a read command and suc­cessive address bytes (0×00) until a valid 8-, 16-, 24-, or 32­bit addressable device is detected, and begins clocking data
into the processor. Pull-up resistors are required on the
SSEL and MISO pins. By default, a value of 0×85 is written
to the SPI_BAUD register.

• SPI1 slave boot from external master (BMODE = 0x3) — In
this mode, SPI1 is configured to operate in slave mode and
to receive the bytes of the .LDR file from a SPI host (mas­ter) agent. To hold off the host device from transmitting
while the boot ROM is busy, the Blackfin processor asserts
a GPIO pin, called host wait (HWAIT), to signal to the host
device not to send any more bytes until the pin is deas­serted. The host must interrogate the HWAIT signal,
available on PG4, before transmitting every data unit to the
processor. A pull-up resistor is required on the SPI1_SS
input. A pull-down on the serial clock may improve signal
quality and booting robustness.

to select a single SPI

on PG11

on PF8

• SPI0 master boot from flash (BMODE = 0x4) — In this
mode SPI0 is configured to operate in master mode and to
connect to 8-, 16-, 24-, or 32-bit addressable devices. The
processor uses the PF8/SPI0_SSEL2
EEPROM/flash device, submits a read command and suc­cessive address bytes (0×00) until a valid 8-, 16-, 24-, or 32­bit addressable device is detected, and begins clocking data
into the processor. Pull-up resistors are required on the
SSEL and MISO pins. By default, a value of 0×85 is written
to the SPI_BAUD register.

• Boot from PPI host device (BMODE = 0x5) — The proces­sor operates in PPI slave mode and is configured to receive
the bytes of the LDR file from a PPI host (master) agent.

• Boot from UART host device (BMODE = 0x6) — In this
mode UART0 is used as the booting source. Using an auto­baud handshake sequence, a boot-stream formatted
program is downloaded by the host. The host selects a bit
rate within the UART clocking capabilities. When per­forming the autobaud, the UART expects a “@” (0×40)
character (eight bits data, one start bit, one stop bit, no par­ity bit) on the RXD pin to determine the bit rate. The
UART then replies with an acknowledgment which is com­posed of 4 bytes (0xBF—the value of UART_DLL) and
(0×00—the value of UART_DLH). The host can then
download the boot stream. To hold off the host the proces­sor signals the host with the boot host wait (HWAIT)
signal. Therefore, the host must monitor the HWAIT, (on
PG4), before every transmitted byte.

• Execute from internal L1 ROM (BMODE = 0x7) — In this
mode the processor begins execution from the on-chip 64k
byte L1 instruction ROM starting at address 0xFFA1 0000.

For each of the boot modes (except Execute from internal L1
ROM), a 16 byte header is first brought in from an external
device. The header specifies the number of bytes to be trans­ferred and the memory destination address. Multiple memory
blocks may be loaded by any boot sequence. Once all blocks are
loaded, program execution commences from the start of L1
instruction SRAM.

The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in the
latter case. Bits 7–4 in the system reset configuration (SYSCR)
register can be used to bypass the boot kernel or simulate a
wakeup-from-hibernate boot in case of a software reset.

The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to speed up
booting by managing the PLL, clock frequencies, or serial bit
rates.

The boot ROM also features C-callable functions that can be
called by the user application at run time. This enables second
stage boot or boot management schemes to be implemented
with ease.

to select a single SPI

Rev. A | Page 11 of 44 | August 2011

ADSP-BF592

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro­vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro­grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com­piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera­tion, allowing multiple levels of access to core
processor resources.

The assembly language, which takes advantage of the proces­sor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.

• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program­ming model.

• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.

• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.

DEVELOPMENT TOOLS

The processor is supported with a complete set of
CROSSCORE® software and hardware development tools,
including Analog Devices emulators and VisualDSP++® devel­opment environment. The same emulator hardware that
supports other Blackfin processors also fully emulates the
ADSP-BF592 processor.

EZ-KIT Lite® Evaluation Board

For evaluation of the ADSP-BF592 processor, use the EZ-KIT
Lite boards soon to be available from Analog Devices. When
these evaluation kits are available, order using part number
ADZS-BF592-EZLITE. The boards come with on-chip emula­tion capabilities and are equipped to enable software
development. Multiple daughter cards will be available.

DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD (TARGET)

The Analog Devices family of emulators are tools that every sys­tem developer needs in order to test and debug hardware and
software systems. Analog Devices has supplied an IEEE 1149.1

JTAG Test Access Port (TAP) on each JTAG processor. The
emulator uses the TAP to access the internal features of the pro­cessor, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers. The
processor must be halted to send data and commands, but once
an operation has been completed by the emulator, the processor
system is set running at full speed with no impact on
system timing.

To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see (EE-68) Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.

RELATED DOCUMENTS

The following publications that describe the ADSP-BF592 pro­cessor (and related processors) can be ordered from any Analog
Devices sales office or accessed electronically on our website:

• Getting Started With Blackfin Processors

• ADSP-BF59x Blackfin Processor Hardware Reference

• Blackfin Processor Programming Reference

• ADSP-BF592 Blackfin Processor Anomaly List

RELATED SIGNAL CHAINS

A signal chain is a series of signal conditioning electronic com-
ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the

www.analog.com website.

The Circuits from the Lab
provides:

• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection
guides and application information

• Reference designs applying best practice design techniques

TM

site (www.analog.com\circuits)

Rev. A | Page 12 of 44 | August 2011

SIGNAL DESCRIPTIONS

ADSP-BF592

Signal definitions for the ADSP-BF592 processor are listed in

Table 7. In order to maintain maximum function and reduce

package size and pin count, some pins have dual, multiplexed
functions. In cases where pin function is reconfigurable, the
default state is shown in plain text, while the alternate function
is shown in italics.

All pins are three-stated during and immediately after reset,

All I/O pins have their input buffers disabled with the exception
of the pins that need pull-ups or pull-downs, as noted in

Table 7.

Adding a parallel termination to EXTCLK may prove useful in
further enhancing signal integrity. Be sure to verify over­shoot/undershoot and signal integrity specifications on actual
hardware.

with the exception of EXTCLK, which toggles at the system
clock rate.

Table 7. Signal Descriptions

Driver

Signal Name Type Function

Port F: GPIO and Multiplexed Peripherals

PF0–GPIO/DR1SEC/PPI_D8/WAK EN1 I/O GPIO/SPORT1 Receive Data Secondary/PPI Data 8/Wake Ena ble 1 A
PF1–GPIO/DR1PRI/PPI_D9 I/O GPIO/SPORT1 Receive Data Primary/PPI Data 9 A
PF2–GPIO/RSCLK1/PPI_D10 I/O GPIO/SPORT1 Receive Serial Clock/PPI Data 10 A
PF3–GPIO/RFS1/PPI_D11 I/O GPIO/SPORT1 Receive Frame Sync/PPI Data 11 A
PF4–GPIO/DT1 SEC/PPI_D12 I/O GPIO/SPORT1 Transmit Data Secondary/PPI Data 12 A
PF5–GPIO/DT1 PRI/PPI_D13 I/O GPIO/SPORT1 Transmit Data Primary/PPI Data 13 A
PF6–GPIO/TSCLK1/PPI_D14 I/O GPIO/SPORT1 Transmit Serial Clock/PPI Data 14 A
PF7–GPIO/TFS1/PPI_D15 I/O GPIO/SPORT1 Transmit Frame Sync/PPI Data 15 A
PF8–GPIO/TMR2/SPI0_SSEL2
PF9–GPIO/TMR0/PPI_FS1/SPI0_SSEL3
PF10–GPIO/TMR1/PPI_FS2 I/O GPIO/Timer 1/PPI Frame Sync 2 A
PF11–GPIO/UA_TX/SPI0_SSEL4
PF12–GPIO/UA_RX/SPI0_SSEL7

PF13–GPIO/SPI0_MOSI/SPI1_SSEL3
PF14–GPIO/SPI0_MISO/SPI1_SSEL4

PF15–GPIO/SPI0_SCK/SPI1_SSEL5

Port G: GPIO and Multiplexed Peripherals

PG0–GPIO/DR0SEC/SPI0_SSEL1

PG1–GPIO/DR0PRI/SPI1_SSEL1/WAK EN3 I/O GPIO/SPORT0 Receive Data Primary/SPI1 Slave Select Enable 1/Wake Enable 3 A
PG2–GPIO/RSCLK0/SPI0_SSEL5
PG3–GPIO/RFS0/PPI_FS3 I/O GPIO/SPORT0 Receive Frame Sync/PPI Frame Sync 3 A
PG4–GPIO(HWAIT)/DT 0SEC/SPI0_SSEL6

PG5–GPIO/DT0PR I/SPI1_SSEL6
PG6–GPIO/TSCLK0 I/O GPIO/SPORT0 Transmit Serial Clock A
PG7–GPIO/TFS0/SPI1_SSEL7
PG8–GPIO/SPI1_SCK/PPI_D0 I/O GPIO/SPI1 Clock/PPI Data 0 A
PG9–GPIO/SPI1_MOSI/PPI_D1 I/O GPIO/SPI1 Master Out Slave In/PPI Data 1 A
PG10–GPIO/SPI1_MISO/PPI_D2 I/O GPIO/SPI1 Master In Slave Out/PPI Data 2

/WAK EN0 I/O GPIO/Timer 2/SPI0 Slave Select Enable 2/Wake Enable 0 A

I/O GPIO/Timer 0/PPI Frame Sync 1/SPI0 Slave Select Enable 3 A

I/O GPIO/UART Transmit/SPI0 Slave Select Enable 4 A

/TACI2–0 I/O GPIO/UART Receive/SPI0 Slave Select Enable 7/Timers 2–0 Alternate Input

Capture

I/O GPIO/SPI0 Master Out Slave In/SPI1 Slave Select Enable 3 A

I/O GPIO/SPI0 Master In Slave Out/SPI1 Slave Select Enable 4

(This pin should always be pulled high through a 4.7 k resistor,
if booting via the SPI port.)

I/O GPIO/SPI0 Clock/SPI1 Slave Select Enable 5 A

/SPI0_SS I/O GPIO/SPORT0 Receive Data Secondary/SPI0 Slave Select Enable 1/SPI0 Slave

Select Input

I/O GPIO/SPORT0 Receive Serial Clock/SPI0 Slave Select Enable 5 A

I/O GPIO (HWAIT output for Slave Boot Modes)/SPORT0 Transmit Data

Secondary/SPI0 Slave Select Enable 6

I/O GPIO/SPORT0 Transmit Data Primary/SPI1 Slave Select Enable 6 A

I/O GPIO/SPORT0 Transmit Frame Sync/SPI1 Slave Select Enable 7 A

(This pin should always be pulled high through a 4.7 k resistor if booting via
the SPI port.)

Typ e

A

A

A

A

A

Rev. A | Page 13 of 44 | August 2011

ADSP-BF592

Table 7. Signal Descriptions (Continued)

Signal Name Type Function

PG11–GPIO/SPI1_SSEL5/PPI_D3 I/O GPIO/SPI1 Slave Select Enable 5/PPI Data 3 A
PG12–GPIO/SPI1_SSEL2
PG13–GPIO/SPI1_SSEL1
PG14–GPIO/SPI1_SSEL4
PG15–GPIO/SPI1_SSEL6

TWI

SCL I/O TWI Serial Clock (This signal is an open-drain output and requires a pull-up

SDA I/O TWI Serial Data (This signal is an open-drain output and requires a pull-up

JTAG Port

TCK I JTAG CLK
TDO O JTAG Serial Data Out A
TDI I JTAG Serial Data In
TMS I JTAG Mode Select
TRST

EMU

Clock

CLKIN I CLK/Crystal In
XTAL O Crystal Output
EXTCLK O External Clock Output pin/System Clock Output C

Mode Controls

RESET
NMI

BMODE2–0 I Boot Mode Strap 2–0
PPI_CLK I PPI Clock Input

External Regulator Control

PG
EXT_WAKE O Wake up Indication A

Power Supplies ALL SUPPLIES MUST BE POWERED

V

DDEXT

V

DDINT

GND G Ground for All Supplies (Back Side of LFCSP Package.)

/PPI_D4/WAK EN2 I/O GPIO/SPI1 Slave Select Enable 2 Output/PPI Data 4/Wake E nabl e 2 A
/SPI1_SS/PPI_D5 I/O GPIO/SPI1 Slave Select Enable 1 Output/PPI Data 5/SPI1 Slave Select Input A
/PPI_D6/TACLK1 I/O GPIO/SPI1 Slave Select Enable 4/PPI Data 6/Timer 1 Auxiliary Clock Input A
/PPI_D7/TACLK2 I/O GPIO/SPI1 Slave Select Enable 6/PPI Data 7/Timer 2 Auxiliary Clock Input A

resistor. Consult version 2.1 of the I

2

C specification for the proper resistor

value.)

2

resistor. Consult version 2.1 of the I

C specification for the proper resistor

value.)

IJTAGReset

(This lead should be pulled low if the JTAG port is not used.)

O Emulation Output

I Reset
I Nonmaskable Interrupt

(Thisleadshouldbepulledhighwhennotused.)

I Power Good indication

See Operating Conditions on Page 15.
PI/OPowerSupply
P Internal Power Supply

Driver

Typ e

B

B

A

Rev. A | Page 14 of 44 | August 2011