ANALOG DEVICES ADSP-BF561 Service Manual

Engineer-to-Engineer Note EE-256

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Using the ADSP-BF561 Blackfin® Processor as a TFT-LCD Controller

Contributed by C. Lam Rev 2 – March 7, 2006

Introduction

The ADSP-BF561 Blackfin® processor has two
parallel peripheral interfaces (PPIs) that enable
video to be simultaneously input and output from
the device. The PPI can interface to video
decoders that convert standard analog television
signals, compatible with NTSC and PAL
standards, into 4:2:2 component video data. The
PPI can also directly connect to several TFT
LCD panels that accept RGB video data. This
EE-Note describes the hardware and software
requirements necessary to develop a video
application that simultaneously streams data to
the ADSP-BF561 Blackfin processor and
displays it on a LCD panel with a RGB interface.

Hardware Interface

The following hardware was used in this
implementation of the application:

 ADSP-BF561 EZ-KIT Lite® board
 Logic Product Development Zoom Display

Kit (with Sharp LQ035Q7DB02 LCD Panel)

 Input video source (DVD player, video

camera, or any other input video source that
outputs signals compatible with NTSC
standards)

The selection of this Sharp LCD panel is
arbitrary. This particular LCD panel is very
popular in PDA applications and has a “low level
interface,” which means most of the drive
electronics normally implemented in the LCD

module have been removed. Removing these
electronic components from the module saves
both cost and space. Because the drive
electronics are not integrated in the LCD module,
an additional timing ASIC is usually needed to
generate the specific timing signals required for
the row and column drivers.

However, because the ADSP-BF561

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processor provides many general­purpose PWM timers, it can be
configured to provide the proper LCD
timing, thus eliminating the need for the
external timing ASIC.

To simplify the development process, Logic
Product Development produces an evaluation
module for this particular Sharp LCD panel,
called the Zoom Display Kit (ZDK). In this
application, the EZ-KIT Lite board interfaces
directly to the ZDK.

A DVD player serves as the video input source
for this application. The S-Video output of the
DVD player connects to the RCA video input
jack (J6) on the EZ-KIT Lite board.

Figure 1 in the Appendix shows a block diagram

of the hardware connections between the ADSP­BF561 processor, the input video source, and the
output display panel. Figure 2 shows the pin
interface between the ADSP-BF561 processor
and the LCD panel.

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Software Interface

The software interface consists of three main
parts:

 Receiving the input data
 Processing the input data
 Transmitting the processed data

The dual-core ADSP-BF561 Blackfin processor
has 32 KB of L1 instruction memory SRAM
available for each core. In partitioning the
software components, we choose to have Core A
handle the DMA of the input data and Core B
handle the core processing and DMA of the
output data. In this scheme, Core A is unused for
any core processing and is available for
additional tasks, if necessary.

Figure 3 in the Appendix shows a block diagram

of the software flow: receiving the input video
data, processing and formatting the data, and
sending the data out to be displayed.

Receiving the Input Data

Configuring the processor to receive the input
data requires setting up input source buffers in
SDRAM memory, configuring the DMA
channel, and configuring the PPI port. Because
the EZ-KIT Lite design maps the video decoder
to PPI0, this port is designated to be used for
video input.

Source Buffers in SDRAM Memory

There are two source buffers in SDRAM
memory defined to receive the incoming data.
Having two buffers allows time for processing of
the first buffer while simultaneously receiving
data from the next video frame.

controller 1, channel 0 by default, this channel
must be configured to transfer the data from
PPI0’s port to the SDRAM source buffers.

Because there are two source buffers to fill with
the incoming data, the small model descriptor list
is the DMA mode of choice. This mode instructs
the DMA channel to transfer data to the first
buffer and then continue to fill the second buffer
upon completion of the first.

This mode requires both setting up descriptors in
memory and writing directly to memory-mapped
registers (MMRs). The following registers are
written directly:

 X and Y count registers: these registers

specify the number of words to transfer. The
word size can be 8, 16, or 32 bits, configured
by writing the WDSIZE bits in the
configuration register. In this application, the
input frame size is 1716 bytes * 525 lines.
Since the word size used is 32 bits, the X
count register is set to 429 (1716/4), and the
Y count register is set to 525.

 X and Y modify registers: these registers

specify the number of bytes to modify after
reading in a word. Since the word size used is
32 bits, the number of bytes to modify after
each read is 4 (32 bits = 4 bytes).

 Next descriptor pointer register: this register

contains the address of the next descriptor
location to load after the data transfers
specified by current descriptor have been
processed. As soon as the DMA channel is
enabled, it will read from the next descriptor
pointer register, get the address of the next
descriptor, and fetch the DMA elements from
the descriptor. In this application, the next
descriptor pointer register is assigned the
address of the first receive descriptor.

Direct Memory Access (DMA)

There are two peripheral DMA controllers on the
ADSP-BF561 processor. Each DMA controller
has a set of channels linked to different
peripherals. Since PPI0 is linked to DMA

Using the ADSP-BF561 Blackfin® Processor as a TFT-LCD Controller (EE-256) Page 2 of 10

 Configuration register: this register contains

all the parameters and operating modes. In
this register, we define the DMA mode to be
small model descriptor list, word size to be
32 bits, descriptor size (number of elements

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in each descriptor) to be 4, DMA direction to
receive data, and interrupts to be enabled.

The receive descriptors are set up in L1 Data
Bank A memory. There are two descriptors, one
for each input source buffer. As described in the
descriptor size of the configuration register, there
are four elements in each descriptor. These
elements define the next descriptor pointer
location, the lower 16 bits of the receive buffer’s
starting address, the upper 16 bits of the receive
buffer’s starting address, and the DMA
configuration value. The first descriptor points to
the second descriptor, and the second descriptor
points to the first descriptor. This creates a loop
for the receive DMA to fill the first source
buffer, then the second source buffer, and then
repeat continuously.

Figure 4 in the Appendix shows a diagram of the

receive DMA descriptors and how they are
linked.

Parallel Peripheral Interface 0 (PPI0)

The PPI provides a parallel interface to the video
decoder. After the decoder digitizes the incoming
analog, NTSC, or PAL signal, it outputs a
parallel 8- or 16-bit data stream. The PPI
receives this data in ITU-R 656 format.

Processing the Input Data

Once the first receive DMA completes, it
generates an interrupt. In the interrupt service
routine, a flag is set to indicate that the first input
source buffer has been filled and is ready to be
processed. The processing contains two routines:

 Decimation and de-interlacing
 Color space conversion and formatting

Decimation and De-interlacing

The input video source is an NTSC-compatible
DVD player. An NTSC active video frame size
dimensions of 720 words/line * 480 lines/frame
and contains two fields/frame. All of Field 1’s
data (odd lines) is received first, followed by all
of Field 2’s data (even lines). However, typical
LCD panels require a progressive data format, in
which line one of Field 1 is followed by line one
of Field 2, followed by line two of Field 1, and
so on. The LCD panel used in this application
has dimensions of 240 words/line * 320
lines/frame and requires a progressive data
format.

The decimation and de-interlacing routine
resolves the issues of the two different frame
sizes and data arrangements.

The registers necessary to configure the PPI to
receive data from the decoder are:

 Frame register: this register holds the number

of lines that make up a frame. If the
programmed value in this register does not
match the actual received lines, the frame
track error (FT_ERR) bit is set in the PPI
status register. In this particular application,
the value programmed in this register is 525.

 Control register: this register sets the PPI

parameters and operating modes. Through
this register, the PPI is configured to receive
data in ITU-R 656 mode, with a data length
of eight bits.

Using the ADSP-BF561 Blackfin® Processor as a TFT-LCD Controller (EE-256) Page 3 of 10

Figure 5 in the Appendix shows a diagram of the

data arrangement of interlaced and non­interlaced data.

Color Space Conversion

When the DVD player outputs an analog signal
to the video decoder, the video decoder, in turn,
outputs YCbCr component video data. These
components represent the luminance and
chrominance of the pixels. Because this LCD
panel accepts data in RGB components, a color
space conversion process is necessary.

The color space conversion routine converts the
YCbCr components to RGB components using
the following standard equations: