Analog Devices ADSP BF531 2 3 a Datasheet

Blackfin

ADSP-BF531/ADSP-BF532/ADSP-BF533

FEATURES

Up to 600 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of pro-

gramming and compiler-friendly support

Advanced debug, trace, and performance monitoring

0.8 V to 1.2 V core V

3.3 V and 2.5 V tolerant I/O 160-ball mini-BGA, 169-ball lead free PBGA, and 176-lead

LQFP packages

MEMORY

Up to 148K bytes of on-chip memory:

16K bytes of instruction SRAM/Cache 64K bytes of instruction SRAM 32K bytes of data SRAM/Cache 32K bytes of data SRAM

4K bytes of scratchpad SRAM Two dual-channel memory DMA controllers Memory management unit providing memory protection

with on-chip voltage regulation

Embedded Processor

External memory controller with glueless support for

SDRAM, SRAM, FLASH, and ROM

Flexible memory booting options from SPI and external

memory

PERIPHERALS

Parallel peripheral interface (PPI)/GPIO, supporting

ITU-R 656 video data formats

Two dual-channel, full duplex synchronous serial ports, sup-

porting eight stereo I 12-channel DMA controller SPI-compatible port Three timer/counters with PWM support UART with support for IrDA Event handler Real-time clock Watchdog timer Debug/JTAG interface On-chip PLL capable of 1x to 63x frequency multiplication Core timer

S channels

JTAG TEST AND

EMULATION

VOLTAGE

REGULATOR

INSTRUCTION

MEMORY

CORE/SYSTEM BUS INTERFACE

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

EVENT

CONTROLLER/

CORE TIMER

MMU

CONTROLLER

BOOT ROM

Figure 1. Functional Block Diagram

DMA

WATCHDOG TIMER

REAL-TIME CLOCK

UART PORT

IRDA

DATA

MEMORY

TIMER0, TIMER1,

TIMER2

PPI / GPIO

SERIAL PORTS (2)

SPI PORT

EXTERNAL PORT

FLASH, SDRAM

CONTROL

ADSP-BF531/ADSP-BF532/ADSP-BF533

General Description ................................................. 3

Portable Low Power Architecture ............................. 3

System Integration ................................................ 3

ADSP-BF531/ADSP-BF532/ADSP-BF533 Processor

Peripherals ....................................................... 3

Blackfin Processor Core .......................................... 3

DMA Controllers .................................................. 8

Real-Time Clock ................................................... 8

Watchdog Timer .................................................. 9

Timers ............................................................... 9

Serial Ports (SPORTs) ............................................ 9

Serial Peripheral Interface (SPI) Port ......................... 9

UART Port ........................................................ 10

Programmable Flags (PFx) .................................... 10

Parallel Peripheral Interface ................................... 10

Dynamic Power Management ................................ 11

Voltage Regulation .............................................. 12

Clock Signals ..................................................... 13

Booting Modes ................................................... 13

Instruction Set Description ................................... 14

Development Tools ............................................. 14

Designing an Emulator-Compatible Processor Board .. 15

Pin Descriptions .................................................... 16

Specifications ........................................................ 19

Recommended Operating Conditions ...................... 19

Electrical Characteristics ....................................... 19

Absolute Maximum Ratings .................................. 20

ESD Sensitivity ................................................... 20

Timing Specifications .......................................... 21

Clock and Reset Timing .................................... 22

Asynchronous Memory Read Cycle Timing ........... 23

Asynchronous Memory Write Cycle Timing .......... 24

SDRAM Interface Timing .................................. 25

External Port Bus Request and Grant Cycle Timing .. 26

Parallel Peripheral Interface Timing ..................... 27

Serial Ports ..................................................... 28

Serial Peripheral Interface (SPI) Port

—Master Timing .......................................... 32

Serial Peripheral Interface (SPI) Port

—Slave Timing ............................................. 33

Universal Asynchronous Receiver-Transmitter

(UART) Port—Receive and Transmit Timing ...... 34

Programmable Flags Cycle Timing ....................... 35

Timer Cycle Timing .......................................... 36

JTAG Test and Emulation Port Timing .................. 37

Output Drive Currents ......................................... 38

Power Dissipation ............................................... 40

Test Conditions .................................................. 41

Environmental Conditions .................................... 44

160-Lead BGA Pinout ............................................. 45

169-Ball PBGA Pinout ............................................. 48

176-Lead LQFP Pinout ............................................ 50

Outline Dimensions ................................................ 52

Ordering Guide ..................................................... 55

REVISION HISTORY

1/05—Revision A: Changed from Rev. 0 to Rev. A

Deleted tolerance from voltage regulator description and

changed part in (Figure 7) Voltage Regulator Circuit........12

Defined new nominal voltage for ADSP-BF533 in Recom-

mended Operating Conditions....................................19

Clarified test voltage in Table 10, Table 11, Table12 .........21

Changed data for 400 MHz in (Table 30) Internal Power Dissi-

pation ...................................................................40

Changed package height in (Figure 46) 160-Ball Mini-BGA

(BC-160)................................................................52

Changed operating voltage for ADSP-BF532 and ADSP-BF533

parts and adds two part numbers to Ordering Guide.........55

Changes to format throughout document.

3/04—Revision 0: Initial Version

Rev. A | Page 2 of 56 | January 2005

GENERAL DESCRIPTION

ADSP-BF531/ADSP-BF532/ADSP-BF533

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISClike microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction set architecture.

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are completely code and pin compatible, differing only with respect to their performance and on-chip memory. Specific performance and memory configurations are shown in Table 1.

Table 1. Processor Comparison

ADSP-BF531 ADSP-BF532 ADSP-BF533

Maximum Performance

Instruction SRAM/Cache

Instruction SRAM

Data SRAM/Cache

Data SRAM 32K bytes Scratchpad 4K bytes 4K bytes 4K bytes

By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package.

400 MHz 800 MMACs

16K bytes 16K bytes 16K bytes

16K bytes 32K bytes 64K bytes

16K bytes 32K bytes 32K bytes

400 MHz 800 MMACs

600 MHz 1200 MMACs

PORTABLE LOW POWER ARCHITECTURE

Blackfin processors provide world-class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This translates into longer battery life for portable appliances.

SYSTEM INTEGRATION

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are highly integrated system-on-a-chip solutions for the next generation of digital communication and consumer multimedia applications. By combining industry-standard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The system peripherals include a UART port, an SPI port, two serial ports (SPORTs), four general-purpose timers (three with PWM capability), a real-time clock, a watchdog timer, and a parallel peripheral interface.

ADSP-BF531/ADSP-BF532/ADSP-BF533 PROCESSOR PERIPHERALS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor contains a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see the functional block diagram in Figure 1 on Page 1). The general- purpose peripherals include functions such as UART, timers with PWM (pulse width modulation) and pulse measurement capability, general-purpose flag I/O pins, a real-time clock, and a watchdog timer. This set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the part. In addition to these generalpurpose peripherals, the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor contains high speed serial and parallel ports for interfacing to a variety of audio, video, and modem codec functions; an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources; and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios.

All of the peripherals, except for general-purpose I/O, real-time clock, and timers, are supported by a flexible DMA structure. There is also a separate memory DMA channel dedicated to data transfers between the processor’s various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals.

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor includes an on-chip voltage regulator in support of the ADSPBF531/ADSP-BF532/ADSP-BF533 processor dynamic power management capability. The voltage regulator provides a range of core voltage levels from a single 2.25 V to 3.6 V input. The voltage regulator can be bypassed at the user’s discretion.

BLACKFIN PROCESSOR CORE

As shown in Figure 2 on Page 5, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register file.

The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields.

Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported.

The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing

Rev. A | Page 3 of 56 | January 2005

ADSP-BF531/ADSP-BF532/ADSP-BF533

tasks. These include bit operations such as field extract and population count, modulo 2 saturation and rounding, and sign/exponent detection. The set of video instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions.

For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). By also using the second ALU, quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions.

The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies.

The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation).

Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information.

In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access.

The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources.

The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle.

multiply, divide primitives,

The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip memory as cache or SRAM, and larger, lower cost and performance off-chip memory systems. See Figure 3 on Page 5,

Figure 4 on Page 5, and Figure 5 on Page 6.

The L1 memory system is the primary highest performance memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical memory.

The memory DMA controller provides high bandwidth datamovement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces.

Internal (On-Chip) Memory

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has three blocks of on-chip memory providing high bandwidth access to the core.

The first is the L1 instruction memory, consisting of up to 80K bytes SRAM, of which 16K bytes can be configured as a four way set-associative cache. This memory is accessed at full processor speed.

The second on-chip memory block is the L1 data memory, consisting of up to two banks of up to 32K bytes each. Each memory bank is configurable, offering both cache and SRAM functionality. This memory block is accessed at full processor speed.

The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory.

External (Off-Chip) Memory

The external bus interface can be used with both asynchronous devices such as SRAM, FLASH, EEPROM, ROM, and I/O devices, and synchronous devices such as SDRAMs. The bus width is always 16 bits. A1 is the least significant address of a 16bit word. 8-bit peripherals should be addressed as if they were 16-bit devices, where only the lower eight bits of data should be used.

Rev. A | Page 4 of 56 | January 2005

LD032BITS

LD132BITS

SD 3 2 BI TS

R7 R6 R5 R4 R3

R2 R1

R7.H R6.H R5.H R4.H R3.H

R2.H R1.H

R0.H

ADSP-BF531/ADSP-BF532/ADSP-BF533

ADDRESS ARITHMETIC UNIT

SP FP P5 P4 P3 P2 P1 P0

R7.L R6.L R5.L R4.L R3.L

R2.L R1.L

R0.L

I3 I2 I1 I0

BARREL SHIF TER

B3 L2 L1 L0

A0 A1

88 8 8

40 40

DAG0 DA G 1

SEQUENCER

ALIGN

DECODE

LOOP BUFFER

CONTROL

UN IT

0xFFFF FFFF

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF90 0000

0xFF80 8000

0xFF80 4000

0xFF80 0000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

CORE MMR REGISTERS (2M BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

RESERVED

INSTRUCTION SRAM/CACHE (16K BYTE)

INSTRUCTION SRAM (64K BYTE)

RESERVED

DATA BANK B SRAM/CACHE (16K BYTE)

DATA BANK B SRAM (16K BYTE)

RESERVED

DATA BANK A SRAM/CACHE (16K BYTE)

DATA BANK A SRAM (16K BYTE)

RESERVED

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

RESERVED

SDRAM MEMORY (16M BYTE TO 128M BYTE)

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

0xFFFF FFFF

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

P A M

Y R O M E M L A N R E T N

P A M

Y R O M E M L A N R E T X E

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 8000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

CORE MMR REGISTERS (2M BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

RESERVED

INSTRUCTION SRAM/CACHE (16K BYTE)

INSTRUCTION SRAM (32K BYTE)

RESERVED

DATA BANK B SRAM/CACHE (16K BYTE)

RESERVED

DATA BANK A SRAM/CACHE (16K BYTE)

RESERVED

ASYNC MEMORY BANK 3 (1M BYT E)

ASYNC MEMORY BANK 2 (1M BYT E)

ASYNC MEMORY BANK 1 (1M BYT E)

ASYNC MEMORY BANK 0 (1M BYT E)

RESERVED

SDRAM MEMORY (16M BYTE TO 128M BYTE)

P A M

Y R O M E M

L A N R E T N

P A M

Y R O M E M L A N R E T X E

Figure 3. ADSP-BF533 Internal/External Memory Map

Rev. A | Page 5 of 56 | January 2005

Figure 4. ADSP-BF532 Internal/External Memory Map

ADSP-BF531/ADSP-BF532/ADSP-BF533

0xFFFF FFFF

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 C000

0xFFA0 8000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

Figure 5. ADSP-BF531 Internal/External Memory Map

The PC133-compliant SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. The SDRAM controller allows one row to be open for each internal SDRAM bank, for up to four internal SDRAM banks, improving overall system performance.

The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks will only be contiguous if each is fully populated with 1M byte of memory.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one of which contains the control MMRs for all core functions, and the other of which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals.

CORE MMR REGISTERS (2M BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

RESERVED

INSTRUCTION SRAM/CACHE (16K BYTE)

RESERVED

INSTRUCTION SRAM (16K BYTE)

RESERVED

DATA BANK A SRAM/CACHE (16K BYTE)

RESERVED

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

RESERVED

SDRAM MEMORY (16M BYTE TO 128M BYTE)

P A M

Y R O M E M L A N R E T N

P A M

Y R O M E M

L A N R E T X E

Booting

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor contains a small boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Booting Modes on

Page 13.

Event Handling

The event controller on the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor handles all asynchronous and synchronous events to the processor. The ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller provides support for five different types of events:

• Emulation – An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface.

• Reset – This event resets the processor.

• Non-Maskable Interrupt (NMI) – The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system.

• Exceptions – Events that occur synchronously to program flow (i.e., the exception will be taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions.

• Interrupts – Events that occur asynchronously to program flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack.

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC.

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF531/ADSP-BF532/

Rev. A | Page 6 of 56 | January 2005

ADSP-BF531/ADSP-BF532/ADSP-BF533

ADSP-BF533 processor. Table 2 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities.

Table 2. Core Event Controller (CEC)

Priority (0 is Highest)

0Emulation/Test ControlEMU 1 Reset RST 2 Nonmaskable Interrupt NMI 3ExceptionEVX 4 Reserved 5 Hardware Error IVHW 6Core TimerIVTMR 7 General Interrupt 7 IVG7 8 General Interrupt 8 IVG8 9 General Interrupt 9 IVG9 10 General Interrupt 10 IVG10 11 General Interrupt 11 IVG11 12 General Interrupt 12 IVG12 13 General Interrupt 13 IVG13 14 General Interrupt 14 IVG14 15 General Interrupt 15 IVG15

Event Class EVT Entry

System Interrupt Controller (SIC)

The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor provides a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (IAR). Table 3 describes the inputs into the SIC and the default mappings into the CEC.

Event Control

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor provides the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide:

• CEC interrupt latch register (ILAT) – The ILAT register indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared.

• CEC interrupt mask register (IMASK) – The IMASK register controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though

Table 3. System Interrupt Controller (SIC)

Peripheral Interrupt Event Default Mapping

PLL Wakeup IVG7 DMA Error IVG7 PPI Error IVG7 SPORT 0 Error IVG7 SPORT 1 Error IVG7 SPI Error IVG7 UART Error IVG7 Real-Time Clock IVG8 DMA Channel 0 (PPI) IVG8 DMA Channel 1 (SPORT 0 RX) IVG9 DMA Channel 2 (SPORT 0 TX) IVG9 DMA Channel 3 (SPORT 1 RX) IVG9 DMA Channel 4 (SPORT 1 TX) IVG9 DMA Channel 5 (SPI) IVG10 DMA Channel 6 (UART RX) IVG10 DMA Channel 7 (UART TX) IVG10 Timer 0 IVG11 Timer 1 IVG11 Timer 2 IVG11 PF Interrupt A IVG12 PF Interrupt B IVG12 DMA Channels 8 and 9

(Memory DMA Stream 1) DMA Channels 10 and 11

(Memory DMA Stream 0) Software Watchdog Timer IVG13

IVG13

the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.)

• CEC interrupt pending register (IPEND) – The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode.

The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3 on Page 7.

• SIC interrupt mask register (SIC_IMASK) – This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in the register, that peripheral event is unmasked and will be processed by the

Rev. A | Page 7 of 56 | January 2005

ADSP-BF531/ADSP-BF532/ADSP-BF533

system when asserted. A cleared bit in the register masks the peripheral event, preventing the processor from servicing the event.

• SIC interrupt status register (SIC_ISR) – As multiple peripherals can be mapped to a single event, this register allows the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event.

• SIC interrupt wakeup enable register (SIC_IWR) – By enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. (For more infor-

mation, see Dynamic Power Management on Page 11.)

Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC will recognize and queue the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.

DMA CONTROLLERS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has multiple, independent DMA controllers that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor’s internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the SPORTs, SPI port, UART, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel.

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor DMA controller supports both 1-dimensional (1D) and 2-dimensional (2D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks.

The 2D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is especially useful in video applications where data can be de-interleaved on the fly.

Examples of DMA types supported by the ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor DMA controller include:

• A single, linear buffer that stops upon completion

• A circular, autorefreshing buffer that interrupts on each full or fractionally full buffer

• 1D or 2D DMA using a linked list of descriptors

• 2D DMA using an array of descriptors, specifying only the base DMA address within a common page

In addition to the dedicated peripheral DMA channels, there are two memory DMA channels provided for transfers between the various memories of the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor system. This enables transfers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and flash memory—with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism.

REAL-TIME CLOCK

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor realtime clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time.

The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60 second counter, a 60 minute counter, a 24 hour counter, and a 32,768 day counter.

When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day.

The stopwatch function counts down from a programmed value, with one second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated.

Like other peripherals, the RTC can wake up the processor from sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the processor from deep sleep mode, and wake up the on-chip internal voltage regulator from a powered-down state.

Connect RTC pins RTXI and RTXO with external components as shown in Figure 6.

Rev. A | Page 8 of 56 | January 2005

ADSP-BF531/ADSP-BF532/ADSP-BF533

RTXI

C1 C2

SUGGESTED COMPONENTS: ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 12 PF LOAD (SURFACE-MOUNT PACKAGE) C1 = 22 PF C2 = 22 PF R1 = 10 M OHM

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.

Figure 6. External Components for RTC

RTXO

WATCHDOG TIMER

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error.

If configured to generate a hardware reset, the watchdog timer resets both the core and the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register.

The timer is clocked by the system clock (SCLK), at a maximum frequency of f

SCLK

TIMERS

There are four general-purpose programmable timer units in the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor. Three timers have an external pin that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input to the PF1 pin, an external clock input to the PPI_CLK pin, or to the internal SCLK.

The timer units can be used in conjunction with the UART to measure the width of the pulses in the data stream to provide an autobaud detect function for a serial channel.

The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system clock or to a count of external signals.

In addition to the three general-purpose programmable timers, a fourth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts.

SERIAL PORTS (SPORTS)

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor incorporates two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features:

S capable operation.

•I

• Bidirectional operation – Each SPORT has two sets of independent transmit and receive pins, enabling eight channels

of I

S stereo audio.

• Buffered (8-deep) transmit and receive ports – Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers.

• Clocking – Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (f

/131,070) Hz to (f

SCLK

/2) Hz.

• Word length – Each SPORT supports serial data words from 3 to 32 bits in length, transferred most-significant-bit first or least-significant-bit first.

• Framing – Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync.

• Companding in hardware – Each SPORT can perform A-law or µ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies.

• DMA operations with single-cycle overhead – Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory.

• Interrupts – Each transmit and receive port generates an interrupt upon completing the transfer of a data-word or after transferring an entire data buffer or buffers through DMA.

• Multichannel capability – Each SPORT supports 128 channels out of a 1,024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible devices.

The SPI interface uses three pins for transferring data: two data pins (master output-slave input, MOSI, and master input-slave output, MISO) and a clock pin (serial clock, SCK). An SPI chip select input pin (SPISS

) lets other SPI devices select the proces-

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ADSP-BF531/ADSP-BF532/ADSP-BF533

sor, and seven SPI chip select output pins (SPISEL7–1) let the processor select other SPI devices. The SPI select pins are reconfigured programmable flag pins. Using these pins, the SPI port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments.

The SPI port’s baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller, configurable to support transmit or receive data streams. The SPI’s DMA controller can only service unidirectional accesses at any given time.

The SPI port’s clock rate is calculated as:

SCLK

SPI Clock Rate

---------------------------------

2 SPI_Baud×

Where the 16-bit SPI_Baud register contains a value of 2 to 65,535.

During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.

UART PORT

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor provides a full-duplex universal asynchronous receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART port includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates.

The UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable:

• Supporting bit rates ranging from (f (f

/16) bits per second.

SCLK

• Supporting data formats from seven to 12 bits per frame.

• Both transmit and receive operations can be configured to generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as:

----------------------------------------------- -

UART Clock Rate

16 UART_Divisor×

/1,048,576) to

SCLK

Where the 16-bit UART_Divisor comes from the DLH register (most significant 8 bits) and DLL register (least significant 8bits).

In conjunction with the general-purpose timer functions, autobaud detection is supported.

The capabilities of the UART are further extended with support for the Infrared Data Association (IrDA

) Serial Infrared Physi-

cal Layer Link Specification (SIR) protocol.

PROGRAMMABLE FLAGS (PFX)

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has 16 bidirectional, general-purpose programmable flag (PF15– 0) pins. Each programmable flag can be individually controlled by manipulation of the flag control, status and interrupt registers:

• Flag direction control register – Specifies the direction of each individual PFx pin as input or output.

• Flag control and status registers – The ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor employs a “write one to modify” mechanism that allows any combination of individual flags to be modified in a single instruction, without affecting the level of any other flags. Four control registers are provided. One register is written in order to set flag values, one register is written in order to clear flag values, one register is written in order to toggle flag values, and one register is written in order to specify a flag value. Reading the flag status register allows software to interrogate the sense of the flags.

• Flag interrupt mask registers – The two flag interrupt mask registers allow each individual PFx pin to function as an interrupt to the processor. Similar to the two flag control registers that are used to set and clear individual flag values, one flag interrupt mask register sets bits to enable interrupt function, and the other flag interrupt mask register clears bits to disable interrupt function. PFx pins defined as inputs can be configured to generate hardware interrupts, while output PFx pins can be triggered by software interrupts.

• Flag interrupt sensitivity registers – The two flag interrupt sensitivity registers specify whether individual PFx pins are level- or edge-sensitive and specify—if edge-sensitive— whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity.

PARALLEL PERIPHERAL INTERFACE

The processor provides a parallel peripheral interface (PPI) that can connect directly to parallel A/D and D/A converters, ITU-R 601/656 video encoders and decoders, and other generalpurpose peripherals. The PPI consists of a dedicated input clock pin, up to three frame synchronization pins, and up to 16 data pins. The input clock supports parallel data rates up to half the system clock rate.

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ADSP-BF531/ADSP-BF532/ADSP-BF533

In ITU-R 656 modes, the PPI receives and parses a data stream of 8-bit or 10-bit data elements. On-chip decode of embedded preamble control and synchronization information is supported.

Three distinct ITU-R 656 modes are supported:

• Active video only – The PPI does not read in any data between the end of active video (EAV) and start of active video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI.

• Vertical blanking only – The PPI only transfers vertical blanking interval (VBI) data, as well as horizontal blanking information and control byte sequences on VBI lines.

• Entire field – The entire incoming bitstream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals.

Though not explicitly supported, ITU-R 656 output functionality can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and streaming the data out the PPI in a frame sync-less mode. The processor’s 2D DMA features facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis.

The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. The modes are divided into four main categories, each allowing up to 16 bits of data transfer per PPI_CLK cycle:

• Data receive with internally generated frame syncs

• Data receive with externally generated frame syncs

• Data transmit with internally generated frame syncs

• Data transmit with externally generated frame syncs

These modes support ADC/DAC connections, as well as video communication with hardware signaling. Many of the modes support more than one level of frame synchronization. If desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data.

DYNAMIC POWER MANAGEMENT

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor provides five operating modes, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. Control of clocking to each of the ADSP-BF531/ ADSP-BF532/ADSP-BF533 processor peripherals also reduces power consumption. See Table 4 for a summary of the power settings for each mode.

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed.

Active Operating Mode—Moderate Power Savings

In the active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. In this mode, the CLKIN to CCLK multiplier ratio can be changed, although the changes are not realized until the full-on mode is entered. DMA access is available to appropriately configured L1 memories.

In the active mode, it is possible to disable the PLL through the PLL control register (PLL_CTL). If disabled, the PLL must be re-enabled before transitioning to the full-on or sleep modes.

Table 4. Power Settings

Mode PLL PLL

Bypassed

Full-On Enabled No Enabled Enabled On Active Enabled/

Disabled Sleep Enabled Disabled Enabled On Deep Sleep Disabled Disabled Disabled On Hibernate Disabled Disabled Disabled Off

Yes Enabled Enabled On

Core Clock (CCLK)

System Clock (SCLK)

Core Power

Hibernate Operating Mode—Maximum Static Power Savings

The hibernate mode maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register. This disables both CCLK and SCLK. Furthermore, it sets the internal power supply voltage (V

) to 0 V to provide the lowest static power

DDINT

dissipation. Any critical information stored internally (memory contents, register contents, etc.) must be written to a nonvolatile storage device prior to removing power if the processor state is to be preserved. Since V

is still supplied in this mode, all of

DDEXT

the external pins three-state, unless otherwise specified. This allows other devices that may be connected to the processor to have power still applied without drawing unwanted current. The internal supply regulator can be woken up either by a realtime clock wakeup or by asserting the RESET

pin.

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the processor. When in the sleep mode, assertion of wakeup will

Rev. A | Page 11 of 56 | January 2005

ADSP-BF531/ADSP-BF532/ADSP-BF533

cause the processor to sense the value of the BYPASS bit in the PLL control register (PLL_CTL). If BYPASS is disabled, the processor will transition to the full-on mode. If BYPASS is enabled, the processor will transition to the active mode.

When in the sleep mode, system DMA access to L1 memory is not supported.

Deep Sleep Operating Mode—Maximum Dynamic Power Savings

The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals, such as the RTC, may still be running but will not be able to access internal resources or external memory. This powereddown mode can only be exited by assertion of the reset interrupt (RESET

) or by an asynchronous interrupt generated by the RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the active mode. assertion of RESET

while in deep sleep mode causes the proces-

sor to transition to the full-on mode.

Power Savings

As shown in Table 5, the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor supports three different power domains. The use of multiple power domains maximizes flexibility, while maintaining compliance with industry standards and conventions. By isolating the internal logic of the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor into its own power domain, separate from the RTC and other I/O, the processor can take advantage of dynamic power management, without affecting the RTC or other I/O devices. There are no sequencing requirements for the various power domains.

Table 5. Power Domains

Power Domain VDD Range

All internal logic, except RTC V RTC internal logic and crystal I/O V All other I/O V

DDINT

DDRTC

DDEXT

The power dissipated by a processor is largely a function of the clock frequency of the processor and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic.

The dynamic power management feature of the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor allows both the processor’s input voltage (V (f

) to be dynamically controlled.

CCLK

) and clock frequency

DDINT

The savings in power dissipation can be modeled using the power savings factor and % power savings calculations.

The power savings factor is calculated as:

power savings factor

CCLKRED

---------------------

CCLKNOM

DDINTRED

⎛⎞

--------------------------

⎝⎠

DDINTNOM

RED

⎞

⎛

------------ -

⎠

⎝

NOM

where the variables in the equations are:

•f

•V

•T

is the nominal core clock frequency

CCLKNOM

is the reduced core clock frequency

CCLKRED

is the nominal internal supply voltage

DDINTNOM

is the reduced internal supply voltage

DDINTRED

is the duration running at f

NOM

is the duration running at f

RED

CCLKNOM

CCLKRED

The percent power savings is calculated as:

% power savings 1 power savings factor–()100%×=

VOLTAGE REGULATION

The Blackfin processor provides an on-chip voltage regulator that can generate processor core voltage levels 0.85 V to 1.2 V from an external 2.25 V to 3.6 V supply. Figure 7 shows the typical external components required to complete the power management system. voltage levels and is programmable with the voltage regulator control register (VR_CTL) in increments of 50 mV. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power (V

can still be applied, eliminating the need for external

DDEXT

buffers. The voltage regulator can be activated from this powerdown state either through an RTC wakeup or by asserting RESET

, which will then initiate a boot sequence. The regulator

can also be disabled and bypassed at the user’s discretion.

DDEXT

DDINT

1–0

OUT

See EE-228: Switching Regulator Design Considerations for ADSP-BF533

Blackfin Processors.

The regulator controls the internal logic

) supplied. While in hibernation,

DDEXT

100µF

10µH

0.1µF

100µF

1µF

NOTE: VR

OUT

AND DESIGNER S HOULD MINIMIZE T RACE LENGTH TO FDS 9431A.

Figure 7. Voltage Regulator Circuit

ZHCS1000

EXTERNAL CO MPONENTS

1–0 SHOULD BE TIED T OGETHER EXTERNALLY

2.25V TO 3.6V INPUT VOLTAG E RANGE

FDS9431A

Rev. A | Page 12 of 56 | January 2005

ADSP-BF531/ADSP-BF532/ADSP-BF533

133

CLOCK SIGNALS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator.

If an external clock is used, it must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor’s CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected.

Alternatively, because the ADSP-BF531/ADSP-BF532/ ADSP-BF533 processor includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 8. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessorgrade crystal should be used.

CLKIN

CLKOUTXTAL

into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

Table 6. Example System Clock Ratios

Signal Name SSEL3–0

Divider Ratio VCO/SCLK

Example Frequency Ratios (MHz)

VCO SCLK

0001 1:1 100 100 0011 3:1 400 133 1010 10:1 500 50

The maximum frequency of the system clock is f

. Note that

SCLK

the divisor ratio must be chosen to limit the system clock frequency to its maximum of f

. The SSEL value can be changed

SCLK

dynamically without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV).

The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1–0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

Table 7. Core Clock Ratios

Figure 8. External Crystal Connections

As shown in Figure 9 on Page 13, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a user programmable 1x to 63x multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier is 10x, but it can be modified by a software instruction sequence. On-the-fly frequency changes can be effected by simply writing to the PLL_DIV register.

“FINE” ADJUSTMENT

RE QUIRES PLL SEQ UENCING

CLKIN

PLL

0. 5×−64×

Figure 9. Frequency Modification Methods

VCO

SCL K ≤ CC L K SCL K ≤

“COARSE” ADJUSTMENT

ON-THE-FL Y

÷1,2,4,8

÷1:15

MHZ

CC LK

SCLK

Signal Name CSEL1–0

Divider Ratio VCO/CCLK

Example Frequency Ratios

VCO CCLK

00 1:1 300 300 01 2:1 300 150 10 4:1 500 125 11 8:1 200 25

BOOTING MODES

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor has two mechanisms (listed in Table 8) for automatically loading internal L1 instruction memory after a reset. A third mode is provided to execute from external memory, bypassing the boot sequence.

Table 8. Booting Modes

BMODE1–0 Description

00 Execute from 16-bit external memory (bypass

boot ROM) 01 Boot from 8-bit or 16-bit FLASH 10 Boot from SPI host slave mode) 11 Boot from SPI serial EEPROM (8-, 16-, or 24-bit

address range)

All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3–0 bits of the PLL_DIV register. The values programmed

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ADSP-BF531/ADSP-BF532/ADSP-BF533

The BMODE pins of the reset configuration register, sampled during power-on resets and software-initiated resets, implement the following modes:

• Execute from 16-bit external memory – Execution starts from address 0x2000 0000 with 16-bit packing. The boot ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup).

• Boot from 8-bit or 16-bit external flash memory – The flash boot routine located in boot ROM memory space is set up using asynchronous memory bank 0. All configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle R/W access times; 4-cycle setup).

• Boot from SPI serial EEPROM (8, 16, or 24-bit addressable) – The SPI uses the PF2 output pin to select a single SPI EEPROM device, submits successive read commands at addresses 0x00, 0x0000, and 0x000000 until a valid 8-, 16-, or 24-bit addressable EEPROM is detected, and begins clocking data into the beginning of L1 instruction memory.

For each of the boot modes, a 10-byte header is first read from an external memory device. The header specifies the number of bytes to be transferred and the memory destination address. Multiple memory blocks may be loaded by any boot sequence. Once all blocks are loaded, program execution commences from the start of L1 instruction SRAM.

In addition, Bit 4 of the reset configuration register can be set by application code to bypass the normal boot sequence during a software reset. For this case, the processor jumps directly to the beginning of L1 instruction memory.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor resources.

The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/CPU features are optimized for both 8-bit and 16-bit operations.

• A multi-issue load/store modified Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified programming model.

• Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data types; and separate user and supervisor stack pointers.

• Code density enhancements, which include intermixing of 16- and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits.

DEVELOPMENT TOOLS

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor is supported with a complete set of CROSSCORE hardware development tools, including Analog Devices emulators and VisualDSP++

‡

development environment. The same emulator hardware that supports other Blackfin processors also fully emulates the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor.

The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to processor assembly. The processor has architectural features that improve the efficiency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action.

†

software and

†

CROSSCORE is a registered trademark of Analog Devices, Inc.

‡

VisualDSP++ is a registered trademark of Analog Devices, Inc.

Rev. A | Page 14 of 56 | January 2005

ADSP-BF531/ADSP-BF532/ADSP-BF533

Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source and object information).

• Insert breakpoints.

• Set conditional breakpoints on registers, memory, and stacks.

• Trace instruction execution.

• Perform linear or statistical profiling of program execution.

• Fill, dump, and graphically plot the contents of memory.

• Perform source level debugging.

• Create custom debugger windows.

The VisualDSP++ IDDE lets programmers define and manage software development. Its dialog boxes and property pages let programmers configure and manage all of the Blackfin development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and generate outputs.

• Maintain a one-to-one correspondence with the tool’s command line switches.

The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK.

VCSE is Analog Devices technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. Components can be downloaded from the Web and dropped into the application. Component archives can be published from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.

Use the expert linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color coded graphical form, easily move code and data to different areas of the processor or external memory with the drag of the mouse, and examine runtime stack and heap usage.

The expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments.

Analog Devices emulators use the IEEE 1149.1 JTAG test access port of the ADSP-BF531/ADSP-BF532/ADSP-BF533 processor to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing.

In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the Blackfin processor family. Hardware tools include Blackfin processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.

DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD

The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG processor. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)— use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support.

Rev. A | Page 15 of 56 | January 2005

ADSP-BF531/ADSP-BF532/ADSP-BF533

PIN DESCRIPTIONS

ADSP-BF531/ADSP-BF532/ADSP-BF533 processor pin definitions are listed in Table 9.

All pins are three-stated during and immediately after reset, except the memory interface, asynchronous memory control, and synchronous memory control pins, which are driven high.

is active, then the memory pins are also three-stated. All

If BR unused I/O pins have their input buffers disabled with the exception of the pins that need pull-ups or pull-downs as noted in the table footnotes.

In order to maintain maximum functionality and reduce package size and pin count, some pins have dual, multiplexed functionality. In cases where pin functionality is reconfigurable, the default state is shown in plain text, while alternate functionality is shown in italics.

Table 9. Pin Descriptions

Pin Name I/O Function Driver Type

Memory Interface

ADDR19–1 O Address Bus for Async/Sync Access A DATA15–0 I/O Data Bus for Async/Sync Access A ABE1–0/SDQM1–0 O Byte Enables/Data Masks for Async/Sync Access A

BR BG

IBus Request OBus Grant A

BGH OBus Grant Hang A

Asynchronous Memory Control

AMS3–0

OBank Select A

ARDY I Hardware Ready Control AOE

OOutput Enable A ARE ORead Enable A AWE OWrite Enable A

Synchronous Memory Control

SRAS

O Row Address Strobe A SCAS O Column Address Strobe A SWE OWrite Enable A SCKE O Clock Enable A CLKOUT O Clock Output B SA10 O A10 Pin A SMS OBank Select A

Timers

TMR0 I/O Timer 0 C TMR1/PPI_FS1 I/O Timer 1/PPI Frame Sync1 C TMR2/PPI_FS2 I/O Timer 2/PPI Frame Sync2 C

Rev. A | Page 16 of 56 | January 2005

ADSP-BF531/ADSP-BF532/ADSP-BF533

Table 9. Pin Descriptions (Continued)

Pin Name I/O Function Driver Type

Parallel Peripheral Interface Port/GPIO

PF0/SPISS

I/O Programmable Flag 0/SPI Slave Select Input C PF1/SPISEL1/TMRCLK I/O Programmable Flag 1/SPI Slave Select Enable 1/External Timer Reference C PF2/SPISEL2 I/O Programmable Flag 2/SPI Slave Select Enable 2 C PF3/SPISEL3/PPI_FS3 I/O Programmable Flag 3/SPI Slave Select Enable 3/PPI Frame Sync 3 C PF4/SPISEL4/PPI15 I/O Programmable Flag 4/SPI Slave Select Enable 4 / PPI 15 C PF5/SPISEL5/PPI14 I/O Programmable Flag 5/SPI Slave Select Enable 5 / PPI 14 C PF6/SPISEL6/PPI13 I/O Programmable Flag 6/SPI Slave Select Enable 6 / PPI 13 C PF7/SPISEL7/PPI12 I/O Programmable Flag 7/SPI Slave Select Enable 7 / PPI 12 C PF8/PPI11 I/O Programmable Flag 8/PPI 11 C PF9/PPI10 I/O Programmable Flag 9/PPI 10 C PF10/PPI9 I/O Programmable Flag 10/PPI 9 C PF11/PPI8 I/O Programmable Flag 11/PPI 8 C PF12/PPI7 I/O Programmable Flag 12/PPI 7 C PF13/PPI6 I/O Programmable Flag 13/PPI 6 C PF14/PPI5 I/O Programmable Flag 14/PPI 5 C PF15/PPI4 I/O Programmable Flag 15/PPI 4 C PPI3–0 I/O PPI3–0 C PPI_CLK I PPI Clock C

Serial Ports

RSCLK0 I/O SPORT0 Receive Serial Clock D RFS0 I/O SPORT0 Receive Frame Sync C DR0PRI I SPORT0 Receive Data Primary DR0SEC I SPORT0 Receive Data Secondary TSCLK0 I/O SPORT0 Transmit Serial Clock D TFS0 I/O SPORT0 Transmit Frame Sync C DT0PRI O SPORT0 Transmit Data Primary C DT0SEC O SPORT0 Transmit Data Secondary C RSCLK1 I/O SPORT1 Receive Serial Clock D RFS1 I/O SPORT1 Receive Frame Sync C DR1PRI I SPORT1 Receive Data Primary DR1SEC I SPORT1 Receive Data Secondary TSCLK1 I/O SPORT1 Transmit Serial Clock D TFS1 I/O SPORT1 Transmit Frame Sync C DT1PRI O SPORT1 Transmit Data Primary C DT1SEC O SPORT1 Transmit Data Secondary C

SPI Port

MOSI I/O Master Out Slave In C

MISO

I/O Master In Slave Out C SCK I/O SPI Clock D

Rev. A | Page 17 of 56 | January 2005

+ 39 hidden pages

Analog Devices ADSP BF531 2 3 a Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

MEMORY

PERIPHERALS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

PORTABLE LOW POWER ARCHITECTURE

SYSTEM INTEGRATION

ADSP-BF531/ADSP-BF532/ADSP-BF533 PROCESSOR PERIPHERALS

BLACKFIN PROCESSOR CORE

MEMORY ARCHITECTURE

Internal (On-Chip) Memory

External (Off-Chip) Memory

I/O Memory Space

Booting

Event Handling

Core Event Controller (CEC)

System Interrupt Controller (SIC)

Event Control

DMA CONTROLLERS

REAL-TIME CLOCK

WATCHDOG TIMER

TIMERS

SERIAL PORTS (SPORTS)

SERIAL PERIPHERAL INTERFACE (SPI) PORT

UART PORT

PROGRAMMABLE FLAGS (PFX)

PARALLEL PERIPHERAL INTERFACE

DYNAMIC POWER MANAGEMENT

Power Savings

VOLTAGE REGULATION

CLOCK SIGNALS

BOOTING MODES

INSTRUCTION SET DESCRIPTION

DEVELOPMENT TOOLS

DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD

PIN DESCRIPTIONS