ANALOG DEVICES ADSP-BF522, ADSP-BF523, ADSP-BF524, ADSP-BF525, ADSP-BF526 Service Manual

...

Blackfin

SPORT0

TIMER0

VOLTAGE REGULATOR*

*REGULATOR ONLY AVAILABLE ON ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS

PORT J

GPIO

PORT H

GPIO

PORT G

GPIO

PORT F

JTAG TEST AND EMULATION

PERIPHERAL ACCESS BUS

OTP MEMORY

COUNTER

WATCHDOG TIMER

RTC

TWI

SPORT1

NFC

PPI

UART0

SPI

TIMER7

EMAC

HOST DMA

BOOT

ROM

DMA

ACCESS

BUS

INTERRUPT

CONTROLLER

DMA

CONTROLLER

L1 DATA

MEMORY

L1 INSTRUCTION

MEMORY

USB

DCB

EAB

EXTERNAL PORT

FLASH, SDRAM CONTROL

UART1

DEB

Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

FEATURES

Up to 600 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of

programming and compiler-friendly support

Advanced debug, trace, and performance monitoring

Accepts a wide range of supply voltages for internal and I/O

operations. See Specifications on Page 27

Programmable on-chip voltage regulator (ADSP-BF523/

ADSP-BF525/ADSP-BF527 processors only)

Qualified for Automotive Applications. See Automotive

Products on Page 86

289-ball and 208-ball CSP_BGA packages

MEMORY

132K bytes of on-chip memory (See Table 1 on Page 3 for L1

and L3 memory size details)

External memory controller with glueless support for SDRAM

and asynchronous 8-bit and 16-bit memories

Flexible booting options from external flash, SPI, and TWI

memory or from host devices including SPI, TWI, and UART

Code security with Lockbox Secure Technology

one-time-programmable (OTP) memory

Memory management unit providing memory protection

PERIPHERALS

USB 2.0 high speed on-the-go (OTG) with integrated PHY IEEE 802.3-compliant 10/100 Ethernet MAC Parallel peripheral interface (PPI), supporting ITU-R 656

video data formats Host DMA port (HOSTDP) 2 dual-channel, full-duplex synchronous serial ports

(SPORTs), supporting eight stereo I 12 peripheral DMAs, 2 mastered by the Ethernet MAC 2 memory-to-memory DMAs with external request lines Event handler with 54 interrupt inputs Serial peripheral interface (SPI) compatible port 2 UARTs with IrDA support 2-wire interface (TWI) controller Eight 32-bit timers/counters with PWM support 32-bit up/down counter with rotary support Real-time clock (RTC) and watchdog timer 32-bit core timer 48 general-purpose I/Os (GPIOs), with programmable

hysteresis NAND flash controller (NFC) Debug/JTAG interface On-chip PLL capable of frequency multiplication

S channels

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Figure 1. Processor Block Diagram

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Features ................................................................. 1

Memory ................................................................ 1

Peripherals ............................................................. 1

General Description ................................................. 3

Portable Low Power Architecture ............................. 3

System Integration ................................................ 3

Processor Peripherals ............................................. 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 5

DMA Controllers .................................................. 9

Host DMA Port .................................................... 9

Real-Time Clock ................................................. 10

Watchdog Timer ................................................ 10

Timers ............................................................. 10

Up/Down Counter and Thumbwheel Interface .......... 10

Serial Ports ........................................................ 11

Serial Peripheral Interface (SPI) Port ....................... 11

UART Ports ...................................................... 11

TWI Controller Interface ...................................... 12

10/100 Ethernet MAC .......................................... 12

Ports ................................................................ 12

Parallel Peripheral Interface (PPI) ........................... 13

USB On-The-Go Dual-Role Device Controller ........... 14

Code Security with Lockbox Secure Technology ......... 14

Dynamic Power Management ................................ 14

ADSP-BF523/ADSP-BF525/ADSP-BF527

Voltage Regulation ........................................... 16

ADSP-BF522/ADSP-BF524/ADSP-BF526

Voltage Regulation ........................................... 16

Clock Signals ..................................................... 16

Booting Modes ................................................... 18

Instruction Set Description .................................... 20

Development Tools .............................................. 21

Designing an Emulator-Compatible

Processor Board (Target) ................................... 21

Related Documents .............................................. 21

Related Signal Chains ........................................... 21

Lockbox Secure Technology Disclaimer .................... 21

Signal Descriptions ................................................. 22

Specifications ........................................................ 27

Operating Conditions

for ADSP-BF522/ADSP-BF524/ADSP-BF526

Processors ...................................................... 27

Operating Conditions

for ADSP-BF523/ADSP-BF525/ADSP-BF527

Processors ...................................................... 29

Electrical Characteristics ....................................... 31

Absolute Maximum Ratings ................................... 36

Package Information ............................................ 37

ESD Sensitivity ................................................... 37

Timing Specifications ........................................... 38

Output Drive Currents ......................................... 72

Test Conditions .................................................. 74

Environmental Conditions .................................... 78

289-Ball CSP_BGA Ball Assignment .. ......................... 79

208-Ball CSP_BGA Ball Assignment .. ......................... 82

Outline Dimensions ................................................ 85

Surface-Mount Design .......................................... 86

Automotive Products .............................................. 86

Ordering Guide ..................................................... 87

REVISION HISTORY

3/12—Rev. B to Rev. C

Corrected USB_VREF and USB_VBUS function (DOC ID:

DOC-881) descriptions in Signal Descriptions .............. 22

Corrected footnote on V

ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors ..... 29

Corrected footnotes and added parameters (DOC-ID:

DOC-901 in Table 26, Absolute Maximum Ratings ........ 36

Corrected footnote on Table 27, Maximum Duty Cycle for

Input Transient Voltage, .......................................... 36

Added Table 29, Maximum Duty Cycle for IOH/IOL Current

Per Pin Group ....................................................... 37

, Operating Conditions for

DDMEM

Rev. C | Page 2 of 88 | March 2012

Replaced 289-Ball CSP_BGA (BC-289-2) ..................... 85

Added the ADBF525WYBCZxxx model to Automotive Prod-

ucts ..................................................................... 86

Added the ADSP-BF525ABCZ-5 and ADSP-BF525ABCZ-6

models to Ordering Guide ........................................ 87

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

GENERAL DESCRIPTION

The ADSP-BF52x processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin

processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.

The ADSP-BF52x processors are completely code compatible with other Blackfin processors. The ADSP-BF523/ ADSP-BF525/ADSP-BF527 processors offer performance up to 600 MHz. The ADSP-BF522/ADSP-BF524/ADSP-BF526 processors offer performance up to 400 MHz and reduced static power consumption. Differences with respect to peripheral combinations are shown in Table 1.

Table 1. Processor Comparison

Feature

Host DMA 111111 USB – 1 1 – 1 1 Ethernet MAC – – 1 – – 1 Internal Voltage Regulator – – – 1 1 1 TWI 111111 SPORTs 222222 UARTs 222222 SPI 111111 GP Timers 888888 GP Counter 111111 Watchdog Timers 111111 RTC 111111 Parallel Peripheral Interface 111111 GPIOs 48 48 48 48 48 48

L1 Instruction SRAM 48K 48K 48K 48K 48K 48K L1 Instruction SRAM/Cache 16K 16K 16K 16K 16K 16K L1 Data SRAM 32K 32K 32K 32K 32K 32K L1 Data SRAM/Cache 32K 32K 32K 32K 32K 32K L1 Scratchpad 4K 4K 4K 4K 4K 4K

Memory (bytes)

L3 Boot ROM 32K 32K 32K 32K 32K 32K Maximum Instruction Rate Maximum System Clock Speed 100 MHz 133 MHz Package Options 289-Ball CSP_BGA

Maximum instruction rate is not available with every possible SCLK selection.

ADSP-BF522

ADSP-BF524

ADSP-BF526

ADSP-BF523

ADSP-BF525

400 MHz 600 MHz

208-Ball CSP_BGA

ADSP-BF527

By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package.

PORTABLE LOW POWER ARCHITECTURE

Blackfin processors provide world-class power management and performance. They are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which is the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. This capability can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This allows longer battery life for portable appliances.

SYSTEM INTEGRATION

The ADSP-BF52x processors are highly integrated system-on-achip solutions for the next generation of embedded network connected applications. By combining industry-standard interfaces with a high performance signal processing core, costeffective applications can be developed quickly, without the need for costly external components. The system peripherals include an IEEE-compliant 802.3 10/100 Ethernet MAC, a USB

2.0 high speed OTG controller, a TWI controller, a NAND flash controller, two UART ports, an SPI port, two serial ports (SPORTs), eight general purpose 32-bit timers with PWM capability, a core timer, a real-time clock, a watchdog timer, a Host DMA (HOSTDP) interface, and a parallel peripheral interface (PPI).

PROCESSOR PERIPHERALS

The ADSP-BF52x processors contain a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see the block diagram on Page 1).

These Blackfin processors contain dedicated network communication modules and high speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios.

All of the peripherals, except for the general-purpose I/O, TWI, real-time clock, and timers, are supported by a flexible DMA structure. There are also separate memory DMA channels dedicated to data transfers between the processor's various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals.

The ADSP-BF523/ADSP-BF525/ADSP-BF527 processors include an on-chip voltage regulator in support of the processor’s dynamic power management capability. The voltage

Rev. C | Page 3 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

SEQUENCER

ALIGN

DECODE

LOOP BUFFER

8888

40 40

A0 A1

BARREL SHIFTER

DATA ARITHMETIC UNIT

CONTROL

UNIT

R7.H R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R7.L R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

AS TAT

40 40

32 32 32LD0

LD1

DAG0

DAG1

ADDRESS ARITHMETIC UNIT

SP FP

P4 P3

DA1

DA0

PREG

RAB

TO MEMORY

regulator provides a range of core voltage levels when supplied from V

. The voltage regulator can be bypassed at the user's

DDEXT

discretion.

BLACKFIN PROCESSOR CORE

As shown in Figure 2, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-, 16-, or 32-bit data from the register file.

The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields.

Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported.

The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions.

For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). If the second ALU is used, quad 16-bit operations are possible.

Figure 2. Blackfin Processor Core

The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions.

The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies.

The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify,

Rev. C | Page 4 of 88 | March 2012

RESERVED

CORE MMR REGISTERS (2M BYTES)

RESERVED

SCRATCHPAD SRAM (4K BYTES)

INSTRUCTION BANK B SRAM (16K BYTES)

SYSTEM MMR RE GISTERS (2M BYTES)

RESERVED

DATA BANK B SRAM / CACHE (16K BYTES)

DATA BANK B SRAM (16K BYTES)

DATA BANK A SRAM / CACHE (16K BYTES)

ASYNC MEMORY BANK 3 (1M BYTES)

ASYNC MEMORY BANK 2 (1M BYTES)

ASYNC MEMORY BANK 1 ( 1M BYTES)

ASYNC MEMORY BANK 0 ( 1M BYTES)

SDRAM MEMORY (16M BYTES 128M BYTES)

INSTRUCTION SRAM / CACHE (16K BYTES)

0xFFFF FFFF

0xFFE0 0000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0xEF00 0000

0x0000 0000

0xFFC0 0000

0xFFB0 1000

0xFFA0 0000

DATA BANK A SRAM (16K BYTES)

0xFF90 0000

0xFF80 0000

RESERVED

0xFFA0 C000

0xFFA0 8000

INSTRUCTION BANK A SRAM (32K BYTES)

RESERVED

BOOT ROM (32K BYTES)

0xEF00 8000

RESERVED

0x08 00 0000

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation).

Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information.

In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access.

The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources.

The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle.

The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

The Blackfin processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency on-chip memory as cache or SRAM, and larger, lower-cost and performance off-chip memory systems. See Figure 3.

The on-chip L1 memory system is the highest-performance memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical memory.

The memory DMA controller provides high-bandwidth datamovement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces.

Rev. C | Page 5 of 88 | March 2012

Internal (On-Chip) Memory

The processor has three blocks of on-chip memory providing high-bandwidth access to the core.

The first block is the L1 instruction memory, consisting of 64K bytes SRAM, of which 16K bytes can be configured as a four-way set-associative cache. This memory is accessed at full processor speed.

The second on-chip memory block is the L1 data memory, consisting of up to two banks of up to 32K bytes each. Each memory bank is configurable, offering both cache and SRAM functionality. This memory block is accessed at full processor speed.

The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory.

External (Off-Chip) Memory

External memory is accessed via the EBIU. This 16-bit interface provides a glueless connection to a bank of synchronous DRAM (SDRAM), as well as up to four banks of asynchronous memory devices including flash, EPROM, ROM, SRAM, and memory mapped I/O devices.

Figure 3. Internal/External Memory Map

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

The SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. A separate row can be open for each SDRAM internal bank and the SDRAM controller supports up to 4 internal SDRAM banks, improving overall performance.

The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing requirements for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated with 1M byte of memory.

NAND Flash Controller (NFC)

The ADSP-BF52x processors provide a NAND flash controller (NFC). NAND flash devices provide high-density, low-cost memory. However, NAND flash devices also have long random access times, invalid blocks, and lower reliability over device lifetimes. Because of this, NAND flash is often used for readonly code storage. In this case, all DSP code can be stored in NAND flash and then transferred to a faster memory (such as SDRAM or SRAM) before execution. Another common use of NAND flash is for storage of multimedia files or other large data segments. In this case, a software file system may be used to manage reading and writing of the NAND flash device. The file system selects memory segments for storage with the goal of avoiding bad blocks and equally distributing memory accesses across all address locations. Hardware features of the NFC include:

• Support for page program, page read, and block erase of NAND flash devices, with accesses aligned to page boundaries.

• Error checking and correction (ECC) hardware that facilitates error detection and correction.

• A single 8-bit external bus interface for commands, addresses, and data.

• Support for SLC (single level cell) NAND flash devices unlimited in size, with page sizes of 256 and 512 bytes. Larger page sizes can be supported in software.

• Capability of releasing external bus interface pins during long accesses.

• Support for internal bus requests of 16 bits.

• DMA engine to transfer data between internal mem ory a nd NAND flash device.

One-Time Programmable Memory

The processor has 64K bits of one-time programmable nonvolatile memory that can be programmed by the developer only one time. It includes the array and logic to support read access and programming. Additionally, its pages can be write protected.

OTP enables developers to store both public and private data on-chip. In addition to storing public and private key data for applications requiring security, it also allows developers to store completely user-definable data such as customer ID, product

ID, MAC address, etc. Hence, generic parts can be shipped, which are then programmed and protected by the developer within this non-volatile memory.

I/O Memory Space

The processor does not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals.

Booting

The processor contains a small on-chip boot kernel, which configures the appropriate peripheral for booting. If the processor is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Booting Modes on Page 18.

Event Handling

The event controller on the processor handles all asynchronous and synchronous events to the processor. The processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher-priority event takes precedence over servicing of a lower-priority event. The controller provides support for five different types of events:

• Emulation — An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface.

• RESET

• Nonmaskable Interrupt (NMI) — The NMI event can be

• Exceptions — Events that occur synchronously to program

• Interrupts — Events that occur asynchronously to program

Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack.

The processor event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt

— This event resets the processor.

generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system.

flow (in other words, the exception is taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions.

flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction.

Rev. C | Page 6 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter into the SIC and are then routed directly into the general-purpose interrupts of the CEC.

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest-priority interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the processor. Table 2 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities.

System Interrupt Controller (SIC)

The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the processor provides a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (SIC_IARx). Table 3 describes the inputs into the SIC and the default mappings into the CEC.

Table 3. System Interrupt Controller (SIC)

Table 2. Core Event Controller (CEC)

Priority (0 is Highest) Event Class EVT Entry

0Emulation/Test ControlEMU 1RESET 2 Nonmaskable Interrupt NMI 3Exception EVX 4 Reserved — 5 Hardware Error IVHW 6 Core Timer IVTMR 7 General-Purpose Interrupt 7 IVG7 8 General-Purpose Interrupt 8 IVG8 9 General-Purpose Interrupt 9 IVG9 10 General-Purpose Interrupt 10 IVG10 11 General-Purpose Interrupt 11 IVG11 12 General-Purpose Interrupt 12 IVG12 13 General-Purpose Interrupt 13 IVG13 14 General-Purpose Interrupt 14 IVG14 15 General-Purpose Interrupt 15 IVG15

RST

General Purpose

Peripheral Interrupt Event

PLL Wakeup Interrupt IVG7 0 0 IAR0 IMASK0, ISR0, IWR0 DMA Error 0 (generic) IVG7 1 0 IAR0 IMASK0, ISR0, IWR0 DMAR0 Block Interrupt IVG7 2 0 IAR0 IMASK0, ISR0, IWR0 DMAR1 Block Interrupt IVG7 3 0 IAR0 IMASK0, ISR0, IWR0 DMAR0 Overflow Error IVG7 4 0 IAR0 IMASK0, ISR0, IWR0 DMAR1 Overflow Error IVG7 5 0 IAR0 IMASK0, ISR0, IWR0 PPI Error IVG7 6 0 IAR0 IMASK0, ISR0, IWR0 MAC Status IVG7 7 0 IAR0 IMASK0, ISR0, IWR0 SPORT0 Status IVG7 8 0 IAR1 IMASK0, ISR0, IWR0 SPORT1 Status IVG7 9 0 IAR1 IMASK0, ISR0, IWR0 Reserved IVG7 10 0 IAR1 IMASK0, ISR0, IWR0 Reserved IVG7 11 0 IAR1 IMASK0, ISR0, IWR0 UART0 Status IVG7 12 0 IAR1 IMASK0, ISR0, IWR0 UART1 Status IVG7 13 0 IAR1 IMASK0, ISR0, IWR0 RTC IVG8 14 1 IAR1 IMASK0, ISR0, IWR0 DMA Channel 0 (PPI/NFC) IVG8 15 1 IAR1 IMASK0, ISR0, IWR0 DMA Channel 3 (SPORT0 RX) IVG9 16 2 IAR2 IMASK0, ISR0, IWR0 DMA Channel 4 (SPORT0 TX) IVG9 17 2 IAR2 IMASK0, ISR0, IWR0 DMA Channel 5 (SPORT1 RX) IVG9 18 2 IAR2 IMASK0, ISR0, IWR0 DMA Channel 6 (SPORT1 TX) IVG9 19 2 IAR2 IMASK0, ISR0, IWR0 TWI IVG10 20 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 7 (SPI) IVG10 21 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 8 (UART0 RX) IVG10 22 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 9 (UART0 TX) IVG10 23 3 IAR2 IMASK0, ISR0, IWR0 DMA Channel 10 (UART1 RX) IVG10 24 3 IAR3 IMASK0, ISR0, IWR0 DMA Channel 11 (UART1 TX) IVG10 25 3 IAR3 IMASK0, ISR0, IWR0

Interrupt (at RESET)Peripheral Interrupt ID

Default Core Interrupt ID

SIC Registers

Rev. C | Page 7 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 3. System Interrupt Controller (SIC) (Continued)

General Purpose

Peripheral Interrupt Event

OTP Memory Interrupt IVG11 26 4 IAR3 IMASK0, ISR0, IWR0 GP Counter IVG11 27 4 IAR3 IMASK0, ISR0, IWR0 DMA Channel 1 (MAC RX/HOSTDP) IVG11 28 4 IAR3 IMASK0, ISR0, IWR0 Port H Interrupt A IVG11 29 4 IAR3 IMASK0, ISR0, IWR0 DMA Channel 2 (MAC TX/NFC) IVG11 30 4 IAR3 IMASK0, ISR0, IWR0 Port H Interrupt B IVG11 31 4 IAR3 IMASK0, ISR0, IWR0 Timer 0 IVG12 32 5 IAR4 IMASK1, ISR1, IWR1 Timer 1 IVG12 33 5 IAR4 IMASK1, ISR1, IWR1 Timer 2 IVG12 34 5 IAR4 IMASK1, ISR1, IWR1 Timer 3 IVG12 35 5 IAR4 IMASK1, ISR1, IWR1 Timer 4 IVG12 36 5 IAR4 IMASK1, ISR1, IWR1 Timer 5 IVG12 37 5 IAR4 IMASK1, ISR1, IWR1 Timer 6 IVG12 38 5 IAR4 IMASK1, ISR1, IWR1 Timer 7 IVG12 39 5 IAR4 IMASK1, ISR1, IWR1 Port G Interrupt A IVG12 40 5 IAR5 IMASK1, ISR1, IWR1 Port G Interrupt B IVG12 41 5 IAR5 IMASK1, ISR1, IWR1 MDMA Stream 0 IVG13 42 6 IAR5 IMASK1, ISR1, IWR1 MDMA Stream 1 IVG13 43 6 IAR5 IMASK1, ISR1, IWR1 Software Watchdog Timer IVG13 44 6 IAR5 IMASK1, ISR1, IWR1 Port F Interrupt A IVG13 45 6 IAR5 IMASK1, ISR1, IWR1 Port F Interrupt B IVG13 46 6 IAR5 IMASK1, ISR1, IWR1 SPI Status IVG7 47 0 IAR5 IMASK1, ISR1, IWR1 NFC Status IVG7 48 0 IAR6 IMASK1, ISR1, IWR1 HOSTDP Status IVG7 49 0 IAR6 IMASK1, ISR1, IWR1 Host Read Done IVG7 50 0 IAR6 IMASK1, ISR1, IWR1 Reserved IVG10 51 3 IAR6 IMASK1, ISR1, IWR1 USB_INT0 Interrupt IVG10 52 3 IAR6 IMASK1, ISR1, IWR1 USB_INT1 Interrupt IVG10 53 3 IAR6 IMASK1, ISR1, IWR1 USB_INT2 Interrupt IVG10 54 3 IAR6 IMASK1, ISR1, IWR1 USB_DMAINT Interrupt IVG10 55 3 IAR6 IMASK1, ISR1, IWR1

Interrupt (at RESET)Peripheral Interrupt ID

Default Core Interrupt ID

SIC Registers

Event Control

The processor provides a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each register is 16 bits wide.

• CEC interrupt latch register (ILAT) — Indicates when events have been latched. The appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. This register is updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared.

• CEC interrupt mask register (IMASK) — Controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and is processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read or

Rev. C | Page 8 of 88 | March 2012

written while in supervisor mode. (Note that generalpurpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.)

• CEC interrupt pending register (IPEND) — The IPEND register keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode.

The SIC allows further control of event processing by providing three pairs of 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 3 on Page 7.

• SIC interrupt mask registers (SIC_IMASKx) — Control the masking and unmasking of each peripheral interrupt event. When a bit is set in these registers, that peripheral event is

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

unmasked and is processed by the system when asserted. A cleared bit in the register masks the peripheral event, preventing the processor from servicing the event.

• SIC interrupt status registers (SIC_ISRx) — As multiple peripherals can be mapped to a single event, these registers allow the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event.

• SIC interrupt wakeup enable registers (SIC_IWRx) — By enabling the corresponding bit in these registers, a peripheral can be configured to wake up the processor, should the core be idled or in sleep mode when the event is generated. For more information see Dynamic Power Management on

Page 14.

Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC recognizes and queues the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.

DMA CONTROLLERS

The processor has multiple, independent DMA channels that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the processor's internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMA-capable peripherals include the Ethernet MAC, NFC, HOSTDP, USB, SPORTs, SPI port, UARTs, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel.

The processor DMA controller supports both one-dimensional (1-D) and two-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks.

The 2-D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly.

Examples of DMA types supported by the processor DMA controller include:

• A single, linear buffer that stops upon completion.

• A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer.

• 1-D or 2-D DMA using a linked list of descriptors.

• 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page.

In addition to the dedicated peripheral DMA channels, there are two memory DMA channels provided for transfers between the various memories of the processor system. This enables transfers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and flash memory—with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism.

The processor also has an external DMA controller capability via dual external DMA request pins when used in conjunction with the external bus interface unit (EBIU). This functionality can be used when a high speed interface is required for external FIFOs and high bandwidth communications peripherals such as USB 2.0. It allows control of the number of data transfers for memory DMA. The number of transfers per edge is programmable. This feature can be programmed to allow memory DMA to have an increased priority on the external bus relative to the core.

HOST DMA PORT

The host port interface allows an external host to be a DMA master to transfer data in and out of the device. The host device masters the transactions and the Blackfin processor is the DMA slave.

The host port is enabled through the PAB interface. Once enabled, the DMA is controlled by the external host, which can then program the DMA to send/receive data to any valid internal or external memory location.

The host port interface controller has the following features.

• Allows external master to configure DMA read/write data transfers and read port status.

• Uses asynchronous memory protocol for external interface.

• 8-/16-bit external data interface to host device.

• Half duplex operation.

• Little-/big-endian data transfer.

• Acknowledge mode allows flow control on host transactions.

• Interrupt mode guarantees a burst of FIFO depth host transactions.

REAL-TIME CLOCK

The real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the Blackfin processor. Connect RTC pins RTXI and RTXO with external

Rev. C | Page 9 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

RTXO

C1 C2

SUGGESTED COMPONENTS: X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR

EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE) C1 = 22 pF C2 = 22 pF R1 = 10 M:

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

RTXI

components as shown in Figure 4.

Figure 4. External Components for RTC

The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time.

The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter.

When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day.

The stopwatch function counts down from a programmed value, with one-second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated.

Like the other peripherals, the RTC can wake up the processor from sleep mode upon generation of any RTC wake-up event. Additionally, an RTC wakeup event can wake up the processor from deep sleep mode or cause a transition from the hibernate state.

WATCHDOG TIMER

The processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an

unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error.

If configured to generate a hardware reset, the watchdog timer resets both the core and the processor peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register.

The timer is clocked by the system clock (SCLK), at a maximum frequency of f

TIMERS

There are nine general-purpose programmable timer units in the processors. Eight timers have an external pin that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input to the several other associated PF pins, an external clock input to the PPI_CLK input pin, or to the internal SCLK.

The timer units can be used in conjunction with the two UARTs to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels.

The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system clock or to a count of external signals.

In addition to the eight general-purpose programmable timers, a ninth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts.

UP/DOWN COUNTER AND THUMBWHEEL INTERFACE

A 32-bit up/down counter is provided that can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumb wheels. The counter can also operate in general-purpose up/down count modes. Then, count direction is either controlled by a level-sensitive input pin or by two edge detectors.

A third input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. All three pins have a programmable debouncing circuit.

An internal signal forwarded to the timer unit enables one timer to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by interrupts when programmable count values are exceeded.

SERIAL PORTS

The processors incorporate two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features:

S capable operation.

•I

Rev. C | Page 10 of 88 | March 2012

SCLK

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

SPI Clock Rate

SCLK

2 SPI_BAUD×

----------------------------------- -

UART Clock Rate

SCLK

16 UART_Divisor×

-----------------------------------------------

• Bidirectional operation — Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I

S stereo audio.

• Buffered (8-deep) transmit and receive ports — Each port has a data register for transferring data words to and from other processor components and shift registers for shifting data in and out of the data registers.

• Clocking — Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (f

/131,070) Hz to (f

SCLK

/2) Hz.

• Word length – Each SPORT supports serial data words from 3 to 32 bits in length, transferred most-significant-bit first or least-significant-bit first.

• Framing — Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync.

• Companding in hardware — Each SPORT can perform A-law or µ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies.

• DMA operations with single-cycle overhead — Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory.

• Interrupts — Each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer, or buffers, through DMA.

• Multichannel capability — Each SPORT supports 128 channels out of a 1024-channel window and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The processors have an SPI-compatible port that enables the processor to communicate with multiple SPI-compatible devices.

The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSI, and Master InputSlave Output, MISO) and a clock pin (serial clock, SCK). An SPI chip select input pin (SPISS processor, and seven SPI chip select output pins (SPISEL7–1 the processor select other SPI devices. The SPI select pins are reconfigured general-purpose I/O pins. Using these pins, the SPI port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments.

The SPI port’s baud rate and clock phase/polarities are programmable, and it has an integrated DMA channel, configurable to support transmit or receive data streams. The SPI’s DMA channel can only service unidirectional accesses at any given time.

) lets other SPI devices select the

) let

The SPI port’s clock rate is calculated as:

Where the 16-bit SPI_BAUD register contains a value of 2 to 65,535.

During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.

UART PORTS

The processors provide two full-duplex universal asynchronous receiver/transmitter (UART) ports, which are fully compatible with PC-standard UARTs. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port includes support for five to eight data bits, one or two stop bits, and none, even, or odd parity. Each UART port supports two modes of operation:

• PIO (programmed I/O) — The processor sends or receives data by writing or reading I/O mapped UART registers. The data is double-buffered on both transmit and receive.

• DMA (direct memory access) — The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates.

Each UART port's baud rate, serial data format, error code generation and status, and interrupts are programmable:

• Supporting bit rates ranging from (f

/16) bits per second.

SCLK

• Supporting data formats from seven to 12 bits per frame.

• Both transmit and receive operations can be configured to generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as:

Where the 16-bit UART_Divisor comes from the UART_DLH (most significant 8 bits) and UART_DLL (least significant 8 bits) registers.

In conjunction with the general-purpose timer functions, autobaud detection is supported.

The capabilities of the UARTs are further extended with support for the infrared data association (IrDA®) serial infrared physical layer link specification (SIR) protocol.

/1,048,576) to

SCLK

Rev. C | Page 11 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

TWI CONTROLLER INTERFACE

The processors include a 2-wire interface (TWI) module for providing a simple exchange method of control data between multiple devices. The TWI is compatible with the widely used

2C®

bus standard. The TWI module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two pins for transferring clock (SCL) and data (SDA) and supports the protocol at speeds up to 400k bits/sec. The TWI interface pins are compatible with 5 V logic levels.

Additionally, the TWI module is fully compatible with serial camera control bus (SCCB) functionality for easier control of various CMOS camera sensor devices.

10/100 ETHERNET MAC

The ADSP-BF526 and ADSP-BF527 processors offer the capability to directly connect to a network by way of an embedded Fast Ethernet Media Access Controller (MAC) that supports both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec) operation. The 10/100 Ethernet MAC peripheral on the processor is fully compliant to the IEEE 802.3-2002 standard and it provides programmable features designed to minimize supervision, bus use, or message processing by the rest of the processor system.

Some standard features are:

• Support of MII and RMII protocols for external PHYs.

• Full duplex and half duplex modes.

• Data framing and encapsulation: generation and detection of preamble, length padding, and FCS.

• Media access management (in half-duplex operation): collision and contention handling, including control of retransmission of collision frames and of back-off timing.

• Flow control (in full-duplex operation): generation and detection of PAUSE frames.

• Station management: generation of MDC/MDIO frames for read-write access to PHY registers.

• Operating range for active and sleep operating modes, see

Table 58 on Page 67 and Table 59 on Page 67.

• Internal loopback from Tx to Rx.

Some advanced features are:

• Buffered crystal output to external PHY for support of a single crystal system.

• Automatic checksum computation of IP header and IP payload fields of Rx frames.

• Independent 32-bit descriptor-driven Rx and Tx DMA channels.

• Frame status delivery to memory via DMA, including frame completion semaphores, for efficient buffer queue management in software.

• Tx DMA support for separate descriptors for MAC header and payload to eliminate buffer copy operations.

• Convenient frame alignment modes support even 32-bit alignment of encapsulated Rx or Tx IP packet data in memory after the 14-byte MAC header.

• Programmable Ethernet event interrupt supports any combination of:

• Any selected Rx or Tx frame status conditions.

• PHY interrupt condition.

• Wake-up frame detected.

• Any selected MAC management counter(s) at halffull.

• DMA descriptor error.

• 47 MAC management statistics counters with selectable clear-on-read behavior and programmable interrupts on half maximum value.

• Programmable Rx address filters, including a 64-bin address hash table for multicast and/or unicast frames, and programmable filter modes for broadcast, multicast, unicast, control, and damaged frames.

• Advanced power management supporting unattended transfer of Rx and Tx frames and status to/from external memory via DMA during low power sleep mode.

• System wakeup from sleep operating mode upon magic packet or any of four user-definable wakeup frame filters.

• Support for 802.3Q tagged VLAN frames.

• Programmable MDC clock rate and preamble suppression.

• In RMII operation, seven unused pins may be configured as GPIO pins for other purposes.

PORTS

Because of the rich set of peripherals, the processor groups the many peripheral signals to four ports—Port F, Port G, Port H, and Port J. Most of the associated pins are shared by multiple signals. The ports function as multiplexer controls.

General-Purpose I/O (GPIO)

The processor has 48 bidirectional, general-purpose I/O (GPIO) pins allocated across three separate GPIO modules—PORTFIO, PORTGIO, and PORTHIO, associated with Port F, Port G, and Port H, respectively. Port J does not provide GPIO functionality. Each GPIO-capable pin shares functionality with other processor peripherals via a multiplexing scheme; however, the GPIO functionality is the default state of the device upon power-up. Neither GPIO output nor input drivers are active by default. Each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers:

• GPIO direction control register — Specifies the direction of each individual GPIO pin as input or output.

• GPIO control and status registers — The processor employs a “write one to modify” mechanism that allows any combination of individual GPIO pins to be modified in a single instruction, without affecting the level of any other GPIO pins. Four control registers are provided. One regis-

Rev. C | Page 12 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

ter is written in order to set pin values, one register is written in order to clear pin values, one register is written in order to toggle pin values, and one register is written in order to specify a pin value. Reading the GPIO status register allows software to interrogate the sense of the pins.

• GPIO interrupt mask registers — The two GPIO interrupt mask registers allow each individual GPIO pin to function as an interrupt to the processor. Similar to the two GPIO control registers that are used to set and clear individual pin values, one GPIO interrupt mask register sets bits to enable interrupt function, and the other GPIO interrupt mask register clears bits to disable interrupt function. GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts.

• GPIO interrupt sensitivity registers — The two GPIO interrupt sensitivity registers specify whether individual pins are level- or edge-sensitive and specify—if edge-sensitive— whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity.

PARALLEL PERIPHERAL INTERFACE (PPI)

The processor provides a parallel peripheral interface (PPI) that can connect directly to parallel analog-to-digital and digital-toanalog converters, video encoders and decoders, and other general-purpose peripherals. The PPI consists of a dedicated input clock pin, up to three frame synchronization pins, and up to 16 data pins. The input clock supports parallel data rates up to half the system clock rate, and the synchronization signals can be configured as either inputs or outputs.

The PPI supports a variety of general-purpose and ITU-R 656 modes of operation. In general-purpose mode, the PPI provides half-duplex, bidirectional data transfer with up to 16 bits of data. Up to three frame synchronization signals are also provided. In ITU-R 656 mode, the PPI provides half-duplex bidirectional transfer of 8- or 10-bit video data. Additionally, on-chip decode of embedded start-of-line (SOL) and start-offield (SOF) preamble packets is supported.

General-Purpose Mode Descriptions

The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. Three distinct submodes are supported:

1. Input mode — Frame syncs and data are inputs into the PPI.

2. Frame capture mode — Frame syncs are outputs from the PPI, but data are inputs.

3. Output mode — Frame syncs and data are outputs from the PPI.

Input Mode

Input mode is intended for ADC applications, as well as video communication with hardware signaling. In its simplest form, PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in PPI_CLK cycles) between reception of this frame sync and the initiation of data reads. The number of input data samples is user programmable and defined by the contents of the PPI_COUNT register. The PPI supports 8-bit and 10-bit through 16-bit data, programmable in the PPI_CONTROL register.

Frame Capture Mode

Frame capture mode allows the video source(s) to act as a slave (for frame capture for example). The ADSP-BF52x processors control when to read from the video source(s). PPI_FS1 is an HSYNC output, and PPI_FS2 is a VSYNC output.

Output Mode

Output mode is used for transmitting video or other data with up to three output frame syncs. Typically, a single frame sync is appropriate for data converter applications, whereas two or three frame syncs could be used for sending video with hardware signaling.

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide variety of video capture, processing, and transmission applications. Three distinct submodes are supported:

1. Active video only mode

2. Vertical blanking only mode

3. Entire field mode

Active Video Mode

Active video only mode is used when only the active video portion of a field is of interest and not any of the blanking intervals. The PPI does not read in any data between the end of active video (EAV) and start of active video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI. After synchronizing to the start of Field 1, the PPI ignores incoming samples until it sees an SAV code. The user specifies the number of active video lines per frame (in PPI_COUNT register).

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval (VBI) data.

Entire Field Mode

In this mode, the entire incoming bit stream is read in through the PPI. This includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after synchronization to Field 1. Data is transferred to or from the synchronous channels through eight DMA engines that work autonomously from the processor core.

Rev. C | Page 13 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

USB ON-THE-GO DUAL-ROLE DEVICE CONTROLLER

The USB OTG dual-role device controller (USBDRC) provides a low-cost connectivity solution for consumer mobile devices such as cell phones, digital still cameras, and MP3 players, allowing these devices to transfer data using a point-to-point USB connection without the need for a PC host. The USBDRC module can operate in a traditional USB peripheral-only mode as well as the host mode presented in the On-the-Go (OTG) supplement to the USB 2.0 specification. In host mode, the USB module supports transfers at high speed (480 Mbps), full speed (12 Mbps), and low speed (1.5 Mbps) rates. Peripheral-only mode supports the high- and full-speed transfer rates.

The USB clock (USB_XI) is provided through a dedicated external crystal or crystal oscillator. See Universal Serial Bus (USB)

On-The-Go—Receive and Transmit Timing on Page 59 for

related timing requirements. If using a crystal to provide the USB clock, use a parallel-resonant, fundamental mode, microprocessor-grade crystal.

The USB on-the-go dual-role device controller includes a phase locked loop with programmable multipliers to generate the necessary internal clocking frequency for USB. The multiplier value should be programmed based on the USB_XI frequency to achieve the necessary 480 MHz internal clock for USB high speed operation. For example, for a USB_XI crystal frequency of 24 MHz, the USB_PLLOSC_CTRL register should be programmed with a multiplier value of 20 to generate a 480 MHz internal clock.

CODE SECURITY WITH LOCKBOX SECURE TE CH N O LO G Y

A security system consisting of a blend of hardware and software provides customers with a flexible and rich set of code security features with Lockbox tures include:

•OTP memory

• Unique chip ID

• Code authentication

• Secure mode of operation

The security scheme is based upon the concept of authentication of digital signatures using standards-based algorithms and provides a secure processing environment in which to execute code and protect assets. See Lockbox Secure Technology Dis-

claimer on Page 21.

Secure Technology. Key fea-

DYNAMIC POWER MANAGEMENT

The processor provides five operating modes, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. When configured for a 0 V core supply voltage, the processor enters the hibernate state. Control of clocking to each of the processor peripherals also reduces power consumption.

See Table 4 for a summary of the power settings for each mode.

Table 4. Power Settings

Core

PLL

Mode/State PLL

Full-On Enabled No Enabled Enabled On Active Enabled/

Disabled Sleep Enabled — Disabled Enabled On Deep Sleep Disabled — Disabled Disabled On Hibernate Disabled — Disabled Disabled Off

Bypassed

Yes E na bl ed E na bl ed O n

Clock (CCLK)

System Clock (SCLK)

Core Power

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled peripherals run at full speed.

Active Operating Mode—Moderate Dynamic Power Savings

In the active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. DMA access is available to appropriately configured L1 memories.

In the active mode, it is possible to disable the control input to the PLL by setting the PLL_OFF bit in the PLL control register. This register can be accessed with a user-callable routine in the on-chip ROM called bfrom_SysControl(). If disabled, the PLL control input must be re-enabled before transitioning to the full-on or sleep modes.

For more information about PLL controls, see the “Dynamic Power Management” chapter in the ADSP-BF52x Blackfin Processor Hardware Reference.

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK). The PLL and system clock (SCLK), however, continue to operate in this mode. Typically, an external event or RTC activity wakes up the processor. When in the sleep mode, asserting a wakeup enabled in the SIC_IWRx registers causes the processor to sense the value of the BYPASS bit in the PLL control register (PLL_CTL). If BYPASS is disabled, the processor transitions to the full-on mode. If BYPASS is enabled, the processor transitions to the active mode.

System DMA access to L1 memory is not supported in sleep mode.

Deep Sleep Operating Mode—Maximum Dynamic Power Savings

The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals,

Rev. C | Page 14 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Power Savings Factor

CCLKRED

CCLKNOM

--------------------------

DDINTRED

DDINTNOM

--------------------------------





RED

NOM

---------------









= % Power Savings 1 Power Savings Factor–()100%×=

such as the RTC, may still be running but cannot access internal resources or external memory. This powered-down mode can only be exited by assertion of the reset interrupt (RESET

) or by an asynchronous interrupt generated by the RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the Active mode. Assertion of RESET

while in deep sleep mode causes the processor to transition to the full on mode.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all of the synchronous peripherals (SCLK). The internal voltage regulator (ADSP-BF523/ADSP-BF525/ADSP-BF527 only) for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register, using the bfrom_SysControl() function. This setting sets the internal power supply voltage (V

DDINT

) to 0 V to provide the lowest static power dissipation. Any critical information stored internally (for example, memory contents, register contents, and other information) must be written to a non volatile storage device prior to removing power if the processor state is to be preserved. Writing b#00 to the FREQ bits also causes EXT_WAKE0 and EXT_WAKE1 to transition low, which can be used to signal an external voltage regulator to shut down.

Since V

DDEXT

and V

can still be supplied in this mode, all

DDMEM

of the external pins three-state, unless otherwise specified. This allows other devices that may be connected to the processor to still have power applied without drawing unwanted current.

The Ethernet or USB modules can wake up the internal supply regulator (ADSP-BF525 and ADSP-BF527 only) or signal an external regulator to wake up using EXT_WAKE0 or EXT_WAKE1. If PG15 does not connect as a PHYINT

signal to an external PHY device, PG15 can be pulled low by any other device to wake the processor up. The processor can also be woken up by a real-time clock wakeup event or by asserting the

pin. All hibernate wake-up events initiate the hardware

RESET reset sequence. Individual sources are enabled by the VR_CTL register. The EXT_WAKEx signals are provided to indicate the occurrence of wake-up events.

As long as V

is applied, the VR_CTL register maintains its

DDEXT

state during hibernation. All other internal registers and memories, however, lose their content in the hibernate state. State variables may be held in external SRAM or SDRAM. The SCKELOW bit in the VR_CTL register controls whether or not SDRAM operates in self-refresh mode, which allows it to retain its content while the processor is in hibernate and through the subsequent reset sequence.

ments for the various power domains, but all domains must be powered according to the appropriate Specifications table for processor Operating Conditions; even if the feature/peripheral is not used.

Table 5. Power Domains

Power Domain VDD Range

All internal logic, except RTC, Memory, USB, OTP V RTC internal logic and crystal I/O V Memory logic V USB PHY logic V OTP logic V All other I/O V

DDINT

DDRTC

DDMEM

DDUSB

DDOTP

DDEXT

The dynamic power management feature of the processor allows both the processor’s input voltage (V quency (f

) to be dynamically controlled.

CCLK

) and clock fre-

DDINT

The power dissipated by a processor is largely a function of its clock frequency and the square of the operating voltage. For example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. Further, these power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic, as shown in the following equations.

where the variables in the equations are:

is the nominal core clock frequency

CCLKNOM

is the reduced core clock frequency

CCLKRED

DDINTNOM

DDINTRED

NOM

RED

is the nominal internal supply voltage

is the reduced internal supply voltage

is the duration running at f

CCLKNOM

CCLKRED

Power Savings

As shown in Table 5, the processor supports six different power domains, which maximizes flexibility while maintaining compliance with industry standards and conventions. By isolating the internal logic of the processor into its own power domain, separate from the RTC and other I/O, the processor can take advantage of dynamic power management without affecting the RTC or other I/O devices. There are no sequencing require-

Rev. C | Page 15 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

DDEXT

(LOW-INDUCTANCE)

DDINT

100μF

OUT

EXT_WAKE1

GND

SHORT AND LOW-

INDUCTANCE WIRE

DDEXT

100μF

10μF

LOW ESR

100nF

SET OF DECOUPLING

CAPACITORS

FDS9431A

ZHCS1000

2.25V TO 3.6V INPUT VOLTAGE RANGE

NOTE: DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.

10μH

SEL

SS/PG

SEE H/W REFERENCE, SYSTEM DESIGN CHAPTER, TO DETERMINE VALUE

ADSP-BF523/ADSP-BF525/ADSP-BF527 VOLTAGE REGULATION

The ADSP-BF523/ADSP-BF525/ADSP-BF527 provides an onchip voltage regulator that can generate processor core voltage levels from an external supply. Figure 5 shows the typical external components required to complete the power management system.

Figure 5. ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulator Circuit

The regulator controls the internal logic voltage levels and is programmable with the voltage regulator control register (VR_CTL) in increments of 50 mV. This register can be accessed using the bfrom_SysControl() function in the on-chip ROM. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power supplied. While in the hibernate state, all external supplies (V V

) can still be applied, eliminating the need for external

DDOTP

buffers. V

must be applied at all times for correct hibernate

DDRTC

operation. The voltage regulator can be activated from this power-down state either through an RTC wakeup, a USB wakeup, an ethernet wake-up, or by asserting the RESET which then initiates a boot sequence. The regulator can also be disabled and bypassed at the user’s discretion.

The voltage regulator has two modes set by the VR normal pulse width control of an external FET and the external supply mode which can signal a power down during hibernate to an external regulator. Set VR regulator or set VR the external mode VR regulator is used, EXT_WAKE0 can control other power sources in the system during the hibernate state. Both signals are high-true for power-up and may be connected directly to the low-true shutdown input of many common regulators. The mode of the SS/PG according to the state of VR tor, the SS/PG

pin is Soft Start, and when using an external

to V

to GND to use the internal regulator. In

SEL

OUT

(Soft Start/Power Good) signal also changes

SEL

becomes EXT_WAKE1. If the internal

. When using an internal regula-

SEL

, V

DDEXT

DDMEM

to use an external

, V

DDUSB

pin, each of

pin—the

SEL

Rev. C | Page 16 of 88 | March 2012

regulator, it is Power Good. The Soft Start feature is recommended to reduce the inrush currents and to reduce V

DDINT

voltage overshoot when coming out of hibernate or changing voltage levels. The Power Good (PG

) input signal allows the processor to start only after the internal voltage has reached a chosen level. In this way, the startup time of the external regulator is detected after hibernation. For a complete description of Soft Start and Power Good functionality, refer to the ADSP-BF52x Blackfin Processor Hardware Reference.

ADSP-BF522/ADSP-BF524/ADSP-BF526 VOLTAGE REGULATION

The ADSP-BF522/ADSP-BF524/ADSP-BF526 processor requires an external voltage regulator to power the V

DDINT

domain. To reduce standby power consumption, the external voltage regulator can be signaled through EXT_WAKE0 or EXT_WAKE1 to remove power from the processor core. These identical signals are high-true for power-up and may be connected directly to the low-true shut down input of many common regulators. While in the hibernate state, all external supplies (V

DDEXT

, V

eliminating the need for external buffers. V

DDMEM

, V

DDUSB

, V

) can still be applied,

DDOTP

DDRTC

must be applied at all times for correct hibernate operation. The external voltage regulator can be activated from this power down state either through an RTC wakeup, a USB wakeup, an ethernet wakeup, or by asserting the RESET

pin, each of which then initiates a boot sequence. EXT_WAKE0 or EXT_WAKE1 indicate a wakeup to the external voltage regulator. The Power Good (PG input signal allows the processor to start only after the internal voltage has reached a chosen level. In this way, the startup time of the external regulator is detected after hibernation. For a complete description of the Power Good functionality, refer to the ADSP-BF52x Blackfin Processor Hardware Reference.

CLOCK SIGNALS

The processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator.

If an external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is connected to the processor’s CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected.

Alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. For fundamental frequency operation, use the circuit shown in Figure 6. A parallel-resonant, fundamental frequency, microprocessorgrade crystal is connected across the CLKIN and XTAL pins. The on-chip resistance between CLKIN and the XTAL pin is in the 500 k range. Further parallel resistors are typically not recommended. The two capacitors and the series resistor shown in

Figure 6 fine tune phase and amplitude of the sine frequency.

The capacitor and resistor values shown in Figure 6 are typical values only. The capacitor values are dependent upon the crystal manufacturers’ load capacitance recommendations and the PCB physical layout. The resistor value depends on the drive level

)

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

CLKIN

CLKOUT

XTAL

CLKBUF

TO PLL CIRCUITRY

FOR OVERTONE OPERATION ONLY:

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR FREQUENCIES ABOVE 33 MHz, THE SUGGE STED CAPACITOR VALUE OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀.

18 pF *

330 ⍀*

BLACKFIN

560 ⍀

PLL

to 64u

÷1to15

÷1,2,4,8

VCO

CLKIN

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

CCLK

SCLK

SCLK d CCLK

specified by the crystal manufacturer. The user should verify the customized values based on careful investigations on multiple devices over temperature range.

Figure 6. External Crystal Connections

A third-overtone crystal can be used for frequencies above 25 MHz. The circuit is then modified to ensure crystal operation only at the third overtone by adding a tuned inductor circuit as shown in Figure 6. A design procedure for third-overtone operation is discussed in detail in application note (EE-168) Using Third Overtone Crystals with the ADSP-218x DSP on the Analog Devices website (www.analog.com)—use site search on “EE-168.”

The CLKBUF pin is an output pin, which is a buffered version of the input clock. This pin is particularly useful in Ethernet applications to limit the number of required clock sources in the system. In this type of application, a single 25 MHz or 50 MHz crystal may be applied directly to the processor. The 25 MHz or 50 MHz output of CLKBUF can then be connected to an external Ethernet MII or RMII PHY device. If, instead of a crystal, an external oscillator is used at CLKIN, CLKBUF will not have the 40/60 duty cycle required by some devices. The CLKBUF output is active by default and can be disabled for power savings reasons using the VR_CTL register.

The Blackfin core runs at a different clock rate than the on-chip peripherals. As shown in Figure 7, the core clock (CCLK) and system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying the CLKIN signal by a programmable multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier can be modified by a software instruction sequence. This sequence is managed by the bfrom_SysControl() function in the on-chip ROM.

On-the-fly CCLK and SCLK frequency changes can be applied by using the bfrom_SysControl() function in the on-chip ROM. The maximum allowed CCLK and SCLK rates depend on the applied voltages V

, V

DDINT

DDEXT

, and V

DDMEM

; the VCO is always

Rev. C | Page 17 of 88 | March 2012

permitted to run up to the frequency specified by the part’s maximum instruction rate. The CLKOUT pin reflects the SCLK frequency to the off-chip world. It is part of the SDRAM interface, but it functions as a reference signal in other timing specifications as well. While active by default, it can be disabled using the EBIU_SDGCTL and EBIU_AMGCTL registers.

Figure 7. Frequency Modification Methods

All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3–0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of f

. The SSEL value can be

SCLK

dynamically changed without any PLL lock latencies by writing the appropriate values to the PLL divisor register (PLL_DIV) using the bfrom_SysControl() function in the on-chip ROM.

Table 6. Example System Clock Ratios

Example Frequency Ratios

Signal Name SSEL3–0

Divider Ratio VCO/SCLK

VCO SCLK

(MHz)

0001 1:1 100 100 0110 6:1 300 50 1010 10:1 500 50

The core clock (CCLK) frequency can also be dynamically changed by means of the CSEL1–0 bits of the PLL_DIV register. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

Table 7. Core Clock Ratios

Example Frequency Ratios

Signal Name CSEL1–0

Divider Ratio VCO/CCLK

VCO CCLK

(MHz)

00 1:1 300 300 01 2:1 300 150 10 4:1 500 125 11 8:1 200 25

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

The maximum CCLK frequency not only depends on the part's maximum instruction rate (see Page 87). This frequency also depends on the applied V

voltage. See Table 12 and

DDINT

Table 15 for details. The maximal system clock rate (SCLK)

depends on the chip package and the applied V and V

voltages (see Table 14 and Table 17).

DDMEM

DDINT

, V

DDEXT

BOOTING MODES

The processor has several mechanisms (listed in Table 8) for automatically loading internal and external memory after a reset. The boot mode is defined by four BMODE input pins dedicated to this purpose. There are two categories of boot modes. In master boot modes the processor actively loads data from parallel or serial memories. In slave boot modes the processor receives data from external host devices.

The boot modes listed in Table 8 provide a number of mechanisms for automatically loading the processor’s internal and external memories after a reset. By default, all boot modes use the slowest meaningful configuration settings. Default settings can be altered via the initialization code feature at boot time or by proper OTP programming at pre-boot time. The BMODE pins of the reset configuration register, sampled during poweron resets and software-initiated resets, implement the modes shown in Table 8.

Table 8. Booting Modes

BMODE3–0 Description

0000 Idle — No boot 0001 Boot from 8- or 16-bit external flash memory 0010 Boot from 16-bit asynchronous FIFO 0011 Boot from serial SPI memory (EEPROM or flash) 0100 Boot from SPI host device 0101 Boot from serial TWI memory (EEPROM/flash) 0110 Boot from TWI host 0111 Boot from UART0 Host 1000 Boot from UART1 Host 1001 Reserved 1010 Boot from SDRAM 1011 Boot from OTP memory 1100 Boot from 8-bit NAND flash

via NFC using PORTF data pins

1101 Boot from 8-bit NAND flash

via NFC using PORTH data pins 1110 Boot from 16-Bit Host DMA 1111 Boot from 8-Bit Host DMA

• Idle/no boot mode (BMODE = 0x0) — In this mode, the processor goes into idle. The idle boot mode helps recover from illegal operating modes, such as when the OTP memory has been misconfigured.

• Boot from 8-bit or 16-bit external flash memory (BMODE = 0x1) — In this mode, the boot kernel loads the first block header from address 0x2000 0000, and (depending on instructions contained in the header) the boot

kernel performs an 8- or 16-bit boot or starts program execution at the address provided by the header. By default, all configuration settings are set for the slowest device possible (3-cycle hold time, 15-cycle R/W access times, 4-cycle setup).

The ARDY is not enabled by default, but it can be enabled through OTP programming. Similarly, all interface behavior and timings can be customized through OTP programming. This includes activation of burst-mode or page-mode operation. In this mode, all asynchronous interface signals are enabled at the port muxing level.

• Boot from 16-bit asynchronous FIFO (BMODE = 0x2) — In this mode, the boot kernel starts booting from address 0x2030 0000. Every 16-bit word that the boot kernel has to read from the FIFO must be requested by placing a low pulse on the DMAR1 pin.

• Boot from serial SPI memory, EEPROM or flash (BMODE = 0x3) — 8-, 16-, 24-, or 32-bit addressable devices are supported. The processor uses the PG1 GPIO pin to select a single SPI EEPROM/flash device and submits a read command and successive address bytes (0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device is detected. Pull-up resistors are required on the SPISEL1

and MISO pins. By default, a value of 0x85 is written to the SPI_BAUD register.

• Boot from SPI host device (BMODE = 0x4) — The processor operates in SPI slave mode and is configured to receive the bytes of the LDR file from an SPI host (master) agent. The HWAIT signal must be interrogated by the host before every transmitted byte. A pull-up resistor is required on the SPISS

input. A pull-down on the serial clock (SCK) may

improve signal quality and booting robustness.

• Boot from serial TWI memory, EEPROM/flash (BMODE = 0x5) — The processor operates in master mode and selects the TWI slave connected to the TWI with the unique ID 0xA0.

The processor submits successive read commands to the memory device starting at internal address 0x0000 and begins clocking data into the processor. The TWI memory device should comply with the Philips I

2C®

Bus Specification version 2.1 and should be able to auto-increment its internal address counter such that the contents of the memory device can be read sequentially. By default, a PRESCALE value of 0xA and a TWI_CLKDIV value of 0x0811 are used. Unless altered by OTP settings, an I

C memory that takes two address bytes is assumed. The development tools ensure that data booted to memories that cannot be accessed by the Blackfin core is written to an intermediate storage location and then copied to the final destination via memory DMA.

• Boot from TWI host (BMODE = 0x6) — The TWI host selects the slave with the unique ID 0x5F.

The processor replies with an acknowledgement and the host then downloads the boot stream. The TWI host agent should comply with the Philips I

C Bus Specification

Rev. C | Page 18 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

version 2.1. An I2C multiplexer can be used to select one processor at a time when booting multiple processors from a single TWI.

• Boot from UART0 host on Port G (BMODE = 0x7) — Using an autobaud handshake sequence, a boot-stream formatted program is downloaded by the host. The host selects a bit rate within the UART clocking capabilities.

When performing the autobaud, the UART expects a “@” (0x40) character (eight bits data, one start bit, one stop bit, no parity bit) on the UART0RX pin to determine the bit rate. The UART then replies with an acknowledgement composed of 4 bytes (0xBF, the value of UART0_DLL, the value of UART0_DLH, then 0x00). The host can then download the boot stream. To hold off the host the Blackfin processor signals the host with the boot host wait (HWAIT) signal. Therefore, the host must monitor HWAIT before every transmitted byte.

• Boot from UART1 host on Port F (BMODE = 0x8). Same as BMODE = 0x7 except that the UART1 port is used.

• Boot from SDRAM (BMODE = 0xA) This is a warm boot scenario, where the boot kernel starts booting from address 0x0000 0010. The SDRAM is expected to contain a valid boot stream and the SDRAM controller must be configured by the OTP settings.

• Boot from OTP memory (BMODE = 0xB) — This provides a stand-alone booting method. The boot stream is loaded from on-chip OTP memory. By default, the boot stream is expected to start from OTP page 0x40 and can occupy all public OTP memory up to page 0xDF. This is 2560 bytes. Since the start page is programmable, the maximum size of the boot stream can be extended to 3072 bytes.

• Boot from 8-bit external NAND flash memory (BMODE = 0xC and BMODE = 0xD) — In this mode, auto detection of the NAND flash device is performed.

BMODE = 0xC, the processor configures PORTF GPIO pins PF7:0 for the NAND data pins and PORTH pins PH15:10 for the NAND control signals.

BMODE = 0xD, the processor configures PORTH GPIO pins PH7:0 for the NAND data pins and PORTH pins PH15:10 for the NAND control signals.

For correct device operation pull-up resistors are required on both ND_CE default, a value of 0x0033 is written to the NFC_CTL register. The booting procedure always starts by booting from byte 0 of block 0 of the NAND flash device.

NAND flash boot supports the following features:

—Device Auto Detection

—Error Detection & Correction for maximum reliability

—No boot stream size limitation

—Peripheral DMA providing efficient transfer of all data

(excluding the ECC parity data)

(PH10) and ND_BUSY (PH13) signals. By

—Software-configurable boot mode for booting from

boot streams spanning multiple blocks, including bad blocks

—Software-configurable boot mode for booting from

multiple copies of the boot stream, allowing for handling of bad blocks and uncorrectable errors

—Configurable timing via OTP memory

Small page NAND flash devices must have a 512-byte page size, 32 pages per block, a 16-byte spare area size, and a bus configuration of 8 bits. By default, all read requests from the NAND flash are followed by four address cycles. If the NAND flash device requires only three address cycles, the device must be capable of ignoring the additional address cycles.

The small page NAND flash device must comply with the following command set:

—Reset: 0xFF

—Read lower half of page: 0x00

—Read upper half of page: 0x01

—Read spare area: 0x50

For large-page NAND-flash devices, the four-byte electronic signature is read in order to configure the kernel for booting, which allows support for multiple large-page devices. The fourth byte of the electronic signature must comply with the specification in Table 9 on Page 20.

Any NAND flash array configuration from Table 9, excluding 16-bit devices, that also complies with the command set listed below are directly supported by the boot kernel. There are no restrictions on the page size or block size as imposed by the small-page boot kernel.

For devices consisting of a five-byte signature, only four are read. The fourth must comply as outlined above.

Large page devices must support the following command set:

—Reset: 0xFF

—Read Electronic Signature: 0x90

—Read: 0x00, 0x30 (confirm command)

Large-page devices must not support or react to NAND flash command 0x50. This is a small-page NAND flash command used for device auto detection.

By default, the boot kernel will always issue five address cycles; therefore, if a large page device requires only four cycles, the device must be capable of ignoring the additional address cycles.

• Boot from 16-Bit Host DMA (BMODE = 0xE) — In this mode, the host DMA port is configured in 16-bit Acknowledge mode, with little endian data formatting. Unlike other modes, the host is responsible for interpreting the boot stream. It writes data blocks individually into the Host DMA port. Before configuring the DMA settings for each block, the host may either poll the ALLOW_CONFIG bit in HOST_STATUS or wait to be interrupted by the HWAIT

Rev. C | Page 19 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

signal. When using HWAIT, the host must still check ALLOW_CONFIG at least once before beginning to configure the Host DMA Port. After completing the configuration, the host is required to poll the READY bit in HOST_STATUS before beginning to transfer data. When the host sends an HIRQ control command, the boot kernel issues a CALL instruction to address 0xFFA0 0000. It is the host's responsibility to ensure that valid code has been placed at this address. The routine at 0xFFA0 0000 can be a simple initialization routine to configure internal resources, such as the SDRAM controller, which then returns using an RTS instruction. The routine may also by the final application, which will never return to the boot kernel.

• Boot from 8-Bit Host DMA (BMODE = 0xF) — In this mode, the Host DMA port is configured in 8-bit interrupt mode, with little endian data formatting. Unlike other modes, the host is responsible for interpreting the boot stream. It writes data blocks individually into the Host DMA port. Before configuring the DMA settings for each block, the host may either poll the ALLOW_CONFIG bit in HOST_STATUS or wait to be interrupted by the HWAIT signal. When using HWAIT, the host must still check ALLOW_CONFIG at least once before beginning to configure the Host DMA Port. The host will receive an interrupt from the HOST_ACK signal every time it is allowed to send the next FIFO depths worth (sixteen 32-bit words) of information. When the host sends an HIRQ control command, the boot kernel issues a CALL instruction to address 0xFFA0 0000. It is the host's responsibility to ensure valid code has been placed at this address. The routine at 0xFFA0 0000 can be a simple initialization routine to configure internal resources, such as the SDRAM controller, which then returns using an RTS instruction. The routine may also by the final application, which will never return to the boot kernel.

Table 9. Fourth Byte for Large Page Devices

Bit Parameter Value Meaning

D1:D0 Page Size

(excluding spare area)

D2 Spare Area Size 00018 byte/512 byte

D5:D4 Block Size

(excluding spare area)

D6 Bus width 00

D3, D7 Not Used for configuration

00 01 10 11

16 byte/512 byte

00 01 10 11

1K byte 2K byte 4K byte 8K byte

64K byte 128K byte 256K byte 512K byte

not supported

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor resources.

The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/MCU features are optimized for both 8-bit and 16-bit operations.

• A multi-issue load/store modified-Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified programming model.

• Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and supervisor stack pointers.

• Code density enhancements, which include intermixing of 16-bit and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits.

DEVELOPMENT TOOLS

The processor is supported with a complete set of CROSSCORE® software and hardware development tools, including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that supports other Blackfin processors also fully emulates the ADSP-BF52x processors.

EZ-KIT Lite Evaluation Board

For evaluation of ADSP-BF52x processors, use the EZ-KIT Lite® boards available from Analog Devices. Order using part numbers ADZS-BF526-EZLITE or ADZS-BF527-EZLITE. The boards come with on-chip emulation capabilities and are equipped to enable software development. Multiple daughter cards are available.

DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD (TARGET)

The Analog Devices family of emulators are tools that every system developer needs in order to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1

Rev. C | Page 20 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

JTAG Test Access Port (TAP) on each JTAG processor. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see (EE-68) Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)— use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support.

LOCKBOX SECURE TECHNOLOGY DISCLAIMER

Analog Devices products containing Lockbox Secure Technology are warranted by Analog Devices as detailed in the Analog Devices Standard Terms and Conditions of Sale. To our knowledge, the Lockbox Secure Technology, when used in accordance with the data sheet and hardware reference manual specifications, provides a secure method of implementing code and data safeguards. However, Analog Devices does not guarantee that this technology provides absolute security.

ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES THAT THE LOCKBOX SECURE TECHNOLOGY CANNOT BE BREACHED, COMPROMISED, OR OTHERWISE CIRCUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF DATA, INFORMATION, PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY.

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the “signal chain” entry in

Wikipedia or the Glossary of EE Terms on the Analog Devices

website.

Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the

www.analog.com website.

Rev. C | Page 21 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

SIGNAL DESCRIPTIONS

Signal definitions for the ADSP-BF52x processors are listed in

Table 10. In order to maintain maximum function and reduce

package size and ball count, some balls have dual, multiplexed functions. In cases where ball function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics.

All pins are three-stated during and immediately after reset, with the exception of the external memory interface, asynchronous and synchronous memory control, and the buffered XTAL output pin (CLKBUF). On the external memory interface, the control and address lines are driven high, with the exception of CLKOUT, which toggles at the system clock rate. During hibernate, all outputs are three-stated unless otherwise noted in

Table 10.

All I/O pins have their input buffers disabled with the exception of the pins that need pull-ups or pull-downs, as noted in

Table 10.

It is strongly advised to use the available IBIS models to ensure that a given board design meets overshoot/undershoot and signal integrity requirements. If no IBIS simulation is performed, it is strongly recommended to add series resistor terminations for all Driver Types A, C and D.

The termination resistors should be placed near the processor to reduce transients and improve signal integrity. The resistance value, typically 33 Ω or 47 Ω, should be chosen to match the average board trace impedance.

Additionally, adding a parallel termination to CLKOUT may prove useful in further enhancing signal integrity. Be sure to verify overshoot/undershoot and signal integrity specifications on actual hardware.

Table 10. Signal Descriptions

Signal Name Type Function

EBIU

ADDR19–1 O Address Bus A

DATA15–0 I/O Data Bus A

/SDQM1–0 O Byte Enables/Data Mask A

ABE1–0

AMS3–0 O Asynchronous Memory Bank Selects (Require pull-ups if hibernate is used.) A

ARDY I Hardware Ready Control

AOE

ARE

AWE O Asynchronous Write Enable A

SRAS

SCAS

SWE

SCKE O SDRAM Clock Enable (Requires a pull-down if hibernate with SDRAM self-

CLKOUT O SDRAM Clock Output B

SA10 O SDRAM A10 Signal A

SMS

O Asynchronous Output Enable A

O Asynchronous Read Enable A

O SDRAM Row Address Strobe A

O SDRAM Column Address Strobe A

OSDRAM Write Enable A

refresh is used.)

O SDRAM Bank Select A

Driver Typ e

Rev. C | Page 22 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 10. Signal Descriptions (Continued)

Driver

Signal Name Type Function

USB 2.0 HS OTG

USB_DP I/O Data + (This ball should be pulled low when USB is unused or not present.) F

USB_DM I/O Data – (This ball should be pulled low when USB is unused or not present.) F

USB_XI I USB Crystal Input (This ball should be pulled low when USB is unused or not

present.)

USB_XO O USB Crystal Output ( This ball should be left unconnected when USB is unused

or not present.)

USB_ID I USB OTG mode (This ball should be pulled low when USB is unused or not

present.)

USB_VREF A USB voltage reference (Connect to GND through a 0.1 μF capacitor or leave

unconnected when not used.)

USB_RSET A USB resistance set. (This ball should be left unconnected.)

USB_VBUS I/O 5V USB VBUS. USB_VBUS is an output only in peripheral mode during SRP

signaling. Host mode requires that an external voltage source of 5 V at 8 mA or more (per the OTG specification) be applied to VBUS. The voltage source needs to be able to charge and discharge VBUS, thus an ON/OFF switch is required to control the voltage source. A GPIO can be used for this purpose (This ball should be pulled low when USB is unused or not present.)

Port F: GPIO and Multiplexed Peripherals

PF0/PPI D0/DR0PRI /ND_D0A I/O GPIO/PPI Data 0/SPORT0 Primary Receive Data

/NAND Alternate Data 0

PF1/PPI D1/RFS0/ND_D1A I/O GPIO/PPI Data 1/SPORT0 Receive Frame Sync

/NAND Alternate Data 1

PF2/PPI D2/RSCLK0/ND_D2A I/O GPIO/PPI Data 2/SPORT0 Receive Serial Clock

/NAND Alternate Data 2/Alternate Capture Input 0

PF3/PPI D3/DT0PRI/ND_D3A I/O GPIO/PPI Data 3/SPORT0 Transmit Primary Data

/NAND Alternate Data 3

PF4/PPI D4/TFS0/ND_D4A/TACLK0 I/O GPIO/PPI Data 4/SPORT0 Transmit Frame Sync

/NAND Alternate Data 4/Alternate Timer Clock 0

PF5/PPI D5/TSCLK0/ND_D5A/

PF6/PPI D6/DT0SEC/ND_D6A/TACI 0 I/O GPIO/PPI Data 6/SPORT0 Transmit Secondary Data

PF7/PPI D7/DR0SEC/ND_D7A/TACI1 I/O GPIO/PPI Data 7/SPORT0 Receive Secondary Data

PF8/PPI D8/DR1PRI I/O GPIO/PPI Data 8/SPORT1 Primary Receive Data C

PF9/PPI D9/RSCLK1/SPISEL6

PF10/PPI D10/RFS1/SPISEL7

PF11/PPI D11/TFS1/CZM I/O GPIO/PPI Data 11/SPORT1 Transmit Frame Sync/Counter Zero Marker C

PF12/PPI D12/DT1PRI /SPISEL2

PF13/PPI D13/TSCLK1/SPISEL3

PF14/PPI D14/DT1SEC /UART1TX I/O GPIO/PPI Data 14/SPORT1 Transmit Secondary Data/UART1 Transmit C

PF15/PPI D15/DR1SEC/UART1RX/TAC I3 I/O GPIO/PPI Data 15/SPORT1 Receive Secondary Data

TAC LK 1 I/O GPIO/PPI Data 5/SPORT0 Transmit Serial Clock

/NAND Alternate Data 5/Alternate Timer Clock 1

/NAND Alternate Data 6/Alternate Capture Input 0

/NAND Alternate Data 7/Alternate Capture Input 1

I/O GPIO/PPI Data 9/SPORT1 Receive Serial Clock/SPI Slave Select 6 D

I/O GPIO/PPI Data 10/SPORT1 Receive Frame Sync/SPI Slave Select 7 C

/CDG I/O GPIO/PPI Data 12/SPORT1 Transmit Primary Data/SPI Slave Select 2/Counter

Down Gate

/CUD I/O GPIO/PPI Data 13/SPORT1 Transmit Serial Clock/SPI Slave Select 3/Counter Up

Direction

/UART1 Receive /Alternate Capture Input 3

Typ e

Rev. C | Page 23 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 10. Signal Descriptions (Continued)

Driver

Signal Name Type Function

Port G: GPIO and Multiplexed Peripherals

PG0/HWAIT I/O GPIO/Boot Host Wait2 C

PG1/SPISS

PG2/SCK I/O GPIO/SPI Clock D

PG3/MISO/DR0SECA I/O GPIO/SPI Master In Slave Out/Sport 0 Alternate Receive Data Secondary C

PG4/MOSI/DT0SECA I/O GPIO/SPI Master Out Slave In/Sport 0 Alternate Transmit Data Secondary C

PG5/TMR1/PPI_FS2 I/O GPIO/Timer1/PPI Frame Sync2 C

PG6/DT0PR IA/TMR2/PPI_FS3 I/O GPIO/SPORT0 Alternate Primary Transmit Data / Timer2 / PPI Frame Sync3 C

PG7/TMR3/DR0PRIA/UART0T X I/O GPIO/Timer3/Sport 0 Alternate Receive Data Primary/UART0 Transmit C

PG8/TMR4/RFS0A/UART0RX/TAC I4 I/O GPIO/Timer 4/Sport 0 Alternate Receive Clock/Frame Sync

PG9/TMR5/RSCLK0A/TACI 5 I/O GPIO/Timer5/Sport 0 Alternate Receive Clock

PG10/TMR6/TSCLK0A/TAC I6 I/O GPIO/Timer 6

PG11/TMR7/HOST_WR

PG12/DMAR1/UART1TXA/HOST_ACK I/O GPIO/DMA Request 1/Alternate UART1 Transmit/Host DMA Acknowledge C

PG13/DMAR0/UART1RXA/HOST_ADDR/TAC I2 I/O GPIO/DMA Request 0/Alternate UART1 Receive/Host DMA Address/Alternate

PG14/TSCLK0A1/MDC/HOST_RD

PG15

Port H: GPIO and Multiplexed Peripherals

PH0/ND_D0/MIICRS/RMIICRSDV/HOST_D0 I/O GPIO/NAND D0/Ethernet MII or RMII Carrier Sense/Host DMA D0 C

PH1/ND_D1/ERxER/HOST_D1 I/O GPIO/NAND D1/Ethernet MII or RMII Receive Error/Host DMA D1 C

PH2/ND_D2/MDIO/HOST_D2 I/O GPIO/NAND D2/Ethernet Management Channel Serial Data/Host DMA D2 C

PH3/ND_D3/ETxEN/HOST_D3 I/O GPIO/NAND D3/Ethernet MII Transmit Enable/Host DMA D3 C

PH4/ND_D4/MIITxCLK/RMIIREF_CLK/HOST_D4 I/O GPIO/NAND D4/Ethernet MII or RMII Reference Clock/Host D4 C

PH5/ND_D5/ETxD0/HOST_D5 I/O GPIO/NAND D5/Ethernet MII or RMII Transmit D0/Host DMA D5 C

PH6/ND_D6/ERxD0/

PH7/ND_D7/ETxD1/HOST_D7 I/O GPIO/NAND D7/Ethernet MII or RMII Transmit D1/Host DMA D7 C

PH8/SPISEL4

PH9/SPISEL5

PH10/ND_CE

PH11/ND_WE/ETxD3/HOST_D11 I/O GPIO/NAND Write Enable/Ethernet MII Transmit D3/Host DMA D11 C

PH12/ND_RE

PH13/ND_BUSY/ERxCLK/HOST_D13 I/O GPIO/NAND Busy/Ethernet MII Receive Clock/Host DMA D13 C

PH14/ND_CLE/ERxDV/HOST_D14 I/O GPIO/NAND Command Latch Enable/Ethernet MII or RMII Receive Data Valid/

PH15/ND_ALE/COL/HOST_D15 I/O GPIO/NAND Address Latch Enable/Ethernet MII Collision/Host DMA Data 15 C

/SPISEL1 I/O GPIO/SPI Slave Select Input/SPI Slave Select 1 C

/UART0 Receive/Alternate Capture Input 4

/Alternate Capture Input 5

/Sport 0 Alternate Transmit

/Alternate Capture Input 6

I/O GPIO/Timer7/Host DMA Write Enable C

Capture Input 2

I/O GPIO/SPORT0 Alternate 1 Transmit/Ethernet Management Channel Clock

/Host DMA Read Enable

/TFS0A/MII PHYINT/RMII MDINT/HOST_CE I/O GPIO/SPORT0 Alternate Transmit Frame Sync/Ethernet/MII PHY Interrupt/RMII

Management Channel Data Interrupt/Host DMA Chip Enable

HOST_D6 I/O GPIO/NAND D6/Ethernet MII or RMII Receive D0/Host DMA D6 C

/ERxD1/HOST_D8/TACLK2 I/O GPIO/Alternate Timer Clock 2/Ethernet MII or RMII Receive D1/Host DMA D8

/SPI Slave Select 4

/ETxD2/HOST_D9/TACLK3 I/O GPIO/SPI Slave Select 5/Ethernet MII Transmit D2/Host DMA D9

/Alternate Timer Clock 3

/ERxD2/HOST_D10 I/O GPIO/NAND Chip Enable/Ethernet MII Receive D2/Host DMA D10 C

/ERxD3/HOST_D12 I/O GPIO/NAND Read Enable/Ethernet MII Receive D3/Host DMA D12 C

Host DMA D14

Typ e

Rev. C | Page 24 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 10. Signal Descriptions (Continued)

Driver

Signal Name Type Function

Port J: Multiplexed Peripherals

PJ0 : PP I_F S1/ TMR0 I/O PPI Frame Sync1/Timer0 C

PJ1 : PP I_C LK/ TMRCLK I PPI Clock/Timer Clock

PJ2: SCL I/O 5V TWI Serial Clock (This pin is an open-drain output and requires a pull-up

PJ3: SDA I/O 5V TWI Serial Data (This pin is an open-drain output and requires a pull-up

resistor.

)

Real Time Clock

RTXI I RTC Crystal Input (This ball should be pulled low when not used.)

RTXO O RTC Crystal Output (Does not three-state during hibernate.)

JTAG Port

TCK I JTAG Clock

TDO O JTAG Serial Data Out C

TDI I JTAG Serial Data In

TMS I JTAG Mode Select

TRST

EMU

I JTAG Reset (This ball should be pulled low if the JTAG port is not used.)

O Emulation Output C

Clock

CLKIN I Clock/Crystal Input

XTAL O Crystal Output (If CLKBUF is enabled, does not three-state during hibernate.)

CLKBUF O Buffered XTAL Output (If enabled, does not three-state during hibernate.) C

Mode Controls

RESET

I Reset

NMI I Nonmaskable Interrupt (This ball should be pulled high when not used.)

BMODE3–0 I Boot Mode Strap 3-0

ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation I/F

SEL

/EXT_WAKE1 O External FET Drive/Wake up Indication 1 (Does not three-state during

OUT

I Internal/External Voltage Regulator Select

hibernate.)

EXT_WAKE0 O Wake up Indication 0 (Does not three-state during hibernate.) C

SS/PG

A Soft Start/Power Good

ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation I/F

EXT_WAKE1 O Wake up Indication 1 (Does not three-state during hibernate.) C

EXT_WAKE0 O Wake up Indication 0 (Does not three-state during hibernate.) C

A Power Good (This signal should be pulled low when not used.)

Typ e

Rev. C | Page 25 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

Table 10. Signal Descriptions (Continued)

Driver

Signal Name Type Function

Power Supplies ALL SUPPLIES MUST BE POWERED

See Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527

Processors on Page 29, and see Operating Conditions for ADSP-BF522/ ADSP-BF524/ADSP-BF526 Processors on Page 27.

DDEXT

DDINT

DDRTC

DDUSB

DDMEM

DDOTP

PPOTP

PI/O Power Supply

P Internal Power Supply

P Real Time Clock Power Supply

P 3.3 V USB Phy Power Supply

PMEM Power Supply

POTP Power Supply

P OTP Programming Voltage

GND G Ground for All Supplies

See Output Drive Currents on Page 72 for more information about each driver type.

HWAIT must be pulled high or low to configure polarity. It is driven as an output and toggle during processor boot. See Booting Modes on Page 18.

When driven low, this ball can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as MII PHYINT. If the ball is

used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the ball with a resistor.

Consult version 2.1 of the I2C specification for the proper resistor value.

Typ e

Rev. C | Page 26 of 88 | March 2012

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527

SPECIFICATIONS

Specifications are subject to change without notice.

OPERATING CONDITIONS FOR ADSP-BF522/ADSP-BF524/ADSP-BF526 PROCESSORS

Parameter Conditions Min Nominal Max Unit

DDINT

DDEXT

DDRTC

DDMEM

DDOTP

PPOTP

DDUSB

IHTWI

ILTWI

Must remain powered (even if the associated function is not used).

If not used, power with V

Balls that use V

to voltages higher than V

The V

PPOTP

on voltage and junction temperature) over the lifetime of the part. Please see Table 30 on Page 37 for details.

When not using the USB peripheral on the ADSP-BF524/ADSP-BF526 or terminating V

Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF52x processors are

3.3 V tolerant (always accept up to 3.6 V maximum VIH). Voltage compliance (on outputs, VOH) is limited by the V

Parameter value applies to all input and bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, and SCL.

The V

IHTWI

SDA and SCL are pulled up to V

Internal Supply Voltage 1.235 1.47 V External Supply Voltage External Supply Voltage External Supply Voltage RTC Power Supply Voltage MEM Supply Voltage1, MEM Supply Voltage1, MEM Supply Voltage1, OTP Supply Voltage OTP Programming Voltage

1.7 1.8 1.9 V

2.25 2.5 2.75 V

33.33.6V

2.25 3.6 V

1.7 1.8 1.9 V

2.25 2.5 2.75 V

33.33.6V

2.25 2.5 2.75 V

For Reads 2.25 2.5 2.75 V For Writes USB Supply Voltage High Level Input Voltage High Level Input Voltage High Level Input Voltage High Level Input Voltage V Low Level Input Voltage Low Level Input Voltage Low Level Input Voltage Low Level Input Voltage V Junction Temperature 289-Ball CSP_BGA

Junction Temperature 208-Ball CSP_BGA

DDMEM

voltage for writes must only be applied when programming OTP memory. There is a finite amount of cumulative time that this voltage may be applied (dependent

min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See V

6, 7

DDEXT/VDDMEM

DDEXT

DDEXT/VDDMEM

DDEXT

= 1.90 V 1.1 V = 2.75 V 1.7 V = 3.6 V 2.0 V

= 1.90 V/2.75 V/3.6 V 0.7 × V

= 1.7 V 0.6 V = 2.25 V 0.7 V = 3.0 V 0.8 V

= Minimum 0.3 × V

6.9 7.0 7.1 V

3.0 3.3 3.6 V

BUSTWI

0+105°C

=0°C to +70°C

AMBIENT

0+105°C

=0°C to +70°C

AMBIENT

–40 +105 °C

DDEXT

are DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AOE, AMS3–0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls are not tolerant

DDMEM

BUSTWI

. See Table 11.

= –40°C to +85°C

AMBIENT

on the ADSP-BF522, V

DDUSB

must be powered by V

DDUSB

supply voltage.

DDEXT

min and max values in Table 11.

BUSTWI

DDEXT

Rev. C | Page 27 of 88 | March 2012

+ 61 hidden pages

ANALOG DEVICES ADSP-BF522, ADSP-BF523, ADSP-BF524, ADSP-BF525, ADSP-BF526 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

MEMORY

FEATURES

PERIPHERALS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

PORTABLE LOW POWER ARCHITECTURE

SYSTEM INTEGRATION

PROCESSOR PERIPHERALS

BLACKFIN PROCESSOR CORE

MEMORY ARCHITECTURE

Internal (On-Chip) Memory

External (Off-Chip) Memory

NAND Flash Controller (NFC)

One-Time Programmable Memory

I/O Memory Space

Booting

Event Handling

Core Event Controller (CEC)

System Interrupt Controller (SIC)

Event Control

DMA CONTROLLERS

HOST DMA PORT

REAL-TIME CLOCK

WATCHDOG TIMER

TIMERS

UP/DOWN COUNTER AND THUMBWHEEL INTERFACE

SERIAL PORTS

SERIAL PERIPHERAL INTERFACE (SPI) PORT

UART PORTS

TWI CONTROLLER INTERFACE

10/100 ETHERNET MAC

PORTS

General-Purpose I/O (GPIO)

PARALLEL PERIPHERAL INTERFACE (PPI)

General-Purpose Mode Descriptions

Input Mode

Frame Capture Mode

Output Mode

ITU-R 656 Mode Descriptions

Active Video Mode

Vertical Blanking Interval Mode

Entire Field Mode

USB ON-THE-GO DUAL-ROLE DEVICE CONTROLLER

CODE SECURITY WITH LOCKBOX SECURE TE CH N O LO G Y

DYNAMIC POWER MANAGEMENT

Full-On Operating Mode—Maximum Performance

Active Operating Mode—Moderate Dynamic Power Savings

Sleep Operating Mode—High Dynamic Power Savings

Deep Sleep Operating Mode—Maximum Dynamic Power Savings

Hibernate State—Maximum Static Power Savings

Power Savings

ADSP-BF523/ADSP-BF525/ADSP-BF527 VOLTAGE REGULATION

ADSP-BF522/ADSP-BF524/ADSP-BF526 VOLTAGE REGULATION

CLOCK SIGNALS

BOOTING MODES

INSTRUCTION SET DESCRIPTION

DEVELOPMENT TOOLS

EZ-KIT Lite Evaluation Board

DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD (TARGET)

RELATED DOCUMENTS

LOCKBOX SECURE TECHNOLOGY DISCLAIMER

RELATED SIGNAL CHAINS

SIGNAL DESCRIPTIONS

SPECIFICATIONS

OPERATING CONDITIONS FOR ADSP-BF522/ADSP-BF524/ADSP-BF526 PROCESSORS